JPH09147597A - Memory integrated circuit chip, its preparation and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for testing a memory cell which assures highly efficient test and a semiconductor IC having complicated circuit topology. SOLUTION: A memory integrated circuit of previously specified circuit topology has an on-chip topology logical driver 50. A topology logical driver 50 selectively inverts the data written into the address memory cell in the memory IC and read from the memory cell depending on the position of the addressed memory cell in the circuit topology of the memory array 32. The topology logical driver 50 is preferably a logical circuit for embodying a pool function for specifying the circuit topology.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory integrated circuit having an on-chip topology decoding circuit. The invention also relates to a method for testing and manufacturing such a circuit.

[0002]

Memory integrated circuit (IC)
s) has a memory array of millions of memory cells used to store charges representing binary data. For example, the presence of charge in a memory cell is generally the same as a binary value of "1", and the absence of charge is generally equal to a binary value of "0". It is a thing. Memory cells are accessed via address signals on the column and row lines. When accessed, data is written to or read from the addressed memory cell via the digit or bit line. The memory cells, column lines, and row lines in a memory array are arranged in a particular layout or shape, commonly referred to as a circuit "topology." Circuit topologies differ significantly between various designed memory ICs. One common design found in many memory circuit topologies is the "folded bit line" structure.
In the folded bitline structure, the bitlines are arranged in pairs and each pair is assigned a complementary binary value signal. For example, one bit line in the pair is dedicated to the binary signal DATA and the other bit line is complementary 2
Dedicated to the decimal signal DATA ^* . (The asterisk * sign is used to indicate the binary complement.)

The memory cells are connected to any of the bit lines in the folded pair. During read and write operations, the bit lines are driven at opposite voltage levels depending on the data content written to or read from the memory cell. For convenience of explanation, in the following description, a read operation of a memory cell holding a charge showing a binary value “1” will be described. The potentials on both bit lines in the pair are initially brought to an intermediate voltage level such as 2.5 volts. The addressed memory cell is then accessed and the charge held therein is transferred to one of the bit lines, raising the voltage on that bit line slightly above one of the pairs. A sense amplifier, or similar circuit, senses the voltage difference on the bit line pair and increases the voltage on the first bit line to, for example, 5 volts, and 2
This voltage difference is increased by reducing the voltage on the th bit line to, for example, 0 volts. This outputs the data in a complementary form to the folded bit line.

One example of a folded bitline structure is a twisted bitline structure. FIG. 1 shows a bit pair D0 flipped or twisted at a connection point 20 across the array.
Figure 4 shows a twisted bit line structure with / D0 ^* -D3 / D3 ^* . The memory cells are connected to the bit line pairs through the array. Bit line pair D0 / D
Representative memory cells 22a-22n and 24a-24n connected to 0 ^* are shown. The twisted bit line structure is derived from the technique of reducing bit-line interference noise during chip operation. Such noise becomes more serious as the memory size increases. Therefore, the twisted bit line structure is 64 mega DRA
M (Dynamic Random Access M)
It is used for large memory such as memory.

The twisted bit line structure has a more complex topology than the simple folded bit line structure.
Accessing the memory cells of the layout of FIG. 1 is more complicated. For example, different addresses are used for memory cells on either side of twisted connection point 20. As the memory capacity of the memory ICs increases, and further, the size thereof is maintained or decreased, other noise problems and layout restrictions are unavoidably required to make the shape more complicated. As a result, the topology of these circuits becomes even more complex, and the complexity of each layer is more difficult to mathematically express because it adds another term to the equation representing the topology. This makes the addressing mechanism more complicated.

One problem with memory ICs is the test procedure. It is becoming increasingly difficult to test memory ICs with complex topologies. To test ICs, memory manufacturers use test equipment programmed by the manufacturer with complex Boolean functions that represent the topology of memory ICs. This Boolean function was created by the manufacturer. Conventional test equipment is capable of handling up to 6-bit addresses. As the topology becomes more complex, for some test patterns a 6-bit address is not sufficient to address individual cells. This renders the test equipment ineffective. Moreover, if the user repairs a particular memory device after a period of use, it will be very difficult to enter the required Boolean function into the test equipment without consulting the manufacturer.

Test problems become even more apparent when a form of compression is used during the test to speed up the test period. It is common to write all "1" or "0" test patterns simultaneously to a group of memory cells. Consider the case of writing an all "1" test pattern to a memory cell in the twisted bit line pair of FIG. 1 as in the following example. During test compression, all four bit line pairs D0 / D0 ^* , D
One bit is used for 1 / D1 ^* , D2 / D2 ^* , and D3 / D3 ^* . In such a conventional address mechanism, since the memory cell receives "1",
In every memory cell, it is not possible to tell from a single address bit whether or not it should have the binary value "1" or "0" placed on the bit line connected to the memory cell. It is impossible to put "1" in. Therefore, memory ICs having complicated topologies
On the other hand, the test equipment cannot fully test.
On the contrary, since the test period is too long, the memory I
Testing C is not desirable.

An object of the present invention is to provide a memory cell capable of efficiently performing such a test, and a method for testing semiconductor ICs having a complicated circuit topology.

[0009]

The present invention is a built-in type,
Semiconductor memory IC having on-chip topology circuit
Is provided. The memory IC includes a memory array of predefined circuit topology having a plurality of memory cells and a number of access lines connected to associated memory cells. The address decoder provides an address for selectively accessing one or more memory cells in the memory array. Also I
The / O buffer temporarily holds data written to and read from the memory cells in the memory array. The read / write controller manages the data write operation and the data read operation, and transfers the data between the I / O buffer and the addressed memory cell.

The on-chip topological logic driver is
The data written to and read from the addressed memory cell is selectively inverted. The topology logic driver selectively inverts the data for a particular addressed memory cell based on the location of the addressed memory cell within the circuit topology of the memory array and the data for other addressed memory cells. Do not flip. In the preferred embodiment, the topology logic driver includes a combination of logic gates that implements a Boolean function of selected bits in an address, the Boolean function defining the circuit topology of the memory array.

The present invention also provides a method for testing and manufacturing such a memory.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 shows a semiconductor memory IC chip 30 constructed according to the present invention. The memory IC 30 includes a memory array 32 and data I /
It includes an O buffer 34, an address decoder 36, and a read / write controller 38. Memory array 3
2 is composed of many memory cells arranged in a predefined circuit topology. These memory cells are
Column address signals CA0-CAJ and row address signal R
Addressable via A0-RAK. Address decoder 36 receives row and column addresses from an external source (microprocessor or computer) and also decodes addresses for use on chip. Internal row and column addresses are carried on address bus 40. Address decoder 36 thus provides addresses (row and column addresses) for selectively accessing one or more memory cells in the memory array. The data I / O buffer 34 temporarily holds the data read from or written in the memory cells in the memory array. The data I / O buffers, which may also be referred to as DQ buffers, are data D0-D.
It is connected to the memory array 32 via a data bus 42 carrying L. The read / write controller 38 uses the I / O
In order to generate timing and control signals used to manage data write and data read operations that effect data transmission between the buffer 34 and the memory cells,
It is connected to the memory array 32 and the data I / O buffer 34. In this way, the data I / O buffer and the read / write controller 38 use the data I / O for reading and writing data to and from the selected bit line.
The O means is efficiently formed.

The memory IC 30 also includes an address bus 40.
And an on-chip topology logic driver 50 connected to the memory cell 32. The topology logic driver provides one or more inverted signals that selectively invert the data written and read on the I / O data bus 42, taking into account the complexity in the circuit topology of the IC. Output. The topology logic driver selectively inverts the data for a particular addressed memory cell and not the data for other memory cells based on the location of the addressed memory cell within the circuit topology of the memory array.

To illustrate various features of the present invention, in the illustrated embodiment, the topology logic driver 50 includes two complementary signal sets EVINV / EV.
The inverted signal is output in the format of INV ^* and ODINV / ODINV ^* . Complementary EVINV / EVINV ^* signals are used to prevent inversion or even inversion of even bits of data transmitted to and on the data bus 42 to the memory array. Similarly, the complementary ODINV / ODINV ^* signals are used to alternately invert or not invert the odd bits of data. These complementary signals are described in more detail below.

Topology logic driver 50 is a different IC
Specially designed for layout. That is, the topology logic driver 50 is configured with special consideration of the specific topology design of the memory IC. Therefore,
The topology logic driver 50 is configured differently for various memory ICs. The logic driver is preferably configured as a logic circuit that represents a Boolean function that defines the circuit topology of a given memory array. By designing the topology logic driver on the memory IC chip, it is not necessary to specially program the test device to test the memory ICs with a complex Boolean function for each test of different memory ICs. Memory ICs can automatically implement topology adjustments without consideration by the manufacturer or user.

The present invention will now be described with respect to the contents of a 64M DRAM as an example. In addition, a preferable configuration of the topology logic driver 50 will be described in detail.

FIG. 3 shows a part of the memory array 32 of FIG. The memory portion is composed of a first memory block 52 and a second memory block 54. Each memory block has a large number of memory cells arranged in an array connected to the intersections of the row access lines and the column access lines. The first memory block 52 is connected between two sets of low voltage, N and P sense amplifiers 56 and 58. Similarly, the second memory block 54 is connected between two sets of N and P sense amplifiers 56 and 60. The sense amplifiers are connected to column access lines 62, also referred to as bit or digit lines. The column access line 62 is connected to the address decoder 36.
Selected by the column decode circuit 64, which regionally decodes the column address received from (FIG. 2).

Each memory block 52 and 54 is connected to an odd column decoding circuit 66 and 68 and an even column decoding circuit 70 and 72, respectively. These decode circuits are also referred to as word lines, row access lines 74.
It is connected to the. The row decode circuit selects the row line 74 to access the memory cells in the memory array block based on the address received from the address decoder 36.

The memory array block 52 is shown in more detail in FIG. The memory array block has a plurality of memory cells (shown by small boxes) operatively connected to the intersections of row access lines 74 and column access lines 62. The column access lines are arranged in pairs to form bit line pairs. 2 of 4 bit line pairs
One set is a bit line pair D0 / D
0 ^* , D1 / D1 ^* , D2 / D2 ^* , and D3 / D3
It is illustrated as including ^* . The upper or first set of bit line pairs is the column address bit CA2 = 0.
And the lower or second set of bit line pairs is selected by the column address bit CA2 = 1.

Even bit line pairs D0 / D0 ^* and D2 /
D2 ^* is connected to the left or even first sense amplifier 56. Odd bit line pair D1 / D1 ^* and D3
/ D3 ^* is connected to the right or odd first sense amplifier 58. Even or odd sense amplifiers are alternately selected by the least significant bit of column address CA0.
Note that CA = 0 selects the even first sense amplifiers 56, and CA = 1 selects the odd first sense amplifiers 58. Four even bit line pairs D0 / D0 ^* and D2
/ D2 ^* is further connected to the two sets of I / O lines in front of the second DC sense amplifier 80. Similarly, four odd bit line pairs D1 / D1 ^* and D3 /
D3 ^* is further connected to two different sets of I / O lines which are connected to the second DC sense amplifier 82. The second DC sense amplifiers 80 and 82 are connected to the data I / O buffer (not shown in FIG. 4) via the same data line.

The DC sense amplifier 80 has the incoming inverted signals INV0 and INV1, and the DC sense amplifier 82 is connected to receive the inverted signals INV2 and INV3. These signals are generated by the topology logic driver 50 (FIG. 2). These independent inverted signals are generated by the bit lines D0 / D0 ^* , D1 / D.
The data on 1 ^* , D2 / D2 ^* , and D3 / D3 ^* can be inverted separately. As another embodiment, less than four inversion signals may be used. In the exemplary circuit topology, described in more detail below with reference to FIG. 5, even bit lines D0 and D2
It can be seen that the even data bits placed above are the same in the array, and the odd data bits placed on the odd bit lines D1 and D3 are the same. Therefore, two inversion signals, even inversion EVINV and odd inversion ODINV
Can be used in place of the four shown inversion signals INVO-INV3.

The individual bit line pairs are twisted line structures, with the bit lines within the bit line pairs intersecting other bit lines within other bit line pairs at twist connections 76 in the middle of the memory array block. Preferably, the twisted configuration can include a superposition of bit lines from two bit line pairs.

Row line 74 is used to access the individual memory cells connected to the selected row.
The even rows 512, 514, ... 768, 770, etc. are connected to the even row decoder circuit 70, and the odd rows 513, 5
15, ... 769, 771, ... are connected to the row decoder circuit 66. The memory cell on the left side of the twisted connection 76 is
Row address bits RA8 = 0 are addressed and the memory cells to the right of twisted connection 76 are addressed via row address bits RA8 = 1. Some memory cells in the array block are spare memory cells. For example, the memory cells connected to rows 512 and 768 are spare memory cells. Such cells are used in place of defective memory cells in the array detected during testing. A method of testing one preferred memory IC with on-chip topology logic driver is described next. The process for replacing defective memory cells with spare memory cells is done using conventional, known techniques.

The IC layout shown in FIG. 4 is a 64M DRAM.
3 shows a specific example of the circuit topology of FIG. Given this circuit topology, the topology logic driver 50 can be derived for this DRAM.
The special derivation of DRAM will be described in detail with reference to FIGS.

FIG. 5 is a table showing the circuit topology of the array block 52. This table shows row R51 on the left side of the twist
2, R513, R514 and R515, and also to the right of the twist in rows R768, R769, R770 and R771.
Contains. The table is generated by verification of the circuit topology for memory cell locations and the assumption that a binary value "1" has been written for all memory cells in array block 52.

Consider a memory cell connected to row R512. This row is addressed by RA8 = 0, RA1 = 0, and RA0 = 0. The upper side of the set of bit line pairs is addressed by CA2 = 0. Array block 5 for bit line pair D1 / D1 ^*
The memory cells on row R512 in 2 (FIG. 4) are connected to bit line D1. Therefore, in the table, the binary value "1" must be written to the bit line D1 in order to place the data value "1" in the memory cell. For bit line pair D0 / D0 ^* , the memory cells on row R512 are connected to bit line D0 ^* . Therefore, in the table, the binary value "0" must be written to bit line D0 to put a data value of "1" in the memory cell (ie, this is the binary value to complementary bit line D0 ^* It is the same as writing "1"). The table is completed in this way.

Here, some data in the table are binary values "0" even if the test patterns are all "1". This is due to the given circuit topology, which requires the input of "0" or the complementary inversion of the binary value "1" to store the binary value "1" in the desired cell. is there.

With this circuit topology, the even data bits placed on even bit lines D0 and D2 are the same throughout the array. Similarly, the odd data bits placed on the odd bit lines D1 and D3 are the same throughout the array. Therefore, two complementary signal pairs can be used to selectively invert even and odd bits of data for the inputs to the memory cells. These complementary inversion signals are EVINV / EVINV ^* and ODINV / as shown in FIG.
ODINV ^* , EVINV / EVINV ^* is for inverting even bits, and also ODINV / ODINV
^* Is used to invert the odd bits respectively.

The Boolean functions of the inverted signals EVINV and ODINV for the exemplary topology circuit of FIG. 4 can be derived from the table of FIG. 5 as follows.

[0030]

[Table 1] EVINV = [(RA8 * x RA0 * x RA1 *) + (RA8 * x RA0 x RA1) + (RA8 x RA0 * x RA1 *) + (RA8 x RA0 x RA1)] x CA2 * + [ (RA8 * x RA0 x RA1 *) + (RA8 * x RA0 * x RA1) + (RA8 x RA0 x RA1 *) + (RA8 x RA0 * x RA1)] x CA2 = (RA0 * x RA1 * + RA0 x RA1) × CA2 * + (RA0 × RA1 * + RA0 * × RA1) × CA2 * ODINV = [(RA8 * × RA0 × RA1 *) + (RA8 * × RA0 * × RA1) + (RA8 × RA0 * × RA1 *) + (RA8 x RA0 x RA1)] x CA2 * + [(RA8 * x RA0 * x RA1 *) + (RA8 * x RA0 x RA1) + (RA8 x RA0 x RA1 *) + (RA8 x RA0 * × RA1)] × CA2 = [RA8 * × (RA0 + RA1) + RA8 × (RA0 + RA1) *] × CA2 * + [RA8 * × (RA0 + RA1) * + RA8 × (RA0 + RA1)] × CA2

FIGS. 6 and 7 show a circuit for implementing these Boolean functions for generating the inverted signals EVINV and ODINV based on the row address and the column address. These circuits are the 64M D
It is part of the topology logic driver 50 for RAM. The topology logic driver includes an overall or general topology decoding circuit 100 (FIG. 6) and a number of regional topology decoding circuits 110 (FIG. 7) connected to the general topology decoding circuit 100.

General-purpose topology decoding circuit 100 of FIG.
Are preferably located in the center of the memory array. This circuit includes row address signals RA0, RA0 ^* , RA1,
An area of memory cells is identified in the memory array for possible data conversions based on the functions RA1 ^* , RA8, RA8 ^* . General-purpose topology decoding circuit 1
00 receives the two least significant bits RA0, RA1 and their complements (signals) for exclusive OR (X
OR) gate 102. These row address bits are used to select a particular row line.
The output of the XOR function is the general-purpose even bit conversion signal GEVI.
Inverted to generate NV. AND gate 104
The result of the XOR function is combined with the address bits RA8 and RA8 ^* by the combination of. These row address bits are used to select memory cells on either side of twisted junction 76. The result of this logic is a general purpose odd bit inversion signal GODINV.

A number of area topology decoding circuits, such as circuit 110 of FIG. 7, are provided to identify a particular area of a memory cell for possible data conversion through the array. Each area topology decoding circuit 11
0 consists of two XOR gates 112 and 114, which achieve the XOR function of the general inverted signals GEVINV and GODINV and the column address signals CA2 and CA2 ^* . The column address signals CA2 and CA2 ^* are used to select a particular set of bit line pairs D0 / D0 ^* -D3 / D3 ^* . The circuit 110 outputs the inversion signals EVINV and ODINV used in the array block of the area.

FIG. 8 shows EVINV / E in the memory array.
The VINV ^* signal is transferred to the internal even bit line pair (ie,
2 shows an even bit inverting I / O circuit 120 for interfacing with D0 / D0 ^* and D2 / D2 ^* ). The inverting I / O circuit 120 is shown connected to the bit line pair D0 / D0 ^* for convenience of explanation. This circuit is
It functions to invert the read and written data on the bit line pair D0 / D0 ^* . ODINV / O
The DINV ^* signal is transferred to the internal odd bit line pair (ie,
Since the odd bit inverting I / O circuits for interfacing D1 / D1 ^* and D3 / D3 ^* ) are similar, only circuit 120 will be described in detail here. Inversion I
The / O circuit 120 is part of the topology logic driver 50.

The even bit inversion I / O circuit 120 receives the ENINV and EVI signals from the area topology decoding circuit 110.
It has an XOR gate 124 which receives the NV ^* signal. The I / O circuit 120 includes a crossover transistor array or data inverter 126 and a write driver 128. The I / O circuit 120 is connected to the DC sense amplifier 122. Data is transmitted to or from the bit line pair D0 / D0 ^* via the data read line DR / DR ^* and the sense amplifier 122. The data read line DR / DR ^* is the data I
It is connected to the / O buffer 34 (FIG. 2). Data is written or read depending on the data write control signal DW which is an input to the XOR gate 124. The output of the XOR gate 124 is the write driver 12
8 is controlled.

The EVINV / EVINV ^* signal is connected to a crossover transistor array or data inverter 126. If the data is inverted, EVI
The NV signal goes high and the EVINV signal goes low. As a result, the data inverter 126 causes the data line D0 / D
Flip data to or from 0 ^* . vice versa,
If the data is not inverted, the EVINV ^* signal will be low and the EVINV signal will be high. As a result, the data inverter 126 holds the same data as it is without inverting it.

The on-chip topology logic driver, which includes general topology circuit 100 (FIG. 6), region topology circuit 110 (FIG. 7), and inverting I / O circuit 120 (FIG. 8), is a function of row and column addresses. Depends on
Efficiently inverts data for a particular memory cell.
In the above example, the logic driver has row bits RA0, RA0.
^* , RA1, RA1 ^* , RA8, RA8 ^* and column bit C
It operates based on the functions of A2 and CA2 ^* . By using the address bits, the logic driver can take into account any circuit topology, including twisted bit line structures. In this way, the topology logic driver can implement other means, but read data from the addressed memory cell based on the location of the addressed memory cell in the circuit topology of the memory array. It defines a data inversion means that can efficiently invert the data that is written to or written to it.

Although a particular preferred embodiment for a 64M DRAM has been described above, the present invention is not so limited and can be used with all other circuit topologies. For example, the same is applicable to the case where the circuit topology is a twisted line structure, a mirror configuration of a complicated memory block, or a more complicated twisted bit line architecture.

The present invention also relates to a method for manufacturing a memory integrated circuit chip having an on-chip topological logic driver. This method firstly selects and selects an integrated circuit chip having a predetermined circuit topology.
Includes designing. Then, a Boolean function representing the circuit topology of the modified circuit is determined. Thereafter, a topological logic circuit embodying the determined Boolean function is formed on the integrated circuit chip.

The memory IC of the present invention is superior to prior art memory ICs in that it has an integrated, on-chip topology circuit. The on-chip topology logic driver selectively inverts the data written to or read from the addressed memory cell based on the location of the addressed memory cell in the circuit topology of the memory array. The use of this predefined topology circuit eliminates the need for Boolean programming of the test equipment for a particular memory IC at the manufacturer or user. Instead, each memory IC
Has its own internal address decoder that takes into account any complex circuit topology. In the test equipment,
It suffices to write the test pattern data to the memory array without considering whether the data is inverted due to topological reasons.

Another advantage of the new on-chip topology decoding circuit is that it facilitates testing of memory arrays. On-chip topology circuits are particularly useful in a compressed mode of testing where many test bits are simultaneously written to and read from memory cells in the array.
Therefore, another aspect of the present invention relates to a method for testing a memory integrated circuit chip having a predetermined circuit topology and an on-chip topology decoding circuit. The method is shown in FIGS.
It will be described with reference to a particular embodiment of a RAM.

FIG. 9 illustrates the test method of the present invention. The first step 200 is to access a group of memory cells in a memory array. One possible group of memory cells is memory array block 52 in FIG. Then, the selected number of bits of test data are simultaneously written to the group of accessed memory cells according to the test pattern (step 202). Examples of test patterns are all binary "1", all binary "0", checkerboard patterns with alternating "1" and "0", or other possible "1" and "0". It is a combination of "0".

On-chip topological logic drivers can accommodate large numbers of data bits written simultaneously. For example, 128 times compression (i.e., writing 128 bits simultaneously) or more can be done using the circuitry of the present invention. This test performance exceeds the capabilities of the test equipment. Since the four second amplifiers are connected to one data line, the test equipment can write the same data to all four write drivers in the second amplifiers 80 and 82. However, from the table of FIG. 5, D1 and D3 actually write the same data to the memory cell, whereas D0 and D2 must be in opposite states. Therefore, the data on two of the four I / O lines must be inverted. External test equipment cannot handle such situations. The on-chip topology circuit of the present invention, however, can handle this condition and can easily accommodate maximum test address compression, which selects all read / write drivers simultaneously.

The next step 204 is to internally locate the particular memory cell in the accessed group that must receive the inverted data to test the pattern for the given circuit topology of the memory array. . In the table of FIG. 5, the data applied to the upper bit lines D0 and D2 in row R512 (CA2 = 0) is as follows.
It must be inverted to ensure that the all "1" test pattern is actually written to the memory cell. In step 206, the bits of test data written to the particular memory cell are selectively inverted based on their position in the circuit topology. The remaining bits of test data written to other memory cells (such as upper bit lines D1 and D3 in row R512) are not inverted.

Following the write and invert steps, test data is then read from the accessed group of memory cells (step 208). The test data that was previously inverted and written to the particular designated memory cell is selectively inverted again on-chip to return to their desired state (step 210). Then, to determine whether the memory integrated circuit has a defective memory cell, the bits of test data read from the group of accessed memory cells are compared to the test data written to the group of accessed memory cells. Is compared with a bit.

[0046]

As described above, according to the present invention, there are provided a memory cell which can be efficiently tested, and a method for efficiently testing a semiconductor IC having a complicated circuit topology. Although the present invention has been described above with reference to specific embodiments, the present invention is not limited to these specific embodiments. The scope of the present invention is defined based on the claims.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a circuit topology having a folded and twisted bit line structure.

FIG. 2 is a block diagram of a memory integrated circuit constructed in accordance with the present invention, the memory integrated circuit having a memory array and a topology logic driver.

FIG. 3 is a block diagram illustrating two memory array blocks in the memory array of FIG.

FIG. 4 is a block diagram of a preferred circuit topology for the memory array block of FIG. 3 according to one embodiment of the invention, also showing a preferred twisted bit line structure.

5 is an explanatory diagram of a table showing a circuit topology of the array block of FIG.

FIG. 6 is an illustration of a general purpose decoding circuit used in the topology logic driver of FIG. 2 to identify a particular area in a memory array for data inversion.

7 is an illustration of a region decoding circuit used in the topology logic driver of FIG. 2 to activate a region selected for data inversion.

8 is an explanatory diagram of a data inverting I / O circuit in the circuit of the topology logic driver in the circuit of FIG.

FIG. 9 is a flow diagram illustrating a method for testing a memory integrated circuit having an on-chip topology logic driver according to the present invention.

[Explanation of symbols]

 30 semiconductor memory IC chip 32 memory array 34 data I / O buffer 36 address decoder 38 read / write controller

 ─────────────────────────────────────────────────── ——————————————————————————————————————————————————————————————————————————————————————————————————— ›−−−−−−−––––––––––––––––––––––––––––––––– Zager United States 83706 Blue Stem Lane, Boyes, Idaho 2107

Claims (16)

[Claims] 1. A memory array of a predefined circuit topology, the memory array having a plurality of memory cells and a plurality of access lines connected to the associated memory cells, and one of the memory cells in the memory array. An address decoder for providing an address for selectively accessing one or more memory cells, and temporarily holding data written to and read from the memory cells in the memory array For I
/ O buffer, a read / write controller for managing data write operations and data read operations, and transferring data between the I / O buffer and addressed memory cells, and addressed memory cells A topological logic driver for selectively inverting data written to and read from a memory cell, the topological logic driver identifying based on the location of the addressed memory cell in the circuit topology of the memory array. A topological logic driver that selectively inverts data for addressed memory cells and does not invert data for other addressed memory cells. 2. The topological logic driver comprises a combination of logic gates embodying a Boolean function of selected bits in an address, the Boolean function defining a circuit topology of a memory array. A memory integrated circuit chip as described. 3. The access line includes a row line and a bit line arranged in pairs, and the address decoder includes a row address for selecting a row line and a column address for selecting a bit line pair. 2. The memory of claim 1, providing an address, wherein the topological logic driver selectively inverts data read and written from an addressed memory cell according to a function of a row address. Integrated circuit chip. 4. The access line includes a row line and a bit line arranged in pairs, and the address decoder includes a row address for selecting a row line and a column address for selecting a bit line pair. Providing an address and wherein the topological logic driver selectively inverts the data read and written from the addressed memory cell according to a function of both the row address and the column address. Item 2. A memory integrated circuit chip according to item 1. 5. A memory array of predefined circuit topology, the memory array having a plurality of memory cells and a number of access lines connected to the associated memory cells, and one of the memory arrays. An address decoder for providing an address for selectively accessing more or more memory cells, and for temporarily holding data written to and read from the memory cells in the memory array. Of I
/ O buffer, a read / write controller for managing data write operations and data read operations, and transferring data between the I / O buffer and addressed memory cells, and addressed memory cells A topological logic driver for selectively inverting data written to and read from a memory cell, the topological logic driver identifying based on the location of the addressed memory cell in the circuit topology of the memory array. Of the memory cells in the memory array for possible data inversion, while selectively inverting the data for the addressed memory cells and not inverting the data for the other addressed memory cells. The topology logic driver includes a general-purpose decoding circuit for identifying regions, That includes a number of regions decoding circuit identifies a particular region of the memory cells in the memory array for the data inversion, the memory integrated circuit chip is composed of a topology logic driver. 6. A memory array of predefined circuit topology, the memory array having a plurality of memory cells and a number of access lines connected to associated memory cells, the access lines being row lines and bits. A bit line is a memory array arranged in pairs and an address decoder for providing an address for selectively accessing one or more memory cells in the memory array, The address decoder provides an address including an address including a row address for selecting a row line and a column address for selecting a bit line pair, and is written to and read from a memory cell in a memory array. I for holding data temporarily
/ O buffer, a read / write controller for managing data write operations and data read operations, and transferring data between the I / O buffer and addressed memory cells, and addressed memory cells A topological logic driver for selectively inverting data written to and read from a memory cell, the topological logic driver identifying based on the location of the addressed memory cell in the circuit topology of the memory array. Selectively inverts data for addressed memory cells and does not invert data for other addressed memory cells, the topology logic driver provides for possible data inversion based on a function of row address. A general purpose decoding circuit for identifying a region of memory cells in the memory array is provided. -The logic driver comprises a general purpose inversion signal and a topology logic driver that includes a number of area decoding circuits that identify a particular area of a memory cell in the memory array for possible data inversion based on the column address. Integrated circuit chip. 7. A memory array having a plurality of memory cells and a number of row lines and column lines connected to associated memory cells, wherein the bit lines are arranged in pairs and the bit lines in the bit line pairs are in the memory array. A memory array having a twisted line structure that crosses other bit lines within a bit line pair at a twisted contact of the memory array, and provides an address for selectively accessing one or more memory cells in the memory array. An address decoder for providing a row address for selecting a row line and an address including a column address for selecting a bit line pair, and an address decoder for writing to a memory cell in the memory array. And I for temporarily holding the data read from the memory cell
/ O buffer, a read / write controller for managing data write operations and data read operations, and transferring data between the I / O buffer and addressed memory cells, and addressed memory cells A topological logic driver for selectively inverting data written to and read from a memory cell, the topological logic driver being associated with those associated bit line pairs and twisted contacts in the memory array. A topological logic driver that selectively inverts data for a particular addressed memory cell and does not invert data for another addressed memory cell based on the location of the memory integrated circuit chip. 8. The topological logic driver includes a combination of logic gates embodying a Boolean function of selected bits in an address, the Boolean function defining a circuit topology of a memory array. 7
A memory integrated circuit chip as described. 9. The memory of claim 7, wherein the topological logic driver selectively inverts written and read data in addressed memory cells according to a function of row address. Integrated circuit chip. 10. The topological logic driver selectively inverts the written and read data in the addressed memory cell according to a function of both the row address and the column address. Item 7. A memory integrated circuit chip according to item 7. 11. A general purpose decoding circuit in which a topological logic driver identifies a region of memory cells in a memory array for possible data inversion, and a memory in the memory array for possible data inversion. 8. The memory integrated circuit chip of claim 7 including a number of area decoding circuits that identify a particular area of the cell. 12. A general purpose decoding circuit in which a topological logic driver identifies a region of memory cells in a memory array for possible data inversion based on a function of row address and outputs a general purpose inversion signal. 8. A plurality of area decoding circuits are included to identify a particular area of a memory cell in a memory array for possible data inversion based on a function of the general purpose inversion signal and a column address. A memory integrated circuit chip as described. 13. A memory array having a predefined circuit topology, the memory array having a plurality of bit line pairs and a plurality of row lines arranged in a folded bit line structure, the bit line pairs being twisted bits. Has a line structure, where the bit lines in a bit line pair cross other bit lines in the bit line pair at twisted contacts in the memory array, and the memory array is connected to the plurality of memory cells connected at the intersections of the bit line pair. A memory array having lines, an address decoder that provides an address consisting of a number of bits in a row line and bit line pair to selectively access a memory cell in the memory array, and a read to the selected bit line pair And data I / O means for writing and circuit topography of the memory array. Data inversion means for selectively inverting the written and read data for the addressed memory cell based on the location of the addressed memory cell in the memory integrated circuit. The chip is operable in a test mode in which the same binary value of data is written to all memory cells connected to a selected bit line pair in the memory array, and the data inverting means considers the circuit topology. In order to selectively invert the data input to the specific memory cell connected to the selected bit line pair and to input the data input to the other memory cell connected to the selected bit line pair, A memory integrated circuit chip characterized by not inverting. 14. The data comprises alternating even and odd bits, the data inverting means comprising two complementary signals EVINV /
Generating a set of EVINV ^* and ODINV / ODINV ^* , the complementary EVINV / EVINV ^* signals are used to selectively invert even bits of data,
The complementary ODINV / ODINV ^* signals are used to selectively invert odd bits of data, and the circuit topology of the memory array is addressed by connecting to the same row line following inversion by the data inversion means. All even bits of the data actually input to the memory cells are the same, and all odd bits of the data actually input to the addressed memory cells connected to the same row line are the same. 14. The memory integrated circuit chip according to claim 13, which is 15. A method for manufacturing a memory integrated circuit chip having an on-chip topology logic driver, the method having a predefined circuit topology and connecting a plurality of memory cells and associated memory cells. A step of providing an integrated circuit chip composed of a memory array having a large number of access lines, a step of obtaining a Boolean function representing a circuit topology of the integrated circuit, and a topology logic circuit embodying the Boolean function on the integrated circuit chip. Forming step, and a method of manufacturing a memory integrated circuit chip comprising: 16. A memory integrated circuit chip having a predefined circuit topology and comprising a plurality of memory cells of normal and spare memory cells and a plurality of access lines connected to associated memory cells. A method of testing a group of memory cells in a memory array according to an address for the memory cells and a selected number of groups of memory cells accessed according to a test pattern. Simultaneously writing bits of the test data of, and internally positioning a particular memory cell within the accessed group receiving inverted data to perform a test pattern for a given circuit topology of the memory array, Specific notes based on their position in the circuit topology A step of selectively inverting the bits of the test data written in the cells on-chip and not inverting the bits of the test data written in other memory cells, and a step of reading the test data from the group of memory cells, The process of selectively inverting the bits of test data from a particular memory cell that was previously inverted, on-chip, and the memory accessed to determine whether the memory integrated circuit has a defective memory cell. A method of testing a memory integrated circuit chip comprising: comparing bits of test data read from a group of cells with bits of test data written to a group of accessed memory cells.