JPH09129820A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount power semiconductor elements on a module substrate in the manner in which both the thermal balance and the heat dispersion of two power transistors are satisfied. SOLUTION: When power transistors 42, 43 are operated, heat is generated from the power transistors 42, 43. Since they are sufficiently small as compared with a module substrate 41, the heat diffuses in thermal diffusion regions 44, 45 at an angle 45 deg. to the surface of the module substrate 41 on which the power transistors 42, 43 are mounted. In this case, the mounting interval of the power transistors 42, 43 is (a), and the thickness of the module substrate 41 is (d). When the power transistors 42, 43 are mounted at an interval which satisfies a relation a=2×d, the thermal diffusion regions 44, 45 of the power transistors 42, 43 come into contact with each other, on the back of the module substrate 41 on which the power transistor 42, 43 are not mounted. Thereby the heat dispersion of the power transistors 42, 43 can be optimized while the thermal balance is maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid in which a plurality of power semiconductor elements such as power transistors and other circuit elements are mounted and arranged on a module mounting board (hereinafter referred to as a module board) to form a module. The present invention relates to an integrated semiconductor device.

[0002]

2. Description of the Related Art In recent years, for example, a semiconductor integrated circuit device used for a CRT video signal final amplification stage circuit has a circuit such as a power semiconductor element such as a power transistor, a resistor, a diode or the like which constitutes the video signal final amplification stage circuit. In many cases, the elements are mounted in high density on the module substrate to form a single package module.

In the conventional method of arranging the power semiconductor elements in the semiconductor integrated circuit device, the mounting distance between the power semiconductor elements is increased in consideration of the heat dissipation of the power semiconductor elements. Hereinafter, a method of arranging power semiconductor elements in the conventional semiconductor integrated circuit device will be described. FIG.
1 is a circuit diagram of an active load feedback circuit which is one of CRT video signal final amplification stage circuits, 1 is a constant current source pnp type power transistor, 2 is a grounded emitter n
pn type power transistor, 3 for push-pull circuit
pn type power transistor, 4 is p for push-pull circuit
The np type power transistors 5 are diodes for compensating a push-pull circuit voltage reduction, and are a constant current source pnp type power transistor 1, a grounded emitter npn type power transistor 2, and a push pull circuit npn type power transistor 3 and a push pull circuit. The pnp type power transistors 4 are complementary power transistors. 6a to 6i are resistors, 7 is a DC power supply, 8a is an input terminal, 8b is an output terminal, 8c is a power supply terminal, and 8d is a ground terminal.

In recent years, in a CRT image screen, a screen in which dots are clearly displayed is desired, and therefore, it is necessary to set a switching speed as high as 5 ns or less. The load feedback circuit is adopted as the CRT video signal final amplification stage circuit. FIG. 7A is a cross-sectional view of the semiconductor integrated circuit device in the mounting arrangement portion of the complementary constant current source pnp type power transistor 1 and the grounded-emitter npn type power transistor 2 in the active load feedback circuit shown in FIG. In FIG. 7A, reference numeral 11 is a module substrate. Reference numerals 12 and 13 denote complementary power transistors mounted on the surface of the module substrate 11, and the power transistor 12 is the constant current source pnp type power transistor 1 shown in FIG.
The power transistor 13 corresponds to the grounded-emitter npn type power transistor 2 of FIG. 14,1
Reference numeral 5 is a heat diffusion region showing a region in which heat generated from the power transistors 12 and 13 diffuses in the module substrate 11, and the boundary between these heat diffusion regions 14 and 15 extends from the front surface to the back surface of the module substrate 11. It spreads radially, and its spread angle forms an angle of 45 degrees with respect to a perpendicular line standing on the module substrate 11.

Here, the thermal diffusion region will be defined. When the semiconductor chip is mounted directly on the module substrate, the area that expands at an angle of 45 degrees (with respect to the perpendicular line standing on the module substrate 11) from the peripheral portion of the contact surface of the semiconductor chip on the module substrate is thermally diffused. Area. When the semiconductor chip is mounted on the module board via the high thermal conductivity pad, the angle of 45 degrees from the peripheral edge of the contact surface of the high thermal conductivity pad on the module board (with respect to the vertical line standing on the module board 11). The area that spreads out is the thermal diffusion area. When the shape of the contact surface of the semiconductor chip or the high thermal conductivity pad with the module substrate is quadrangular, the heat diffusion region has a truncated pyramid shape, and when the contact surface has a circular shape, it has a truncated cone shape.

FIG. 7B is an overall plan view of the semiconductor integrated circuit device shown in FIG. 7A as viewed from the surface on which the power transistors 12 and 13 are mounted. FIG.
In (b), 11 is a module substrate, 12, 13,
Reference numerals 16 and 17 denote power transistors mounted on the surface of the module substrate 11. The power transistor 16 corresponds to the npn-type power transistor 3 for the push-pull circuit in FIG. 6, and the power transistor 17 is for the push-pull circuit in FIG. Corresponding to the pnp type power transistor 4, these are complementary power transistors. Reference numeral 18 denotes a diode mounted on the surface of the module substrate 11, which corresponds to the push-pull circuit voltage reduction compensating diode 5 in FIG. Reference numerals 19 denote chip resistors mounted on the surface of the module substrate 11, which correspond to the resistors 6a to 6i shown in FIG. 21 is the module substrate 1
1 is a pad for terminals formed on the surface of 1 and corresponds to the input terminal 8a, the output terminal 8b, the power supply terminal 8c, and the ground terminal 8d in FIG.

As can be seen from FIGS. 7A and 7B, in the conventional semiconductor integrated circuit device, the heat dissipation of the complementary power transistors 12 and 13 is emphasized, and the heat balance of the power transistors 12 and 13 is taken into consideration. I didn't.
The same applies to the power transistors 16 and 17.

[0008]

In the CRT video signal final amplification stage circuit (semiconductor integrated circuit device) including the complementary power transistors arranged as described above, the influence of heat generated after the operation on the circuit will be described below with reference to FIG. Will be explained. First, immediately after the start of operation, there is almost no temperature difference between the power transistors 12 and 13, so the circuit operates as designed. Next, after a while after the operation, because the heat generation amounts of the power transistor 12 and the power transistor 13 are different, or the thermal diffusion regions 14 and 15 do not cross each other thermally,
Since heat cannot be balanced, the temperatures of the power transistor 12 and the power transistor 13 are different. As a result, the internal circuit constants of the power transistors 12 and 13 are different from those immediately after the operation and are not complementary, the circuit does not operate as designed, and the video signal is not accurately amplified, resulting in image deterioration.

FIGS. 8A and 8B show an example of an output signal when a rectangular wave signal is amplified as an example of a video signal in a semiconductor integrated circuit device (module) in which power transistors are mounted by a conventional arrangement method. The solid line 31 in FIG. 9A is the actual output signal, the broken line 32 is the ideal output signal, the solid line 33 in FIG. 9B is the actual output signal, and the broken line 34 is the ideal output signal. It is shown that, due to the imbalance of the internal circuit constants of the power transistors 12 and 13, even if the level of the input signal is constant, one of the levels of the output signal gradually changes.

A first object of the present invention is to realize a heat balance between two power semiconductor elements, and to obtain two power semiconductor elements due to a difference in heat generation amount between the two power semiconductor elements after the circuit operation. It is an object of the present invention to provide a semiconductor device capable of preventing a change in circuit operation due to an unbalanced element temperature. A second object of the present invention is to realize a heat balance between two power semiconductor elements, and to determine the temperature of the two power semiconductor elements due to the difference in heat generation amount of the two power semiconductor elements after the circuit operation. It is an object of the present invention to provide a semiconductor device capable of preventing the circuit operation from changing due to the unbalance and losing the complementary property as a characteristic between two power semiconductor elements.

A third object of the present invention is to realize a heat balance among four power semiconductor elements, and the four power semiconductor elements are different in heat generation amount after the circuit operation. It is an object of the present invention to provide a semiconductor device capable of preventing a change in circuit operation due to an unbalanced element temperature. A fourth object of the present invention is to realize a heat balance between the four power semiconductor elements and to reduce the temperature of the four power semiconductor elements due to the difference in heat generation amount of the four power semiconductor elements after the circuit operation. Prevent the circuit operation from changing due to the imbalance of the power supply and prevent the loss of the complementary property of two power semiconductor devices as a characteristic between the four power semiconductor devices. It is to provide a semiconductor device which can be manufactured.

A fifth object of the present invention is to realize a heat balance between two power semiconductor elements while ensuring the heat dissipation of the two power semiconductor elements, and to provide two power after circuit operation. It is an object of the present invention to provide a semiconductor device capable of preventing the circuit operation from changing due to the temperature of two power semiconductor elements being unbalanced due to the difference in the heat generation amount of the power semiconductor elements.

A sixth object of the present invention is to secure the heat dissipation of two complementary power semiconductor elements,
This is because the heat balance between the two power semiconductor elements is realized and the temperature of the two power semiconductor elements becomes unbalanced due to the difference in the heat generation amount of the two power semiconductor elements after the circuit operation. It is an object of the present invention to provide a semiconductor device capable of preventing the circuit operation from changing and losing the complementary property as a characteristic between two power semiconductor elements.

A seventh object of the present invention is to realize a heat balance among the four power semiconductor elements while ensuring the heat dissipation of the four power semiconductor elements, and to obtain the four power after circuit operation. It is an object of the present invention to provide a semiconductor device capable of preventing the circuit operation from changing due to the imbalance of the temperatures of the four power semiconductor elements due to the difference in the heat generation amount of the power semiconductor elements.

An eighth object of the present invention is to ensure the heat dissipation of the four complementary power semiconductor elements,
This is because the heat balance between the four power semiconductor elements is realized, and the temperature of the four power semiconductor elements becomes unbalanced due to the difference in heat generation amount of the four power semiconductor elements after the circuit operation. To prevent the circuit operation from changing by 4
It is an object of the present invention to provide a semiconductor device capable of preventing the loss of the complementary property of every two power semiconductor elements as a characteristic between the power semiconductor elements.

A ninth object of the present invention is to realize a heat balance between the four power semiconductor elements and the temperature compensating circuit element so that the temperatures of the four power semiconductor elements and the temperature compensating circuit element are controlled. It is an object of the present invention to provide a semiconductor device capable of preventing a change in circuit operation due to an unbalance.

[0017]

A semiconductor device according to claim 1 is a semiconductor device in which first and second power semiconductor elements are mounted on a module substrate.
The mounting intervals of the power semiconductor elements are radially arranged from the boundary of the heat diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the contact surface of the second power semiconductor element on the module substrate. It is characterized in that the boundary of the expanded thermal diffusion region is set to overlap at least on the back surface of the module substrate.

According to this structure, the boundaries of the heat diffusion regions of the first and second power semiconductor elements overlap at least on the back surface of the module substrate, so that the heat balance between the first and second power semiconductor elements is balanced. Realized and first after circuit operation
Also, it is possible to prevent the circuit operation from changing due to the temperature of the first and second power semiconductor elements becoming unbalanced due to the difference in the amount of heat generated by the second power semiconductor element. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

A semiconductor device according to a second aspect of the present invention is a semiconductor device in which first and second power semiconductor elements are mounted on a module substrate, wherein a mounting interval a between the first and second power semiconductor elements is set. , Where d is the thickness of the module substrate, and is set so as to satisfy the relationship of a ≦ 2 × d.

According to this structure, the heat diffusion region in the module substrate due to the heat generation of the first and second power semiconductor elements is a perpendicular line that stands from the contact surface of the first and second power semiconductor elements to the module substrate. With respect to the module substrate, the angle of 45 degrees is spread radially from the front surface to the back surface of the module substrate, and the boundaries of the heat diffusion regions of the first and second power semiconductor elements are overlapped at least on the back surface of the module substrate. A heat balance between the first and second power semiconductor elements is realized, and the temperature of the first and second power semiconductor elements is changed due to the difference in heat generation amount between the first and second power semiconductor elements after the circuit operation. It is possible to prevent the circuit operation from changing due to the unbalance.
Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

A semiconductor device according to a third aspect is a semiconductor device in which first, second, third and fourth power semiconductor elements are mounted on a module substrate, the first and second power semiconductors. The mounting interval of the elements is such that the boundary between the thermal diffusion regions radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion radially extending from the contact surface of the second power semiconductor element on the module substrate. The boundary between the regions is set to overlap at least on the back surface of the module substrate, and the mounting intervals of the third and fourth power semiconductor elements are radially expanded from the contact surface of the third power semiconductor element on the module substrate. The boundary of the heat diffusion region and the boundary of the heat diffusion region radially extending from the contact surface of the fourth power semiconductor element on the module substrate are at least the back surface of the module substrate. The mounting intervals of the first and third power semiconductor elements are set to overlap each other, and the boundary between the heat diffusion regions radially extending from the contact surface of the first power semiconductor element in the module substrate and the third in the module substrate. The boundary of the heat diffusion region radially extending from the contact surface of the power semiconductor element of is overlapped at least on the back surface of the module substrate, and the mounting intervals of the second and fourth power semiconductor elements are set in the module substrate. The boundary of the thermal diffusion region radially extending from the contact surface of the second power semiconductor element and the boundary of the thermal diffusion region radially expanding from the contact surface of the fourth power semiconductor element on the module substrate are at least the module substrate. It is characterized in that the back side is set to overlap.

According to this structure, the boundary between the thermal diffusion regions of the first and second power semiconductor devices, the boundary between the thermal diffusion regions of the third and fourth power semiconductor devices, and the first and third power semiconductor devices. Since the boundaries of the semiconductor element thermal diffusion regions and the boundaries of the second and fourth power semiconductor elements thermal diffusion regions overlap each other at least on the back surface of the module substrate, the first, second, third and fourth electric powers are provided. A heat balance between the power semiconductor elements is realized, and the first, second, third, and fourth power semiconductor elements have different heat generation amounts after the circuit is operated.
It is possible to prevent the circuit operation from changing due to the temperatures of the second, third and fourth power semiconductor elements becoming unbalanced. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

A semiconductor device according to claim 4 is a module
First, second, third and fourth power semiconductor elements on the substrate
A semiconductor device having a child mounted thereon, comprising:
Power semiconductor element mounting interval a₁The thickness of the module board
Where d is₁Set so as to satisfy the relationship of ≦ 2 × d, and for the third and fourth power
Semiconductor element mounting interval a _TwoAnd a_TwoFor the first and third powers, set so as to satisfy the relation of ≦ 2 × d
Semiconductor element mounting interval a _ThreeAnd a_ThreeFor the second and fourth powers, set so as to satisfy the relation of ≦ 2 × d
Semiconductor element mounting interval a _FourAnd a_FourIt is characterized in that it is set so as to satisfy the relation of ≦ 2 × d.

According to this structure, the heat diffusion regions in the module substrate due to the heat generation of the first, second, third and fourth power semiconductor elements are the first, second, third and fourth power semiconductors. A boundary of thermal diffusion regions of the first and second power semiconductor elements, which spreads radially from the front surface to the back surface of the module substrate at an angle of 45 degrees with respect to a vertical line standing on the module substrate from the contact surface of the element, Boundaries of thermal diffusion regions of the third and fourth power semiconductor devices, first and third
Since the boundaries of the thermal diffusion regions of the power semiconductor elements and the boundaries of the thermal diffusion regions of the second and fourth power semiconductor elements overlap each other at least on the back surface of the module substrate, the first, second, third and A heat balance between the four power semiconductor elements is realized, and the first, second, third, and fourth power semiconductor elements have different heat generation amounts after the circuit is operated.
It is possible to prevent the circuit operation from changing due to the temperatures of the second, third and fourth power semiconductor elements becoming unbalanced. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

A semiconductor device according to a fifth aspect is a semiconductor device in which first and second power semiconductor elements are mounted on a module substrate, and the mounting intervals of the first and second power semiconductor elements are: The module has a boundary of a thermal diffusion region radially extending from a contact surface of the first power semiconductor element on the module substrate and a boundary of a thermal diffusion region radially extending from a contact surface of the second power semiconductor element on the module substrate. It is characterized in that it is set to be in contact with the back surface of the substrate.

According to this structure, the boundaries of the heat diffusion regions of the first and second power semiconductor elements are in contact with each other on the back surface of the module substrate, so that the heat dissipation of the first and second power semiconductor elements is ensured. , Heat balance between the first and second power semiconductor elements is achieved, and the first and second circuit operations are performed.
It is possible to prevent the circuit operation from changing due to the temperature of the first and second power semiconductor elements becoming unbalanced due to the difference in the heat generation amount of the power semiconductor elements. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

A semiconductor device according to a sixth aspect of the present invention is a semiconductor device in which first and second power semiconductor elements are mounted on a module substrate, and a mounting interval a between the first and second power semiconductor elements is set. , Where d is the thickness of the module substrate, and is set so as to satisfy the relationship of a = 2 × d.

According to this structure, the heat diffusion region in the module substrate due to the heat generation of the first and second power semiconductor elements is a perpendicular line that stands from the contact surface of the first and second power semiconductor elements to the module substrate. Since it forms a 45-degree angle with respect to the module substrate and spreads radially from the front surface to the back surface of the module substrate, and the boundary of the heat diffusion regions of the first and second power semiconductor elements are in contact with each other on the back surface of the module substrate. The heat balance between the first and second power semiconductor elements is realized while ensuring the heat dissipation of the first and second power semiconductor elements, and the first and second power semiconductor elements after the circuit operation are realized. It is possible to prevent the circuit operation from changing due to the temperature of the first and second power semiconductor elements becoming unbalanced due to the difference in the amount of heat generation. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

A semiconductor device according to a seventh aspect is a semiconductor device in which first, second, third and fourth power semiconductor elements are mounted on a module substrate, and the first and second power semiconductors are provided. The mounting interval of the elements is such that the boundary between the thermal diffusion regions radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion radially extending from the contact surface of the second power semiconductor element on the module substrate. The boundary between the regions is set to be in contact with the back surface of the module substrate, and the mounting intervals of the third and fourth power semiconductor elements are spread radially from the contact surface of the third power semiconductor element on the module substrate. The boundary of the diffusion region and the boundary of the thermal diffusion region radially extending from the contact surface of the fourth power semiconductor element on the module substrate are set to be in contact with each other on the back surface of the module substrate. And the mounting interval of the third power semiconductor element, the boundary of the thermal diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the contact surface of the third power semiconductor element on the module substrate. The boundary of the heat diffusion region radially expanded from is set to be in contact with the back surface of the module substrate, and the mounting interval of the second and fourth power semiconductor elements is set to the contact of the second power semiconductor element on the module substrate. The boundary of the thermal diffusion region radially extending from the surface and the boundary of the thermal diffusion region radially extending from the contact surface of the fourth power semiconductor element on the module substrate are set to be in contact with each other on the back surface of the module substrate. And

According to this structure, the boundary between the thermal diffusion regions of the first and second power semiconductor elements, the boundary between the thermal diffusion regions of the third and fourth power semiconductor elements, and the first and third power The boundaries of the semiconductor element thermal diffusion regions and the boundaries of the thermal diffusion regions of the second and fourth power semiconductor devices are in contact with each other on the back surface of the module substrate.
A heat balance between the first, second, third, and fourth power semiconductor elements is realized while ensuring the heat dissipation of the third and fourth power semiconductor elements, and the first and second circuit elements after the circuit operation are realized. The circuit operation changes due to the imbalance of the temperatures of the first, second, third and fourth power semiconductor elements due to the difference in the heat generation amount of the second, third and fourth power semiconductor elements. Can be prevented. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

A semiconductor device according to claim 8 is a module
First, second, third and fourth power semiconductor elements on the substrate
A semiconductor device having a child mounted thereon, comprising:
Power semiconductor element mounting interval a₁The thickness of the module board
Where d is₁= 2 × d for the third and fourth powers.
Semiconductor element mounting interval a _TwoAnd a_Two= 2 × d for the first and third powers.
Semiconductor element mounting interval a _ThreeAnd a_Three= 2 × d for the second and fourth powers.
Semiconductor element mounting interval a _FourAnd a_FourIt is characterized in that it is set so as to satisfy the relationship of = 2 × d.

According to this structure, the heat diffusion regions in the module substrate due to the heat generation of the first, second, third and fourth power semiconductor elements are the first, second, third and fourth power semiconductors. A boundary of thermal diffusion regions of the first and second power semiconductor elements, which spreads radially from the front surface to the back surface of the module substrate at an angle of 45 degrees with respect to a vertical line standing on the module substrate from the contact surface of the element, Boundaries of thermal diffusion regions of the third and fourth power semiconductor devices, first and third
Since the boundary of the heat diffusion region of the power semiconductor element and the boundary of the heat diffusion region of the second and fourth power semiconductor elements are in contact with the back surface of the module substrate, respectively, the first, second, third and fourth While ensuring the heat dissipation of the power semiconductor element, the heat balance among the first, second, third and fourth power semiconductor elements is realized, and the first, second, third and fourth circuit operation are performed. It is prevented that the circuit operation is changed due to the unbalanced temperatures of the first, second, third and fourth power semiconductor elements due to the difference in the heat generation amount of the fourth power semiconductor element. be able to. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

According to a ninth aspect of the present invention, in the semiconductor device according to the fifth or sixth aspect, the first and second power semiconductor elements are complementary types. With this configuration, it is possible to prevent loss of the complementary property as a characteristic between the complementary first and second power semiconductor elements. A semiconductor device according to claim 10 is the semiconductor device according to claim 7 or 8, wherein the first and second power semiconductor elements are complementary types, and the third and fourth power semiconductor elements are complementary. It is a type.

With this structure, it is possible to prevent loss of the characteristic between the complementary first and second power semiconductor elements and the complementary characteristic as the characteristic between the complementary third and fourth power semiconductor elements. be able to. The semiconductor device according to claim 11 is claim 3, claim 4, claim 7, claim 8 or claim 10.
The semiconductor device described above is characterized in that a circuit element for temperature compensation is mounted at a position surrounded by the first, second, third and fourth power semiconductor elements on the module substrate.

According to this structure, heat balance between the first, second, third and fourth power semiconductor elements and the temperature compensating circuit element is achieved. Therefore, after starting the circuit operation, When the temperature of the first, second, third and fourth power semiconductor elements rises, the temperature of the circuit element for temperature compensation also rises similarly.
Further, it is possible to prevent the circuit operation from changing due to the temperature of the fourth power semiconductor element and the temperature compensating circuit element becoming unbalanced.

According to a twelfth aspect of the present invention, in the semiconductor device according to the first, third, fifth and seventh aspects, the power semiconductor element is interposed between the power semiconductor element body and the power semiconductor element body and the module substrate. The high thermal conductive pads are provided, the mounting interval is the interval between the high thermal conductive pads, and the heat diffusion region is radially extended from the contact surface of the high thermal conductive pads on the module substrate.

According to this structure, the heat diffusion region is expanded and the heat dissipation can be improved. Others are the same as those of the semiconductor device according to claims 1, 3, 5, and 7. According to a thirteenth aspect of the present invention, in the semiconductor device according to the second, fourth, sixth or eighth aspect, the power semiconductor element is a high temperature semiconductor element main body and a high temperature semiconductor element main body and a module substrate. It is composed of a conductive pad, and the mounting interval is the interval of the high thermal conductive pad.

According to this structure, the heat diffusion area is expanded and the heat dissipation can be improved. Others are the same as those of the semiconductor device according to claims 2, 4, 6, and 8. The semiconductor device according to claim 14, wherein a plurality of sets of complementary power semiconductor elements on the module substrate are radially spread from a contact surface of the power semiconductor element on the module substrate, and a boundary of a heat diffusion region is at least on a back surface of the module substrate. It is characterized in that it is arranged so as to be in contact with a continuous ring.

According to this structure, the boundaries of the thermal diffusion regions of the plurality of sets of power semiconductor elements are in contact with each other on the back surface of the module substrate, so that the plurality of sets of power semiconductor elements can be radiated while ensuring the heat dissipation. Achieves heat balance between semiconductor elements,
It is possible to prevent the circuit operation from changing due to an unbalanced temperature of the plurality of sets of power semiconductor elements due to the difference in heat generation amount of the plurality of sets of power semiconductor elements after the circuit operation. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

According to a fifteenth aspect of the present invention, in the semiconductor device, a plurality of sets of complementary power semiconductor elements on the module substrate are radially spread from the contact surface of the power semiconductor element on the module substrate, and the boundary of the heat diffusion region is the module substrate. A circuit element for temperature compensation of the power semiconductor element is arranged at a position surrounded by the power semiconductor element at least on the back surface so as to be in contact with the annular shape.

According to this structure, the heat balance between the plurality of sets of power semiconductor elements and the temperature compensating circuit element is achieved, so that the temperature of the plurality of sets of power semiconductor elements is set after the start of the circuit operation. When the temperature rises, the temperature of the temperature compensating circuit element also rises in the same manner, which is caused by the imbalance between the temperature of the multiple power semiconductor elements and the temperature compensating circuit element. It is possible to prevent the circuit operation from changing.

According to a sixteenth aspect of the present invention, a plurality of sets of complementary power semiconductor elements on a module substrate surround a circuit element for temperature compensation of the power semiconductor element, and the circuit element is provided on the module substrate. It is characterized in that the power semiconductor device is arranged on a heat diffusion region radially extending from a contact surface of the power semiconductor device. With this configuration, the heat balance between the plurality of sets of power semiconductor elements and the temperature compensating circuit element is achieved, so that the temperatures of the plurality of sets of power semiconductor elements rise after the start of the circuit operation. At the same time, the temperature of the temperature compensating circuit element also rises in the same manner, and the circuit operation is caused by the unbalanced temperatures of the plurality of sets of power semiconductor elements and the temperature compensating circuit element. It can be prevented from changing.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS.
1A shows a semiconductor integrated circuit device according to a first embodiment of the present invention, that is, a complementary constant current source pnp type power transistor 1 and a grounded-emitter n in the active load feedback circuit shown in FIG.
3 is a cross-sectional view of a semiconductor integrated circuit device in a mounting arrangement portion (direct mounting) of a pn type power transistor 2. FIG. FIG. 1 (a)
In the figure, 41 is a module substrate such as a ceramic substrate or a glass / epoxy substrate. Reference numerals 42 and 43 denote complementary power transistors (power semiconductor elements) mounted on the surface of the module substrate 41. The power transistor 42 corresponds to the constant current source pnp type power transistor 1 of FIG.
3 is a grounded emitter npn type power transistor 2 of FIG.
Corresponding to Reference numerals 44 and 45 are heat diffusion regions indicating regions in which heat generated from the power transistors 42 and 43 is diffused in the module substrate 41, and the boundaries between these heat diffusion regions 44 and 45 are from the front surface to the back surface of the module substrate 41. It spreads out radially and the spread angle is
An angle of 45 degrees is formed with respect to a vertical line standing on the module substrate 41. a ₁ is the mounting distance of the power transistors 42 and 43, and d is the thickness of the module substrate 41. FIG.
FIG. 1B is an overall plan view of the semiconductor integrated circuit device shown in FIG. 1A viewed from the surface on which the power transistors 42 and 43 are mounted. In FIG. 1B, 41 is a module substrate, and 42, 43, 46, and 47 are power transistors mounted on the surface of the module substrate 41. The power transistor 42 is the constant current source pn of FIG.
The power transistor 43 corresponds to the grounded-emitter npn-type power transistor 2 of FIG. 6, the power transistor 46 corresponds to the push-pull circuit npn-type power transistor 3 of FIG. 6,
The power transistor 47 is p for the push-pull circuit of FIG.
It corresponds to the np type power transistor 4. Reference numeral 48 denotes a circuit element mounted on the surface of the module substrate 41, for example, a diode which needs to maintain a heat balance with the power transistors 42, 43, 46, 47, and the push-pull circuit voltage reduction compensating diode 5 of FIG. Correspond.

The circuit element used for temperature compensation of the complementary power transistor used in the present invention, for example, a diode, itself performs temperature compensation in response to the temperature variation of the power transistor. Therefore, the diode needs to be in thermal balance with and at the center of the power transistor.

Reference numerals 49 are chip resistors mounted on the surface of the module substrate 41, respectively, and are resistors 6a to 6 shown in FIG.
Corresponds to i, etc. Reference numeral 51 denotes a terminal pad formed on the surface of the module substrate 41, which corresponds to the input terminal 8a, the output terminal 8b, the power supply terminal 8c, and the ground terminal 8d in FIG. a ₁ is the mounting distance between the power transistor 42 and the power transistor 43, and a ₂ is the power transistor 4
6 is the mounting distance between the power transistors 47, a ₃ is the mounting distance between the power transistors 42 and 46, and a ₄ is the mounting distance between the power transistors 43 and 47.

In FIG. 2, the power transistors 42 and 43 are not directly mounted on the module substrate 41, but are mounted on the module substrate 41 via the high thermal conductivity pads 52, and the others are the same as those in FIG. The principle of the semiconductor integrated circuit device of this embodiment configured as described above will be described below.

First, FIG. 1A will be described. When the complementary power transistors 42 and 43 are operated, the power transistors 42 and 43 generate heat, and the power transistors 42 and 43 are generated by the module substrate 4
Since it is sufficiently smaller than 1, the heat is diffused like the heat diffusion regions 44 and 45 at an angle of 45 degrees with respect to the perpendicular line standing on the surface of the module substrate 41 on which the power transistors 42 and 43 are mounted. At this time, the power transistor 4
When the mounting interval of 2, 43 is a ₁ , the thickness of the module substrate 41 is d, and the power transistors 42, 43 are mounted at intervals satisfying a = 2 × d, the power transistors 42, 43 of the module substrate 41 are mounted. As shown in FIG. 1A, the power transistors 42, 4
The thermal diffusion regions 44 and 45 of No. 3 just contact. As a result, the complementary power transistor 42,
No. 43 can maximize heat dissipation while maintaining heat balance.

A solid line 61 in FIG. 3 indicates a rectangular wave as an example of a video signal in a semiconductor integrated circuit device including a module substrate 41 on which complementary power transistors 42 and 43 are mounted by the arrangement method according to the first embodiment of the present invention. It is the output waveform of the semiconductor integrated circuit device when the signal is amplified, the broken line 62 is the same circuit, but the output waveform of the semiconductor integrated circuit device when a> (2 × d) × (1 + 0.01) Is.

From the waveform of FIG. 3, in the case of the power transistors 42 and 43 that require heat dissipation, by mounting them at intervals satisfying a = 2 × d, the circuit operation does not change, the complementary property is maintained, and it is correct. It can be seen that when a rectangular wave is obtained and the mounting interval deviates from the above value by more than + 1%, the circuit operation does not change, the complementary property collapses, and a correct rectangular wave cannot be obtained.

Next, FIG. 1B will be described. As in the circuit shown in FIG. 6, the complementary power transistors are the constant current source pnp type power transistor 1, the grounded emitter npn type power transistor 2, the push pull circuit npn type power transistor 3 and the push pull circuit pnp type power transistor. As shown in FIG. 1B, the power transistors 42, 43, 46, and 47 are provided in order to improve both the heat balance and the heat dissipation with the four sets of the transistor 4 and the four power transistors 1 to 4. The mounting intervals of a ₁ , a ₂ , a ₃ , a ₄ and the module board 4
When the thickness of 1 is d, a ₁ = a ₂ = a ₃ = a ₄ =
By arranging the power transistors 42, 43, 46, and 47 so as to circumscribe a corner of a square whose side is a = 2 × d, the same effect as in FIG. 1A can be obtained.

Further, the voltage reduction compensating diode 5 shown in FIG.
Power transistors 42, 43, 46, 47
If there is an element that wants to be in heat balance with the power transistors 42, 43, 46, 47, as shown in FIG.
By arranging the diode 48 in the square inscribed in, the heat balance between the power transistors 42, 43, 46, 47 and the diode 48 can be achieved.

Further, as shown in FIG. 2, when the high thermal conductivity pad 52 is sandwiched between the power transistors (power semiconductor element bodies) 42, 43 and the module substrate 41, the high thermal conductivity with the power transistors 42, 43. Pad 52,
The same effect as that of FIG. 1A can be obtained even when 52 is combined and arranged as a power semiconductor element. In this case, the mounting interval is the arrangement interval of the high thermal conductive pads 52, 52, and the thermal diffusion region radially extends at an angle of 45 degrees from the contact surface of the high thermal conductive pads 52, 52 on the module substrate 41. It becomes an area.

As described above, according to the semiconductor integrated circuit device of this embodiment, the heat diffusion regions 44 and 45 in the module substrate 41 due to the heat generation of the first and second power transistors 42 and 43 are the first And, from the contact surface of the second power transistors 42, 43 or the contact surface of the high thermal conductivity pad 52, an angle of 45 degrees is formed with respect to a vertical line standing on the module substrate 41, and the module substrate 41 is radially radiated from the front surface to the back surface. Since the boundaries of the thermal diffusion regions 44 and 45 of the first and second power transistors 42 and 43 are just in contact with each other on the back surface of the module substrate 41, the first and second power transistors 4 and 4 are spread.
The heat balance between the first and second power transistors 42 and 43 is realized while ensuring the heat dissipation of the second and third power transistors 42 and 43, and the first and second power transistors 42 and 4 after the circuit operation are realized.
It is possible to prevent the circuit operation from changing due to the imbalance of the temperatures of the first and second power transistors 42 and 43 due to the difference in the heat generation amount of No. 3.
Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

Further, the heat diffusion regions in the module substrate 41 due to the heat generation of the first, second, third and fourth power transistors 42, 43, 46, 47 are the first, second and third.
Third and fourth power transistors 42, 43, 4
From the contact surface of the module substrate 41 and the perpendicular to the module substrate 41, the module substrate 41 forms an angle of 45 degrees and spreads radially from the front surface to the back surface of the module substrate 41, and the heat of the first and second power transistors 42 and 43 is increased. Boundary of diffusion area, third
And the boundaries of the thermal diffusion regions of the fourth power transistors 46, 47, the first and third power transistors 42,
The boundaries of the thermal diffusion regions of 46 and the boundaries of the thermal diffusion regions of the second and fourth power transistors 43 and 47 are exactly in contact with each other on the back surface of the module substrate 41, so that the first, second, third and fourth Of the first, second, third and fourth power transistors 42, 43, 46, 47 while ensuring the heat dissipation of the power transistors 42, 43, 46, 47.
43, 46, 47 to achieve a heat balance between the first, second, third and fourth power transistors 42, 42 after circuit operation.
The first, second, third and fourth power transistors 42, 43, 46,
It is possible to prevent the circuit operation from changing due to the temperature of 47 becoming unbalanced. Therefore,
It is possible to operate the circuit as designed even after a while after the operation starts.

Further, it is possible to prevent loss of the complementary characteristic between the first and second power transistors 42 and 43 and the complementary characteristic as the characteristic between the complementary third and fourth power transistors 46 and 47. You can In addition, the first, second, third and fourth power transistors 42, 43, 46,
Since the heat balance between the circuit element 47 and the temperature compensating circuit element is achieved, the first, second, and
Third and fourth power transistors 42, 43, 4
When the temperature of 6, 47 rises, the temperature of the circuit element for temperature compensation also rises, and the first, second, third and fourth power transistors 42, 43,
It is possible to prevent the circuit operation from changing due to the imbalance between the temperatures of 46 and 47 and other circuit elements.

When the high thermal conductive pad 52 is interposed between the first, second, third and fourth power transistors 42, 43, 46 and 47 and the module substrate 41, heat dissipation is good. Other than the above, the same effect as above is obtained. [Second Embodiment] Hereinafter, a second embodiment of the present invention, that is, an embodiment of a semiconductor integrated circuit device for mounting and disposing a power semiconductor element that requires only heat balance and does not need heat dissipation This will be described with reference to FIGS. 4 and 5. Here, it is assumed that the semiconductor element is more important to keep the heat balance even if the heat dissipation is sacrificed to some extent. For example, even if the amount of power during operation is relatively small and the possibility of damage due to heat is small, that is, even if it is a power semiconductor element, the power is relatively small, but signal processing characteristics such as video signal amplification are strictly required. It is supposed to be done.

For example, in the worst case, the transistor used in the CRT video signal final amplification stage circuit is 0.5 mm.
Power of 4 W or more is applied to a chip size of × 0.5 mm. Therefore, as shown in FIGS. 4 and 5, when the transistor used in the CRT video signal final amplification stage circuit is mounted, the heat dissipation becomes poor and the transistor is destroyed by heat. Therefore, it cannot be applied to such a circuit. However, it can be applied when there is no possibility of transistor destruction due to heat generation during operation, and a correct rectangular wave can be obtained.

FIG. 4A is a sectional view of a power semiconductor element portion of a semiconductor integrated circuit device in which a power semiconductor element is mounted and arranged, and FIG. 4B is a plan view of the same. FIG. 5 is a cross-sectional view of the power semiconductor element portion of the semiconductor integrated circuit device when the high thermal conductivity pad is interposed between the module substrate and the power semiconductor element body. FIG. 4 (a), (b)
Further, in FIG. 5, reference numeral 71 denotes a module substrate such as a ceramic substrate or a glass / epoxy substrate, and 72, 73, 7
Reference numerals 6 and 77 denote power transistors mounted on the surface of the module substrate 71, and reference numerals 74 and 75 denote thermal diffusion regions indicating regions in which heat generated from the power transistors 72 and 73 diffuses in the module substrate 71. The boundary between the heat diffusion regions 74 and 75 is the module substrate 71.
It spreads radially from the front surface to the back surface, and the spread angle forms an angle of 45 degrees with respect to the perpendicular line standing on the module substrate 71. 78 is a power transistor 72,
73, 76 and 77 are temperature compensating circuit elements that require heat balance, 79 is another mounting component, 81 is a terminal pad, and 82 is a high thermal conductivity pad. a ₁ is a power transistor 7
2 is a mounting distance between the power transistor 73, a ₂ is a mounting distance between the power transistor 76 and the power transistor 77, a ₃ is a mounting distance between the power transistor 72 and the power transistor 76, and a ₄ is a mounting distance between the power transistor 73 and the power transistor 77. , D are the thicknesses of the module substrate 71.

In FIG. 4A, when the power transistors 72 and 73 need only heat balance but no heat dissipation, the power transistors 72 and 73 are mounted at intervals satisfying a ≦ 2 × d. On the back surface of the substrate 41 on the side where the power transistors 72 and 73 are not mounted, as shown in FIG.
The thermal diffusion regions 74 and 75 of 2,73 overlap. As a result, the power transistors 72 and 73 can maintain thermal balance.

In FIG. 4B, when there are four power transistors that require heat balance, the power transistors 72, 73, 76 are circumscribed in the four corners of a square having one side of a ≦ 2 × d. By arranging 77 respectively, the heat balance of the power transistors 72, 73, 76, 77 can be maintained. Also, the power transistor 7
By mounting the temperature-compensating circuit element 78, which needs to be in thermal balance with 2, 73, 76, and 77, inside the square, the thermal balance can be maintained.

FIG. 5 shows a case where a high thermal conductivity pad 82 is sandwiched between the power transistors 72 and 73 and the module substrate 71, and the high thermal conductivity pad 82 is regarded as a power semiconductor element, and FIG. By arranging in the same manner as in a), heat balance can be maintained. As described above, according to the semiconductor integrated circuit device of this embodiment, the heat diffusion regions 74 and 75 in the module substrate 71 due to the heat generation of the first and second power transistors 72 and 73.
Is 45 with respect to a vertical line that stands on the module substrate 71 from the contact surface between the first and second power transistors 72 and 73.
In a state where the heat spread regions 74 and 75 of the first and second power transistors 72 and 73 overlap at least on the back surface of the module substrate 71, and the heat spread regions 74 and 75 spread radially from the front surface to the back surface of the module substrate 71. Therefore, the first and second power transistors 72, 7
3 realizes heat balance, and the temperatures of the first and second power transistors 72 and 73 become unbalanced due to the difference in heat generation amount of the first and second power transistors 72 and 73 after the circuit operation. It is possible to prevent the circuit operation from changing due to this. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

Further, the heat diffusion regions in the module substrate 71 due to the heat generated by the first, second, third and fourth power transistors 72, 73, 76, 77 are the first, second and third.
Third and fourth power transistors 72, 73, 7
The contact surfaces of 6, 77 form an angle of 45 degrees with respect to the vertical line standing on the module substrate 71, and spread radially from the front surface to the back surface of the module substrate 71, and the heat of the first and second power transistors 72, 73 is increased. Boundary of diffusion area, third
And the boundaries of the thermal diffusion regions of the fourth power transistors 76, 77, the first and third power transistors 72,
Since the boundaries of the thermal diffusion regions of 76 and the boundaries of the thermal diffusion regions of the second and fourth power transistors 73 and 77 respectively overlap at least on the back surface of the module substrate 71, the first, the second, the third and the fourth. Of the first, second, third and fourth power transistors 72, 73, 76, 77 after the circuit operation is realized, and the heat balance between the power transistors 72, 73, 76, 77 of 1, second, third and fourth power transistors 72,
It is possible to prevent the circuit operation from changing due to the imbalance of the temperatures of 73, 76 and 77.
Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

The present invention can be applied to the case where a power MOSFET, a power MOSFET, a thyristor, an IGBT or the like is used as the power semiconductor element or the power semiconductor element body.

[0064]

According to the semiconductor device of the first or second aspect, the heat balance between the first and second power semiconductor elements is realized, and the first and second power semiconductor elements are operated after the circuit operation. It is possible to prevent the circuit operation from changing due to the imbalance of the temperatures of the first and second power semiconductor elements due to the difference in the amount of heat generation. Therefore,
It is possible to operate the circuit as designed even after a while after the operation starts.

According to the semiconductor device of the third or fourth aspect, the heat balance between the first, second, third and fourth power semiconductor elements is realized, and the first, second and third circuit operations are performed. Due to the difference in heat generation amount of the third and fourth power semiconductor elements,
It is possible to prevent the circuit operation from changing due to the temperatures of the second, third and fourth power semiconductor elements becoming unbalanced. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

According to the semiconductor device of the fifth or sixth aspect, the heat balance between the first and second power semiconductor elements is realized while ensuring the heat dissipation of the first and second power semiconductor elements. However, the circuit operation changes due to the temperature of the first and second power semiconductor elements becoming unbalanced due to the difference in the amount of heat generated by the first and second power semiconductor elements after the circuit operation. Can be prevented. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

According to the semiconductor device of claim 7 or 8, while ensuring the heat dissipation of the first, second, third and fourth power semiconductor elements, the first, second, third and fourth semiconductor elements are secured. A heat balance between the fourth power semiconductor elements is realized, and the first, second, third, and fourth power semiconductor elements have different heat generation amounts after the circuit operation, and the first, second, third, and fourth power semiconductor elements are different. It is possible to prevent the circuit operation from changing due to the temperature of the power semiconductor device of No. 4 becoming unbalanced. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

According to the semiconductor device of the ninth aspect, it is possible to prevent loss of the complementary property as the characteristic between the complementary first and second power semiconductor elements. According to the semiconductor device of the tenth aspect, the characteristic of the complementary first and second power semiconductor elements and the complementary characteristic as the characteristic of the complementary third and fourth power semiconductor elements are lost. Can be prevented.

According to the semiconductor device of the eleventh aspect, after the circuit operation is started, the first, second, third and fourth circuits are provided.
When the temperature of the power semiconductor element of rises, the temperature of the circuit element for temperature compensation also rises,
It is possible to prevent the circuit operation from changing due to the imbalance of the temperatures of the first, second, third and fourth power semiconductor elements and the temperature compensating circuit element.

According to the semiconductor device of the twelfth aspect, the heat diffusion region is expanded and the heat dissipation can be improved. Others are the same as those of the semiconductor device according to claims 1, 3, 5, and 7. According to the semiconductor device of the thirteenth aspect, the heat diffusion region is expanded and the heat dissipation can be improved. Others are claims 2, 4, 6, 8
It is similar to the semiconductor device described. According to the semiconductor device of claim 14, while ensuring the heat dissipation of the plurality of sets of power semiconductor elements, the heat balance between the plurality of sets of power semiconductor elements is realized, and the plurality of sets of power semiconductor elements after the circuit operation are realized. It is possible to prevent the circuit operation from changing due to the imbalance of the temperatures of the plurality of sets of power semiconductor elements due to the difference in the heat generation amount of the semiconductor elements. Therefore, it is possible to operate the circuit as designed even after a while after the operation is started.

According to the semiconductor device of the fifteenth or sixteenth aspect, the heat balance between the plurality of sets of power semiconductor elements and the temperature compensating circuit element is achieved, so that a plurality of sets are provided after the circuit operation is started. When the temperature of the set of power semiconductor elements rises, the temperature of the temperature compensating circuit element also rises in the same manner, and the temperatures of the plurality of sets of power semiconductor elements and the temperature compensating circuit element become unbalanced. It is possible to prevent the circuit operation from changing due to the balance.

[Brief description of the drawings]

1A is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 1B is a plan view of the same.

FIG. 2 is a cross-sectional view of a semiconductor integrated circuit device when a high thermal conductivity pad is interposed in the first embodiment of the present invention.

3 is a waveform diagram of an output signal of the semiconductor integrated circuit device of FIG.

FIG. 4A is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 4B is a plan view of the same.

FIG. 5 is a cross-sectional view of a semiconductor integrated circuit device with a high thermal conductivity pad interposed in a second embodiment of the present invention.

FIG. 6 is a circuit diagram of an active load feedback circuit.

7A is a cross-sectional view of the semiconductor integrated circuit device of this conventional example, and FIG. 7B is a plan view of the same.

8 is a waveform diagram of an output signal of the semiconductor integrated circuit device of FIG.

[Explanation of symbols]

 1 constant current source pnp type power transistor 2 grounded emitter npn type power transistor 3 npn type power transistor for push pull circuit 4 pnp type power transistor for push pull circuit 5 push pull circuit voltage reduction compensation diode 11 module substrate 12 power transistor 13 power Transistor 14 Thermal diffusion area 15 Thermal diffusion area 16 Power transistor 17 Power transistor 18 Push-pull circuit Reduce voltage compensation diode 19 Chip resistor 21 Terminal pad 41 Module substrate 42 Power transistor 43 Power transistor 44 Thermal diffusion area 45 Thermal diffusion area 46 Power Transistor 47 Power transistor 48 Diode 49 Chip resistor 51 Terminal pad 52 High thermal conductivity pad 71 Module board 2 power transistors 73 power transistors 74 thermal diffusion region 75 thermal diffusion region 76 a power transistor 77 a power transistor 78 the circuit elements 79 mounted component 81 terminal pads 82 highly thermally conductive pad

Claims (16)

[Claims] 1. A semiconductor device in which first and second power semiconductor elements are mounted on a module substrate, wherein the mounting intervals of the first and second power semiconductor elements are:
The boundary between the thermal diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the second power semiconductor element on the module substrate. A semiconductor device, characterized in that the boundary is set to overlap at least on the back surface of the module substrate. 2. A semiconductor device in which first and second power semiconductor elements are mounted on a module substrate, wherein a mounting interval a between the first and second power semiconductor elements is provided.
Is set so that the relation of a ≦ 2 × d is satisfied, where d is the thickness of the module substrate. 3. A semiconductor device in which first, second, third and fourth power semiconductor elements are mounted on a module substrate, wherein the mounting intervals of the first and second power semiconductor elements are
The boundary between the thermal diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the second power semiconductor element on the module substrate. The boundary is set to overlap at least on the back surface of the module substrate, and the mounting intervals of the third and fourth power semiconductor elements are set to:
The boundary of the heat diffusion region radially extending from the contact surface of the third power semiconductor element on the module substrate and the boundary of the heat diffusion region radially extending from the contact surface of the fourth power semiconductor element on the module substrate. The boundary is set to overlap at least on the back surface of the module substrate, and the mounting interval of the first and third power semiconductor elements is set to:
The boundary between the thermal diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the third power semiconductor element on the module substrate. The boundary is set to overlap at least on the back surface of the module substrate, and the mounting interval of the second and fourth power semiconductor elements is set to:
The boundary between the thermal diffusion region radially extending from the contact surface of the second power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the fourth power semiconductor element on the module substrate. A semiconductor device, characterized in that the boundary is set to overlap at least on the back surface of the module substrate. 4. A semiconductor device in which first, second, third and fourth power semiconductor elements are mounted on a module substrate, wherein a mounting interval a _{1 of} the first and second power semiconductor elements is set.
Is set to satisfy the relationship of a ₁ ≦ 2 × d, where d is the thickness of the module substrate, and the mounting interval a _{2 of} the third and fourth power semiconductor elements is
Is set so as to satisfy the relationship of a ₂ ≦ 2 × d, and the mounting interval a _{3 of} the first and third power semiconductor elements is set.
Is set so as to satisfy the relationship of a ₃ ≦ 2 × d, and the mounting interval a _{4 of} the second and fourth power semiconductor elements is set.
Is set so as to satisfy the relationship of a ₄ ≦ 2 × d. 5. A semiconductor device in which first and second power semiconductor elements are mounted on a module substrate, wherein the mounting intervals of the first and second power semiconductor elements are:
The boundary between the thermal diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the second power semiconductor element on the module substrate. A semiconductor device, wherein a boundary is set to be in contact with the back surface of the module substrate. 6. A semiconductor device in which first and second power semiconductor elements are mounted on a module substrate, wherein a mounting interval a between the first and second power semiconductor elements is set.
Is set so that the relation of a = 2 × d is satisfied, where d is the thickness of the module substrate. 7. A semiconductor device in which first, second, third and fourth power semiconductor elements are mounted on a module substrate, wherein the mounting intervals of the first and second power semiconductor elements are
The boundary between the thermal diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the second power semiconductor element on the module substrate. The boundary is set to be in contact with the back surface of the module substrate, and the mounting intervals of the third and fourth power semiconductor elements are set as follows.
The boundary of the heat diffusion region radially extending from the contact surface of the third power semiconductor element on the module substrate and the boundary of the heat diffusion region radially extending from the contact surface of the fourth power semiconductor element on the module substrate. The boundary is set to be in contact with the back surface of the module substrate, and the mounting intervals of the first and third power semiconductor elements are
The boundary between the thermal diffusion region radially extending from the contact surface of the first power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the third power semiconductor element on the module substrate. The boundary is set to be in contact with the back surface of the module substrate, and the mounting interval of the second and fourth power semiconductor elements is
The boundary between the thermal diffusion region radially extending from the contact surface of the second power semiconductor element on the module substrate and the thermal diffusion region radially extending from the contact surface of the fourth power semiconductor element on the module substrate. A semiconductor device, wherein a boundary is set to be in contact with the back surface of the module substrate. 8. A semiconductor device in which first, second, third and fourth power semiconductor elements are mounted on a module substrate, wherein a mounting interval a _{1 of} the first and second power semiconductor elements is set.
Is set to satisfy the relationship of a ₁ = 2 × d, where d is the thickness of the module substrate, and the mounting interval a _{2 of} the third and fourth power semiconductor elements is
Is set so as to satisfy the relationship of a ₂ = 2 × d, and the mounting interval a _{3 of} the first and third power semiconductor elements is set.
Is set to satisfy the relationship of a ₃ = 2 × d, and the mounting interval a _{4 of} the second and fourth power semiconductor elements is set to
Is set so as to satisfy the relationship of a ₄ = 2 × d. 9. The semiconductor device according to claim 5, wherein the first and second power semiconductor elements are complementary types. 10. The semiconductor device according to claim 7, wherein the first and second power semiconductor elements are complementary types, and the third and fourth power semiconductor elements are complementary types. 11. A first, a second and a second of a module substrate.
A circuit element for temperature compensation is mounted at a position surrounded by the third and fourth power semiconductor elements, wherein the temperature compensation circuit element is mounted.
13. The semiconductor device according to claim 1. 12. The power semiconductor element comprises a power semiconductor element body and a high thermal conductive pad interposed between the power semiconductor element body and the module substrate, and the mounting interval is the interval between the high thermal conductive pads. 8. The semiconductor device according to claim 1, 3, 5, or 7, wherein the heat diffusion region radially extends from a contact surface of the high thermal conductivity pad on the module substrate. 13. A power semiconductor element comprises a power semiconductor element main body and a high thermal conductive pad interposed between the power semiconductor element main body and a module substrate, and a mounting interval is the interval of the high thermal conductive pads. Claims 2, 4,
The semiconductor device according to 6,8. 14. A plurality of sets of complementary power semiconductor elements on a module substrate are radially spread from a contact surface of the power semiconductor element on the module substrate, and a boundary of a heat diffusion region is at least continuous on the back surface of the module substrate. A semiconductor device arranged in a state of being in contact with an annular shape. 15. A plurality of sets of complementary power semiconductor elements on a module substrate are radially spread from a contact surface of the power semiconductor element on the module substrate, and a boundary of a heat diffusion region is at least continuous on the back surface of the module substrate. A semiconductor device, which is arranged in a state of being in contact with a ring, and a circuit element for temperature compensation of the power semiconductor element is arranged at a position surrounded by the power semiconductor element. 16. A circuit element for temperature compensation of the power semiconductor element is surrounded by a plurality of sets of complementary power semiconductor elements on a module substrate, and the circuit element is connected to the power semiconductor element on the module substrate. A semiconductor device, which is arranged on a heat diffusion region radially extending from a surface.