JPS59149046A - Monolithic planar processed intergrated circuit - Google Patents

Abstract

PURPOSE:To obtain an N-P-N transistor,in which a latch-up is not generated through the operation of a thyristor, by forming an N<+> layer for further isolating a vertical P-N-P transistor and the N-P-N transistor, additionally constituting a parastic transistor and applying reverse bias to the parastic transistor to the state of interruption. CONSTITUTION:An N-P-N transistor 300 amplifies an input signal applied to a base teminal 23, and a P-N-P transistor 100 amplifies the signal and outputs an output signal from itself to a collector terminal 4. When the vertical P-N-P transistor 100 is brought to a saturated region, when collector voltage equalizes to approximately emitter voltage, currents flow through a parastic resistor 10 and the potential of a diffusion isolation layer 13 rises because a parastic transistor 9 is forward-biassed and the base currents of a parastic transistor 8 are flowed. However, a latch-up by a parastic transistor 24 and the N-P-N transitor 300 can be avoided because a parastic transistor 7 for the N-P-N transistor 300 is not operated when potential through which a section between a base and an emitter is brought to a reverse bias state at all times is connected previously to a base terminal 20.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a monolithic planar process integrated circuit that can be used in a semiconductor integrated circuit using a particle PNP transistor.

Conventional configuration and its problems P used in bipolar monolithic semiconductor integrated circuits
As the NP) transistor element, a particle type is often used, which has a smaller element area than the conventional lateral type and has an excellent DC current amplification factor with respect to the collector current.

A conventional monolithic planar process integrated circuit will be described below with reference to the drawings.

Figure 1 (C is a cross-sectional view of a part where transistors (particularly PNP) transistors (NPN) are formed adjacent to each other in a conventional planar bipolar process;
) shows an example of an equivalent circuit diagram including elements (hereinafter referred to as parasitic elements) that occur in addition to the original transistor elements shown in FIG.

In addition, the element symbols enclosed in circles in FIGS. 1 and (B) indicate parasitic elements. In Figure 1 (8), 1.2.3 and 4.
6.5 are the collector, emitter, and base terminals of the PNP and NPN transistors, respectively; 13 is a P-type diffusion isolation layer for electrically isolating each transistor; 16 is a P-type silicon substrate; 7 to 12 indicates a parasitic element. Further, FIG. 1(B) shows the configuration of an amplifier circuit, in which the same parts as in the first circuit are given the same reference numerals, 18 is a base-emitter resistance, and 19 is a current limiting resistance.

The operation of the conventional monolithic planar process integrated circuit configured as described above will be described below.

In FIG. 1(B), N P N transistor 2o
amplifies the input signal applied to base terminal 3 and converts the PNP
Transistor 100 further amplifies the signal and supplies the output signal to a load connected to collector terminal 4. Here, when the PNP transistor 100 operates in the active region, the collector-emitter voltage ■cE
When is large to a certain extent, the parasitic transistor 9 is in a cutoff state, and the other parasitic transistors 8 and 7 are also in a cutoff state, so that there is no adverse effect on the amplification operation.

However, in the above configuration, when the PNP transistor 100 enters the saturation region, that is, when the collector voltage becomes approximately equal to the voltage of the emitter 5, the parasitic transistor 9 operates, and the collector current of the parasitic transistor 8 increases. The base current becomes the parasitic transistor 8,
In order to flow a current from the collector 4 of the PNP transistor to the substrate 16 through the isolation diffusion layer 13 shown in FIG.
The potential of the isolation diffusion layer 13 around the PNPI transistor increases. This causes a problem in that the emitter potential of the parasitic PNP transistor 7 of the adjacent NPN transistor 200 increases, and the parasitic PNP transistor and the NPN transistor 200 operate as thyristors, causing rattling. In the above explanation, the NPN) transistor 200 is used to drive the PNP transistor 1oo, but in other cases, the same problem may occur if the NPN) transistor 200 is an adjacent NPN) transistor with a relatively low collector potential. not.

OBJECTIVE OF THE INVENTION 6 No. 2 An object of the present invention is to provide a monolithic sonic planar process integrated circuit that enables an NPN bipolar transistor that does not cause latte-up (thyristor operation) due to parasitic elements. The monolithic soplanar process integrated circuit of the present invention comprises P
a type substrate, and a particle P formed on the P type substrate.
NP) is equipped with a transistor, and the particulate PNP
) N+ so that it is included in the emitter part of the transistor
A diffusion layer is formed as an emitter, and the particle PN
P) With the emitter of the transistor as the base and the base of the particle PNP transistor as the collector, N
A P N ) transistor is configured, the collector of the particle PNP transistor is set at the same potential as the P type substrate, and a reverse bias voltage is applied to the isolation N region of the particle PNP transistor. This makes it possible to construct an NPN transistor that does not cause ratte-up due to parasitic elements.

DESCRIPTION OF EMBODIMENTS OF THE 6 BASE S Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2(5) is a cross-sectional view of a monolithic planar process integrated circuit according to an embodiment of the present invention, particularly a portion where an NPN transistor and a particle PNP transistor are formed adjacent to each other. 2 shows an equivalent circuit including parasitic elements when an amplifier is configured using the two transistors shown in FIG. 2 (5).

Within the second round, 21, 22.23 and 4°6.5
are the collector and base of the N P N transistor and the particle PNP transistor, respectively.

an emitter terminal, 13 a P-type diffusion isolation layer for electrically isolating each transistor, 16 a P-type substrate, 7
．． 24 is a parasitic PrJP transistor of the NPN transistor, 25 is a parasitic resistance in the P+ layer that separates the NPN transistor, 17 and 20 are terminals of the P+ layer and N+ layer, respectively, to separate the NPN transistor, 1o is a P
The parasitic resistance of the mold substrate, 8.9, is a particle PN, respectively.
11.12 are the parasitic resistances of the collector P+ layer and base N layer of the particle PNP transistor, respectively. Further, in FIG. 2(B), the same parts as in FIG. 2(5) are given the same reference numerals, 18 is a base-emitter resistance, and 19 is a current limiting resistance.

The operation of the monolithic planar process integrated circuit of this embodiment configured as described above will be described below. In FIG. 2(B), the NPN transistor 300 amplifies the input signal applied to the base terminal 23, and the PNP transistor 100 further amplifies the signal and outputs the output signal to the collector terminal 4. Here, when the particle PNP transistor 1o○ enters the saturation region, that is, when the collector voltage becomes almost equal to the emitter voltage, the parasitic transistor 9 is forward biased and the base current of the parasitic transistor 8 flows, so that the parasitic resistance 1o A current flows to increase the potential of the diffusion separation layer 13. However, N
Since the parasitic transistor 7 of the PN transistor 300 will not operate if the base terminal 2o is connected to a potential such that the base-emitter is always in a reverse bias state, the parasitic transistor 24 and the NPN transistor 300
Latch-up (thyristor operation) due to this can be avoided.

As described above, according to this embodiment, a parasitic transistor is added by adding a layer for isolation to the conventional N P N transistor, and the parasitic transistor is reverse biased to be in a cut-off state, thereby preventing rattling due to thyristor operation. It is possible to realize an NPN transistor without

Effects of the Invention As is clear from the above explanation, the present invention allows an NPN transistor to be constructed by simply forming an N+ layer within the emitter P layer of a conventional particle PNP transistor, without increasing the conventional manufacturing process. , an excellent effect can be obtained in that an NPN transistor that does not cause latch-up can be obtained. This has the excellent effect of allowing circuits with a high possibility of output transistor saturation to be included in integrated circuits, such as the output stage when driving high-velocity loads such as motors and speakers. It will be done.

[Brief explanation of the drawing]

Figure 1 (5) is an enlarged sectional view of the main part of a conventional monolithic planar process integrated circuit, and Figure 1 (B) is Figure 1 (8).
An equivalent circuit diagram of FIG.
(in Fig. 2) is an equivalent circuit diagram of Fig. 2). 7... Parasitic transistor, 10... Substrate parasitic resistance, 13... Inter-element diffusion isolation layer, 16...
...P type substrate, 17,2o...NPN
) Transistor separation layer terminal, 21... Collector terminal, 22... Emitter terminal, 23...
Base terminal, 24... Parasitic transistor. Name of agent: Patent attorney Toshio Nakao and 1 other person
Figure 1 (c) Figure 2
(A)], 4

Claims (1)

[Claims] a P-type substrate; and a particle PNP transistor formed on the P-type substrate;
N+ so that it is included in the emitter part of the P transistor
A diffusion layer is formed as an emitter, and the particle PN
An NPN transistor is configured with the emitter of the P transistor as a base and the base of the particle PNP transistor as a collector;
1. A monolithic planar process integrated circuit, characterized in that the collector of the transistor is at the same potential as the P-type substrate, and a reverse bias voltage is applied to the isolation N region of the particle PNP transistor.