JPH09129708A - Control of substrate processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent adverse effects on a substrate under processing when a transfer waiting time has occurred. SOLUTION: When a transfer waiting time has occurred, the first skip mode is executed. For a substrate located downstream from the longest processing time unit, processing is performed until a transfer path is completed. In the meantime, transfer is stopped for the substrate located upstream from the longest processing time unit. When an alarm is generated during the execution of the first skip mode, the second skip mode is executed. Processing is continued until the transfer path is completed for a substrate located at a path after an alarm generating unit. In the mean time, transfer is stopped for a substrate located upstream from the alarm unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling a substrate processing apparatus for processing a substrate such as a semiconductor wafer or a liquid crystal display substrate while sequentially carrying the substrates to a plurality of processing units according to a preset carrying path.

[0002]

2. Description of the Related Art In a substrate processing apparatus, a substrate is transferred to each processing unit by a transfer robot according to a processing recipe that defines the order (transfer path) of transferring the substrate to each processing unit and the processing conditions in each processing unit. ,
Processing is executed in each processing unit. By the way, depending on the processing recipe, the processing unit with the longest processing time (hereinafter referred to as “longest processing time unit”)
Processing time may be longer than one transfer time by the transfer robot (total time required to transfer a substrate in each processing unit to the next processing unit). In such a case, a waiting time (hereinafter, referred to as “transfer waiting time”) occurs before the time when the transfer robot transfers the next substrate to the longest processing time unit. For this reason,
The processing in the longest processing time unit is rate-limiting, and the operating speed of the entire substrate processing apparatus is limited. Conventionally, the transportation of the entire substrate processing apparatus is stopped when the transportation waiting time occurs.

[0003]

However, if the processing of the substrate is stopped midway, the substrate being processed may be adversely affected in the process. For example, if the progress of the process of heating the substrate is stopped, the heat treatment is performed for a longer time than planned, resulting in so-called overbaking (excessive heat treatment).

The present invention has been made in order to solve the above-mentioned problems in the prior art, and control that can prevent adverse effects on the substrate being processed in the process even when a transfer waiting time occurs. The purpose is to provide a method.

[0005]

Means for Solving the Problem and Its Action / Effect To solve at least a part of the above-mentioned problem, a first invention is to sequentially process a substrate to be processed into a plurality of processing units in accordance with a preset transport path. A method of controlling a substrate processing apparatus which carries out processing while transporting the substrate, wherein, in response to occurrence of a waiting time for transporting a substrate to a longest processing time unit having the longest processing time among the plurality of processing units, Substrates located downstream of the longest processing time unit in the transport path continue to be processed and transported until the transport path is completed, and substrates located upstream of the longest processing time unit are transported. And a first skip mode for canceling.

In this way, since the processing can be completed for the substrates located on the downstream side of the longest processing time unit, it is possible to prevent at least the adverse effects on the processing of these substrates.

In the first invention, when an alarm for notifying an abnormality of any one of the plurality of processing units is generated during execution of the first skip mode, an alarm is generated in the transport path. A second skip mode in which processing and transportation are continued for a substrate located downstream of the unit until the transportation path is completed, and transportation is stopped for a substrate located upstream of the alarm generation unit. Is preferably provided.

In this way, since the processing can be completed for the substrates located on the downstream side of the alarm generating unit, it is possible to prevent at least adverse effects on the processing of these substrates.

[0009]

Other Embodiments of the Invention The present invention includes the following other embodiments. A first aspect is a control device of a substrate processing apparatus that sequentially processes a substrate to be processed while sequentially transferring the substrate to a plurality of processing units according to a preset transfer path, and the processing time in the plurality of processing units is reduced. A transfer waiting time generation detecting unit that detects occurrence of a waiting time of transfer for delivering a substrate to the longest processing time unit that is the longest, and a transfer waiting time from the longest processing time unit in the transfer path according to the occurrence of the transfer waiting time. The first skip mode execution is performed in which the substrate located on the downstream side is continuously processed and transported until the transportation path is completed, and the substrate located on the upstream side of the longest processing time unit is stopped. And means.

In a second aspect, in addition to the first aspect, an alarm for notifying an abnormality of any one of the plurality of processing units is generated during execution of the first skip mode. Occasionally, for the substrate located on the downstream side of the alarm generation unit in the transportation path, the processing and the transportation are continued until the transportation path is completed, and the substrate positioned on the upstream side of the alarm generation unit is transported. And a second skip mode executing means for canceling.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

A. First Embodiment: Next, an embodiment of the present invention will be described based on an embodiment. FIG. 1 is a perspective view showing a semiconductor wafer processing apparatus to which an embodiment of the present invention is applied. This semiconductor wafer processing apparatus performs a series of processes on a semiconductor wafer W (coating process, developing process, heating process, cooling process in this embodiment).
It is a spinner provided with a plurality of processing units for performing. The first processing unit group A arranged on the front surface includes a spin coater SC for performing a coating process and a spin developer SD for performing a developing process.

A second processing unit group B is provided at a position on the rear side facing the first processing unit group A. The second processing unit group B includes hot plates HP1 to HP3 and cool plates CP for performing various heat treatments.
1 to CP3.

Further, this apparatus is provided with a transfer area C extending along the first processing unit group A at a position sandwiched between the first processing unit group A and the second processing unit group B. There is. In the transfer area C, a transfer robot 10 is movably arranged. The transfer robot 10 includes a moving body 12 having a support member 11 having two arms for supporting the semiconductor wafer W (only one arm is visible in the drawing). The upper and lower two arms constituting the support member 11 are driven by an arm drive mechanism (not shown), and the semiconductor wafer is exchanged in each processing unit. That is, one arm receives the semiconductor wafer after the processing from the processing unit, and the other arm places the semiconductor wafer transported from another processing unit on the processing unit.
Although not shown, a three-dimensional drive mechanism is connected to the moving body 12 of the transfer robot 10. This drive mechanism moves the moving body 12 to the front of each processing unit to enable delivery of the semiconductor wafer W.

An indexer IND which carries out the semiconductor wafer W from the cassette 20 and carries the semiconductor wafer W into the cassette 20 is provided at the end of the semiconductor wafer processing apparatus. The transfer robot 40 provided in the indexer IND takes out the semiconductor wafer W from the cassette 20 and sends it out to the transfer robot 10, or conversely receives the semiconductor wafer W which has been subjected to a series of processing from the transfer robot 10, and receives the semiconductor wafer W from the cassette 20. Perform the work to return to. FIG.
Although not shown in the figure, an interface unit for transferring the semiconductor wafer W to / from another processing apparatus (for example, an exposure apparatus such as a stepper) is provided at the opposite end (right side in the drawing) of the indexer IND. It is provided. The transfer of the semiconductor wafer W between the semiconductor wafer processing apparatus of the embodiment and another processing apparatus is performed by the mobile robot (not shown) provided in the interface unit and the transfer robot 10.
This is done by cooperating with and.

FIG. 2 is a block diagram of the semiconductor wafer processing apparatus of FIG. In FIG. 2, the controller 50 is
Arithmetic unit (CPU) and main memory (RAM and RO
M), which is an arithmetic processing unit to which a display 51 and a keyboard 52 are connected. Controller 5
0 is a transfer robot 10 or a transfer robot 40 (robot of the indexer IND) according to a preset processing recipe, and each processing unit SC, SD, HP1 to H
Controls the operation of P3, CP1 to CP3. The controller 50 further includes a conveyance waiting time occurrence detecting means for detecting occurrence of a conveyance waiting time, an alarm detecting means for detecting occurrence of an alarm from the processing unit, and a skip mode execution for executing two skip modes described later. It has a function as a means.

Software programs (application programs) for realizing various functions by the controller 50 are transferred from a portable storage medium (portable storage medium) such as a floppy disk or a CD-ROM to the controller 5.
0 is transferred to the main memory or the external storage device.

FIG. 3 is an explanatory view showing an example of a semiconductor wafer transfer path in the semiconductor wafer processing apparatus. In this example, the semiconductor wafer is transferred from the indexer IND to the hot plate HP1, the cool plate CP1, the spin coater SC, the hot plate HP2, and the cool plate CP2 in this order, and processed by each processing unit.
Finally, it is returned into the cassette 20 of the indexer IND.
In FIG. 3, reference numerals n to (n-6) written in the blocks showing the respective processing units indicate the numbers of the semiconductor wafers processed by the respective processing units. That is, in the state of FIG. 3, the (n-6) th wafer is the cool plate CP.
The wafer is cooled by 2 and the (n-5) th wafer is heated by the hot plate HP2. Similarly, the subsequent wafers are also processed in their respective processing units. The n-th wafer described at the position of the indexer IND has been taken out from the cassette 20 by the transfer robot 40, and is in a state of waiting on a pin (not shown) to be transferred to the transfer robot 10.

Paths P1 to P between the processing units
6 corresponds to the operation of being carried by the carrying robot 10. In this embodiment, the path P on the left end of FIG.
The wafer existing between 1 and the path P6 at the right end is referred to as "wafer being processed". Therefore, each processing unit HP
The wafer processed in 1, CP1, SC, HP2, CP2 is the “wafer being processed”. On the other hand, the wafer waiting on the pin of the indexer IND (the wafer described in the block indicating the indexer IND) is not the “wafer being processed”.

The transport path shown in FIG. 3 is registered in the processing recipe preset by the user. The processing recipe is data that defines a transport path and processing conditions in each processing unit. The controller 50 uses the transfer robot 10 and the transfer robot 40 according to this processing recipe.
And each processing unit. That is, when the semiconductor wafer processing apparatus is operating normally, the wafers are sequentially processed according to the transfer path shown in FIG. In this example, it is assumed that the spin coater SC is the longest processing time unit.

Assuming that the time required to transfer the wafer in each pass is 8 seconds, the transfer robot 1
The total time required for 0 to carry all the paths P1 to P6 once (referred to as “total carrying time”) is 48 seconds. Processing units HP1, CP1, SC, HP2, CP
When the processing time in the longest processing time unit of 2 is longer than the total transfer time, the transfer waiting time occurs in the transfer robot 10.

FIG. 4 is a flow chart showing the control operation when the conveyance waiting time occurs. In step S1, the controller 50 determines whether a conveyance waiting time has occurred. For example, a semiconductor wafer is loaded into the spin coater SC, which is the longest processing time unit, and the time until the processing is completed (called “remaining processing time”) is shorter than the total transfer time (48 seconds) of the transfer robot 10. When it is long, it is determined that the conveyance waiting time has occurred.

In step S2, delivery of a new wafer from the indexer IND is prohibited. As a result, the operation of transferring a new wafer from the indexer IND to the transfer robot 10 is stopped.

In step S3, with respect to the wafer under processing located on the transfer path downstream of the longest processing time unit (spin coater SC), the processing and the transfer are continued. On the other hand, the wafer under processing located on the transfer path upstream of the longest processing time unit is made to stand by at the standby position in each processing unit after the processing in that processing unit is completed. Hereinafter, the operation of step S3 will be referred to as "first skip mode". In the example shown in FIG. 3, the processing and transfer of the wafers in process ((n-5) th and (n-4) th wafers) located on the transfer path downstream of the spin coater SC are continued as they are, and the indexer Return to IND. On the other hand, the in-process wafers ((n-2) th and (n-1) th wafers) located on the path upstream of the spin coater SC are made to wait at the standby position after the processing in the processing unit is completed.

FIG. 5 is an explanatory diagram showing the flow of the wafer in the case of shifting to the first skip mode due to the occurrence of the transfer waiting time. The leftmost column in FIG. 5 shows the processing cycle. Here, one cycle means a period in which each wafer is processed by one processing unit and is transferred to the next processing unit. In addition, the upper IND, HP1,
CP1 and the like indicate the respective processing units, and the numbers written below them indicate the order of the wafers. Further, the code “x” indicates that there is no wafer.

In the processing cycle 4, when the first wafer reaches the spin coater SC which is the longest processing time unit,
Transfer waiting time occurs. As a result, the first skip mode is executed, and the wafers existing in the processing units HP1 and CP1 on the upstream side of the spin coater SC are in the standby state after the processing in each processing unit is completed. In addition,
At this point, there is no wafer being processed in the processing units HP2 and CP2 on the downstream side of the spin coater SC.

During the execution of the first skip mode (step S3), the delivery of the wafer from the indexer IND remains stopped. The delivery of the wafer from the indexer IND is restarted when the following condition C1 or C2 is satisfied in the next step S4 (step S5).

Condition C1: (remaining processing time of the longest processing time unit) .ltoreq. (Operating time of the indexer) + (total transport time of paths between the indexer and the longest processing time unit)

Here, the "operating time of the indexer" means
This is the time required for the indexer IND to take out one wafer from the cassette 20 and deliver it to the transfer robot 10. Further, “the total transport time of the paths between the indexer and the longest processing time unit” is the total transport time of the three paths P1 to P3 in the case of FIG. 3, and is therefore 24 seconds.

Condition C2: The wafer existing in the processing unit next to the unit having the longest processing time on the transfer path is transferred to the most downstream processing unit.

In the example of FIG. 3, the "processing unit next to the longest processing time unit" is the second hot plate HP.
2 and the “downstream processing unit” is the second cool plate CP2.

The right side of the inequality sign of the above first condition C1 is
This is the shortest time required for the transport robot 10 to reach the longest processing time unit from the position of the indexer IND (referred to as "shortest arrival time"). Therefore, when the first condition C1 is satisfied, that is, when the remaining processing time of the longest processing time unit becomes less than or equal to the shortest arrival time of the transfer robot 10, it can be considered that there is no net transfer waiting time. . Therefore, at this time, in step S5, the delivery of a new wafer from the indexer IND is restarted, and when the processing in the longest processing time unit is completed, the wafer can be immediately passed from the indexer IND to the transfer robot 10 so that the dead time is lost. Prevent it from happening.

When the second condition C2 is satisfied, it is expected that the wafer will soon return from the most downstream processing unit to the indexer IND. Therefore, even when the second condition C2 is satisfied, the indexer IND
Return the wafer to the new wafer with the new indexer IN
By allowing D to be replaced immediately, wasted time is prevented.

In the processing cycle 4 of FIG. 5, since there are no wafers in the processing units HP2 and SP2 on the downstream side of the spin coater SC, the above second condition C2 is satisfied. Therefore, in process cycle 4, the delivery of the wafer from the indexer IND is virtually not stopped.

When the processing in the longest processing time unit is completed (step S6 in FIG. 4), the wafer transfer is restarted and the process returns to step S1. For example, when the processing cycle 4 in FIG. 5 is completed, the first wafer is transferred from the spin coater SC to the hot plate HP2, and the wafers waiting in each processing unit upstream of the spin coater SC are also transferred to the next processing unit. To be done. Then, in the processing cycle 5, when the spin coater SC, which is the longest processing time unit, starts processing the second wafer, a transfer waiting time occurs, so steps S2 and S3 in FIG. 4 are executed again. At this point, since the first wafer is present in the next processing unit (hot plate HP2) of the spin coater SC, the processing and transfer of the first wafer are continuously executed in step S3. As a result, in the processing cycles 5 to 7 in FIG. 5, the first skip mode is executed and only the first wafer is sequentially transferred.

In the processing cycle 7 of FIG. 5, when the processing of the spin coater SC, which is the longest processing time unit, is completed, the wafers on the upstream side of the spin coater SC are transferred to the next processing units. Then, in the processing cycle 8, when the spin coater SC, which is the longest processing time unit, starts processing the third wafer, a transfer waiting time occurs, so steps S2 and S3 in FIG. 4 are executed again.

As described above, in the first skip mode,
When processing is started in the spin coater SC, which is the longest processing time unit, processing and transportation are continued for wafers existing in the downstream path of the spin coater SC, while wafers existing in the upstream path of the spin coater SC are continued. For, the transportation is stopped. Therefore, with respect to the wafer existing on the path on the downstream side of the longest processing time unit, the processing can be completed without adversely affecting the process such as overbaking.

By the way, in the example of FIG. 5, before the processing of the spin coater SC, which is the longest processing time unit, is completed,
The processing and transfer of the wafer downstream of the spin coater SC has been completed. However, depending on the processing recipe, the processing of the spin coater SC, which is the longest processing time unit, may be completed before the processing and transfer of the wafer downstream of the spin coater SC is completed.

As shown in the example of FIG. 5, when the processing and transfer of the wafer downstream of the spin coater SC is completed before the processing of the spin coater SC, which is the longest processing time unit, is completed, the above-mentioned first process is performed. The condition C1 of is not necessary. FIG.
If it is determined in step S4 of step S4 that the restart of the wafer delivery is determined using only the second condition, in the processing cycles 5 and 6 of FIG.
The fifth wafer is in a non-standby state.

On the other hand, if the processing of the spin coater SC, which is the longest processing time unit, is completed before the processing and transfer of the wafer downstream of the spin coater SC is completed, the second condition C2 is unnecessary. The user can also select and use only one of the two conditions C1 and C2 according to the processing recipe.

B. Second Embodiment: FIG. 6 is a flowchart showing the operation in the second embodiment of the present invention. The flowchart of FIG. 6 includes a step S between the steps S3 and S4 of the flowchart of the first embodiment shown in FIG.
11 to S13 are added. As described in step S11, the operation of FIG. 6 is an operation when an alarm is issued from any of the processing units in the middle of the first skip mode.

Each processing unit generates an alarm and notifies the controller 50 when any abnormality is detected. The alarm is, for example, a shortage of the amount of the chemical liquid in the spin coater SC, a temperature abnormality in the hot plates HP1 and HP2, or the like. The controller 50 informs the user of this alarm in step S11, and at the same time, in step S12.
In step S13, control according to the alarm occurrence is executed.

In the processing of the second skip mode in step S12, the controller 50 processes and transfers the wafer under processing located on the transfer path after the processing unit that issued the alarm (referred to as "alarm generating unit"). Continue as is. On the other hand, the wafer being processed, which is located on the transfer path before the alarm generating unit, is made to wait at the standby position of the processing unit after the processing in the processing unit is completed.

The wafer existing in one of the paths P1 to P6 between the processing units when the alarm is issued is delivered to at least the next processing unit.

Further, depending on the substrate processing apparatus and the processing recipe, a plurality of processing units that are equivalent to each other may be arranged in parallel on the transfer path. For example, in FIG. 3, a plurality of hot plates are arranged in parallel at the position of the hot plate HP1. In such a case, when one of a plurality of processing units equivalent to each other arranged in parallel generates an alarm, the processing is continued to the end even for wafers existing in another processing unit equivalent to the alarm generation unit. To be done.

FIG. 7 is an explanatory view showing the operation contents in the case of shifting to the second skip mode due to the alarm generation in the middle of the first skip mode in the second embodiment. The example in FIG. 7A is an example in which the processing unit (cool plate CP2) on the downstream side of the spin coater SC, which is the longest processing time unit, issues an alarm in the processing cycle 5 in FIG. As described above, when the alarm generation unit is located downstream of the longest processing time unit, the wafer existing upstream of the alarm generation unit is in the standby state in the second skip mode.

The example of FIG. 7B is an example in which a processing unit (cool plate CP1) on the upstream side of the spin coater SC which is the longest processing time unit issues an alarm. As described above, when the alarm generation unit is located upstream of the longest processing time unit, the wafer existing upstream of the alarm generation unit (in the example of FIG. 7B, the fourth wafer on the hot plate HP1). The wafer) is in the standby state in the second skip mode. Further, the wafer after the alarm generation unit and on the upstream side of the longest processing time unit (the third wafer on the cool plate CP1 in the example of FIG. 7B) waits in the first skip mode. It becomes a state. Further, since the first skip mode is applied to the wafer on the downstream side as viewed from both the alarm generation unit and the longest processing time unit, the processing and the transfer are continued.

As described above, when an alarm is issued in the middle of the first skip mode, the first skip mode and the second skip mode are executed in a multiple manner. As can be seen from the above description, the second skip mode has priority over the first skip mode. When the alarm is released in step S13 of FIG. 6, the process is continued from the state of being suspended in the second skip mode.

In the above-described second embodiment, when the alarm is issued in the middle of the first skip mode, the second skip mode is executed to process and transfer the wafers existing in the path after the alarm generating unit. And so on. Therefore, with respect to the wafer existing on the path after the alarm generation unit, the processing can be completed without adversely affecting the process such as overbaking.

The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the scope of the invention.
For example, the following modifications are possible.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a semiconductor wafer processing apparatus to which an embodiment of the present invention is applied.

FIG. 2 is a block diagram of a semiconductor wafer processing apparatus.

FIG. 3 is an explanatory diagram showing a transfer path of a semiconductor wafer W in the semiconductor wafer processing apparatus.

FIG. 4 is a flowchart showing an operation in the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a flow of wafers when a skip mode is entered due to an alarm generation.

FIG. 6 is a flowchart showing the operation of the second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing the operation contents of a multiple skip mode in the second embodiment.

[Explanation of symbols]

 10 ... Transport robot 11 ... Support member 12 ... Moving body 20 ... Cassette 40 ... Transfer robot 50 ... Controller 51 ... Display 52 ... Keyboard CP1-CP3 ... Cool plate HP1-HP3 ... Hot plate IND ... Indexer SC ... Spin coater (rotating type) Chemical coating device SD: Spin developer (rotary chemical developing device 9)

Claims (2)

[Claims] 1. A method of controlling a substrate processing apparatus for sequentially processing a substrate to be processed to a plurality of processing units along a preset transfer path, wherein the processing time is the longest among the plurality of processing units. In accordance with the occurrence of the waiting time of the transfer for transferring the substrate to the longest processing time unit, the substrate located on the downstream side of the longest processing time unit in the transfer path is processed until the transfer path is completed. The method for controlling a substrate processing apparatus, further comprising: a first skip mode in which the substrate is positioned on the upstream side of the longest processing time unit and is stopped. 2. The method for controlling a substrate processing apparatus according to claim 1, wherein an alarm for notifying an abnormality of any one of the plurality of processing units during execution of the first skip mode. When occurs, for the substrate located on the downstream side of the alarm generation unit in the transfer path, while continuing the processing and transfer until the transfer path is completed,
A method for controlling a substrate processing apparatus, comprising: a second skip mode for stopping the transportation of a substrate located upstream of the alarm generation unit.