JPH09127196A - Ic tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC tester which is high in the degree of freedom and effective by providing a plurality of adders and multiplier to carry out various modulation on one modulation data. SOLUTION: Modulation data are changed over and given to the first and the second adder 1, 3 or a multiplier 6 for enlarging the degree of freedom. Namely, data composed of frequency data and modulation data which are added by the first adder 1 are inputted, and a phase accumulator 2 outputs phase data. The phase data sent from the phase accumulator and the modulation data are added by the second adder 3, and a sine wave table memory 4 outputs amplitude data with added data used as address. The amplitude data sent from the sine wave table memory 4 and the modulation data are mutually multiplayed by a multiplier 6, and a D/A converted signal is given to a tested object 9.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an object to be tested (I
IC that applies a modulated signal to C, LSI, etc.) for testing
The present invention relates to an IC tester having a high degree of freedom, a small circuit scale, and a short test time.

[0002]

2. Description of the Related Art A conventional IC tester is a device under test (I
C, LSI, etc.), the data of the modulated signal to be given to the device under test is stored in the memory in advance, the data is taken out from this memory and converted into an analog signal by the D / A converter. It was giving a signal to the test object.

In the case of such a configuration, there are the following problems. Since a plurality of test signals are required for the test of the test object, a memory is required for each test signal given to the test object. Since the modulated signal must store data according to the frequency of the carrier wave, a large capacity memory is required.

When the number of memories is reduced, a plurality of test signals are output, so that it takes a long time to write a large amount of data in the memories, resulting in a long test time. For example, when the object to be tested is an FM demodulator, the FM modulated wave and the AM modulated wave whose modulation signals are the same are input and the test is performed. I had to remember.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to realize an IC tester having a high degree of freedom, a small circuit scale and a short test time.

[0006]

According to the present invention, there is provided a first adder for adding frequency data and modulated data, and a phase accumulator for inputting data from the first adder and outputting phase data. , A second adder for adding the phase data and the modulation data from the phase accumulator, a sine wave table memory for outputting amplitude data with the data added by the second adder as an address, and the sine wave It has a multiplier that multiplies the amplitude data from the table memory by the modulation data, and a D / A converter that converts the data from this multiplier into an analog signal and gives it to the device under test, and switches the modulation data. Is applied to the first adder, the second adder, or the multiplier.

[0007]

In the present invention as described above, the modulation data is switched and given to the first adder, the second adder or the multiplier. The first adder performs frequency modulation by adding the modulation data and the frequency data. The second adder performs phase modulation by adding the modulation data and the data from the phase accumulator. And
The multiplier performs amplitude modulation by multiplying the modulation data and the amplitude data from the sine wave table memory. In this way, various types of modulation can be performed with one modulation data.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In the figure, reference numeral 1 denotes a first adder, which adds frequency data for determining a carrier frequency stored in the register 10 and modulation data.

A phase accumulator 2 receives the data from the adder 1 and outputs the phase data. The phase accumulator 2 is composed of an adder 21 and a register 22, and cumulatively adds the data from the adder 1. A second adder 3 adds the phase data from the phase accumulator 2 and the modulation data.

Reference numeral 4 is a sine wave table memory, which outputs amplitude data using the data added by the adder 3 as an address. An adder 5 adds the modulation data and the carrier level data stored in the register 50. A multiplier 6 multiplies the amplitude data from the sine wave table memory 4 by the data from the adder 5.

Reference numeral 7 is a switching unit, which is a modulation data a, b and "0".
Data and data are switched by a control signal of a control unit (not shown) and given to the adders 1, 3, and 5. The switching unit 7 is composed of selectors 71 to 73. The selector 71 selects the modulation data a, b, “0” data by the control signal of the control unit and inputs it to the adder 1 as the modulation data. Similarly, the selector 72 selects the modulation data a, b, “0” data by the control signal of the control unit and inputs it to the adder 3 as the modulation data. The selector 73 uses the modulated data a,
b, "0" data is selected by the control signal of the control unit and input to the adder 5 as modulation data.

Reference numeral 8 denotes a D / A converter which converts the data from the multiplier 6 into an analog signal and supplies it to a device under test (hereinafter abbreviated as DUT) 9. Here, the modulation data a. Although b is generally data sequentially output from the memory, it may be digital data output from the direct digital synthesizer.

The operation of such a device is performed by the DUT 9 using the FM.
The case of a (frequency modulation) demodulator and the case of a QAM (quadrature amplitude modulation) demodulator will be described below. When DUT9 is an FM demodulator. The selector 71 selects the modulation data a according to the control signal from the control unit, and the adder 1
The selector 72 selects “0” data, and the adder 3
The selector 73 selects “0” data, and the adder 5
Give to.

As a result, the adder 1 adds the modulation data a and the frequency data of the register 10 and gives it to the phase accumulator 2. The phase accumulator 2 performs cumulative addition of the input data and outputs it to the adder 3. Adder 3
Outputs the data from the phase accumulator 2 because the data from the selector 72 is "0". The sine wave table memory 4 outputs amplitude data using the data from the adder 4 as an address. The adder 5 is the selector 7
Since the data from 3 is "0", the carrier level data of the register 50 is output. Then, the multiplier 6 multiplies the amplitude data from the sine wave table memory 4 and the carrier level data from the adder 5 and gives the product to the D / A converter 8. The D / A converter 8 converts the data from the multiplier 6 into an analog signal and supplies it to the DUT 9.

The DUT 9 demodulates the analog signal and outputs the demodulated signal. The IC tester inputs the demodulated signal through an A / D converter (not shown), compares the modulated data with the modulated data a, and tests the DUT 9. If they match, the DUT 9 is judged to be a non-defective product, and if they do not match, it is judged to be a defective product.

Next, according to a control signal from the control section, the selector 71 selects "0" data and supplies it to the adder 1, the selector 72 selects "0" data and supplies it to the adder 3, and the selector 73 modulates. The data a is selected and given to the adder 5.

As a result, the adder 1 supplies the frequency data of the register 10 to the phase accumulator 2 because the data from the selector 71 is "0". The phase accumulator 2 performs cumulative addition of the input data, and the adder 3
Output to Since the data from the selector 72 is “0”, the adder 3 outputs the data from the phase accumulator 2. The sine wave table memory 4 outputs amplitude data using the data from the adder 4 as an address. The adder 5 adds the modulated data a and the carrier level data of the register 50 and outputs it. Then, the multiplier 6 multiplies the amplitude data from the sine wave table memory 4 and the data from the adder 5 and gives the result to the D / A converter 8. The D / A converter converts the data from the multiplier 6 into an analog signal and gives it to the DUT 9.

The DUT 9 demodulates the analog signal and outputs the demodulated signal. The IC tester inputs the demodulated signal through the A / D converter, compares the modulated data with the modulated data a, and tests the DUT 9. If they match, the DUT 9 determines that the product is defective, and if they do not match, it determines that the product is non-defective.

When the DUT 9 is a QAM demodulator. A phase modulation component and an amplitude modulation component are assigned to the modulation data a and b, respectively. The selector 71 is controlled by the control signal from the control unit.
Selects "0" data and supplies it to the adder 1, and the selector 72
Selects the modulation data a and supplies it to the adder 3, and the selector 73
Selects the modulation data b and supplies it to the adder 5.

As a result, since the data from the selector 71 is "0", the adder 1 gives the frequency data of the register 10 to the phase accumulator 2. The phase accumulator 2 performs cumulative addition of the input data and outputs it to the adder 3. The adder 3 adds the modulated data a and the data of the phase accumulator 2 and outputs it. The sine wave table memory 4 outputs amplitude data using the data from the adder 4 as an address. The adder 5 outputs the modulated data b
And the carrier level data of the register 50 are added and output. Then, the multiplier 6 multiplies the amplitude data from the sine wave table memory 4 and the data from the adder 5 to obtain D
/ A converter 8 The D / A converter converts the data from the multiplier 6 into an analog signal and gives it to the DUT 9.

The DUT 9 demodulates the analog signal and outputs the demodulated signal. The IC tester inputs the demodulated signal through the A / D converter, compares the modulated data a and b with each other, and tests the DUT 9. If they match, the DUT 9 is judged to be a non-defective product, and if they do not match, it is judged to be a defective product.

In this way, since the modulation data can be switched by the switching unit 7 to perform various types of modulation, the degree of freedom is high. Further, since the same modulation data can be used for different modulations, it is not necessary to store the modulated signal (test signal) for each modulation in the memory, so that the circuit scale can be reduced. Similarly, since it is not necessary to store the modulated data at the frequency of the carrier wave in the memory, the circuit scale can be reduced. Further, since it is not necessary to write a long modulated signal in the memory, the test time can be shortened.

Needless to say, a low-pass filter is not provided between the D / A converter 8 and the DUT 9 in the embodiment, but it is necessary in the actual configuration. Further, although the switching unit 7 has shown the example of switching the modulation data a, b, and “0” data, the present invention is not limited to this, and one modulation data and “0” data may be switched. Further, in the embodiment, the configuration in which the carrier level is changed by the adder 5 is shown, but the present invention is not limited to this, and a configuration in which the carrier level is added to the output of the D / A converter 8 in an analog manner may be used. .

[0024]

The present invention has the following effects. Since various kinds of modulation can be performed by switching the modulation data, the degree of freedom is large. Further, since the same modulation data can be used for different modulations, it is not necessary to store the modulated signal (test signal) for each modulation in the memory, so that the circuit scale can be reduced. Similarly, since it is not necessary to store the modulated data at the frequency of the carrier wave in the memory, the circuit scale can be reduced. And
Since it is not necessary to write a long modulated signal to the memory,
The test time can be shortened.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

[Explanation of symbols]

 1,3 Adder 2 Phase accumulator 4 Sine wave table memory 6 Multiplier 7 Switching unit 8 D / A conversion unit 9 DUT

Claims (1)

[Claims] 1. A first adder for adding frequency data and modulated data, a phase accumulator for inputting data from the first adder and outputting phase data, and phase data for the phase accumulator. And a second adder for adding the modulated data, and the data added by the second adder as an address,
A sine wave table memory that outputs amplitude data, a multiplier that multiplies the amplitude data from this sine wave table memory by the modulation data, and a D signal that is converted from the data from this multiplier into an analog signal and is given to the device under test. / A converter, and supplies modulated data to the first adder, the second adder, or the multiplier by switching the modulated data.