JPH09260949A - Signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal generator with which a waveform can be instantaneously switched without expanding circuit scale by applying data outputted from a storage part to an arithmetic part while switching them. SOLUTION: Parameter banks 1a-1d at the storage part respectively store the parameters of frequency data, gain value and offset value. Besides, plural pieces of data are stored in plural registers. An arithmetic part 2 performs arithmetic corresponding to the data from the parameter register banks 1a-1d, and the data are converted into an analog signal by a D/A converter 3 and outputted. Registers 4a-4d are provided on the signal line of a register switching signal, hold the register switching signal, respectively apply the register switching signal to the parameter register banks 1a-1d and output the register switching signal to the following stage. Therefore, since the data outputted from the parameter register banks 1a-1d are switched while being followed up at the switching point of the waveform, the waveform can be instantaneously switched without being distorted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator used in, for example, an IC tester, and more particularly to a signal generator capable of instantaneously changing an output signal.

[0002]

2. Description of the Related Art A conventional digital signal generator is used to change an output signal such as a sine wave or a modulated wave.
It is common to rewrite the contents of the setting register for each parameter. Such a device is shown in FIG. Here, an example of a signal generator that outputs a modulated signal is shown. In the figure, reference numeral 10 denotes an arithmetic unit which inputs data from the registers 21 to 23 and performs arithmetic operations. 20 is a D / A converter,
The calculation result of the calculation unit 10 is converted into an analog signal and output.

In the arithmetic unit 10, a DDS (Direct Digital Synthesizer) 11 outputs sine wave digital data using the data of the register 21 as frequency data. Reference numeral 12 is a register which inputs and holds the data from the DDS 11. A multiplier 13 multiplies the data from the register 12 by the data from the register 22. 1
Reference numeral 4 is a register for inputting and holding the data from the multiplier 13. An adder 15 adds the data from the register 14 and the data from the register 23. Reference numeral 16 is a register, which inputs and holds the data from the adder 15 and
Output to the D / A converter 20.

The operation of such a device will be described below.
The parameter data is held in the registers 21 to 23.
The arithmetic unit 10 performs an arithmetic operation using these data and outputs the data. The D / A converter 20 outputs this data as an analog signal. To change the output signal,
The data held in the registers 21 to 23 is changed, and the arithmetic unit 10 performs an arithmetic operation based on the changed data and outputs the data in the same manner as above. This data is converted to D / A converter 2
0 outputs as an analog signal.

[0005]

In the device having such a configuration, the registers 21 to 2 are used to change the waveform to be output.
It is necessary to rewrite 3, and it takes time to rewrite all the registers. As a result, the IC tester cannot instantaneously perform another test, which requires a long test time.

As a countermeasure against this, the configuration shown in FIG. 3 can be considered. The signal generators 30 and 40 are provided, and the switch 50
The signal generators 30 and 40 are switched to output. As a result, different waveforms can be instantaneously switched and output, but the circuit scale becomes large. here,
The insides of the signal generators 30 and 40 have the same configuration as the device shown in FIG. Therefore, an object of the present invention is to realize a signal generator capable of instantaneously switching waveforms without increasing the circuit scale.

[0007]

According to the present invention, a storage unit for storing parameters, an operation unit for performing an operation using data from the storage unit, and a D for converting the operation result of the operation unit into an analog signal and outputting the analog signal. / A converter, and switches the parameters stored in the storage unit to give them to the arithmetic unit.

In the present invention as described above, the parameters stored in the storage unit are switched and given to the arithmetic unit. The arithmetic unit performs an arithmetic operation based on the data from the storage unit. Then, the D / A converter converts the calculation result of the calculation unit into an analog signal and outputs it.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numerals 1a to 1d denote parameter register banks which are storage units, and respectively include frequency data, gain values,
Stores parameters for offset value and gain value.
The parameter register banks 1a to 1d store a plurality of data by a plurality of registers. Reference numeral 2 denotes an arithmetic unit, which performs an arithmetic operation based on the data from the parameter register banks 1a to 1d. A D / A converter 3 converts the calculation result of the calculation unit 2 into an analog signal and outputs it. 4a ~
A register 4d is provided on the signal line of the register switching signal, holds the register switching signal, supplies the register switching signal to each of the parameter register banks 1a to 1d, and outputs the register switching signal to the register in the subsequent stage.

In the calculation unit 2, 2a is a DDS, which outputs digital data of a sine wave using the data from the parameter register bank 1a as frequency data. Reference numeral 2b is a register, which holds the data from the DDS 2a. A multiplier 2c multiplies the data from the register 2b by the data from the parameter register bank 1b. 2d is a register, which holds the data from the multiplier 2c. 2e is an adder, which adds the data from the parameter register bank 1c and the data from the register 2d. 2f is a register, which holds the data from the adder 2e. A multiplier 2g multiplies the data from the parameter register bank 1d by the data from the register 2f. Reference numeral 2h is a register, which holds the data from the multiplier 2g and outputs it to the D / A converter 3. Here, each unit operates with the same clock. Further, the registers 4b to 4d are provided corresponding to the registers 2b, 2d, and 2f forming the pipeline delay.

The operation of such a device is described below.
When the register switching signal "A" is at the first clock, the register 4a
Is held. The register 4a outputs a register switching signal "A" to the parameter register bank 1a and the register 4b. As a result, the parameter register bank 1a
Outputs the data of the register corresponding to the register switching signal "A" to the DDS 2a.

At the second clock, the register 4b holds the register switching signal "A", and the parameter register bank 1
b and register 4c. Then, the parameter register bank 1b outputs the data of the register corresponding to the register switching signal "A" to the multiplier 2c. At this time, the register 2b uses the data of the parameter register bank 1a corresponding to the register switching signal "A" to perform DDS.
The result calculated by 2a is held.

At the third clock, the register 4c holds the register switching signal "A", and the parameter register bank 1
c and register 4d. Then, the parameter register bank 1c outputs the data of the register corresponding to the register switching signal "A" to the adder 2e. At this time, the register 2d has the parameter register bank 1 corresponding to the data of the register 2b and the register switching signal "A".
The result calculated by the multiplier 2c is held with the data of b.

At the fourth clock, the register 4d holds the register switching signal "A", and the parameter register bank 1
Output to d. And the parameter register bank 1d
Outputs the data in the register corresponding to the register switching signal "A" to the multiplier 2g. At this time, register 2f
Holds the result calculated by the adder 2e based on the data of the register 2d and the data of the parameter register bank 1c corresponding to the register switching signal "A".

At the fifth clock, the register 2h uses the data of the register 2f and the data of the parameter register bank 1d corresponding to the register switching signal "A" to multiply the multiplier 2
The result calculated by g is held and output to the D / A converter 3.
At this time, for the first time, the D / A converter 3 outputs a waveform corresponding to the register switching signal "A".

Similarly, when the register switching signal "B" is input, the registers 4a to 4d sequentially hold the register switching signal "B" every clock and output it to the next register. At the same time, the registers 2b, 2d, 2f, 2h hold and output the data input every clock.

As described above, since the data output from the parameter register banks 1a to 1d are switched by the register switching signal and given to the arithmetic unit 2, the waveforms can be switched instantaneously without increasing the circuit scale. . Further, since the registers 4a to 4d corresponding to the pipeline delay inside the arithmetic unit 2 are provided in the signal line of the register switching signal, the data output from the parameter register banks 1a to 1d are switched at the waveform switching point. . In other words, the waveforms can be switched without instantaneously disturbing the waveforms at the time of output.

The present invention is not limited to the above embodiment, and various internal configurations of the arithmetic unit 2 are conceivable. For example, a configuration may be added in which a circuit configuration that adds phase modulation to the calculation unit 2 is added. In short, any configuration may be used as long as the parameters are switched and given to the calculation unit that performs calculation.

[0019]

According to the first aspect of the present invention, since the data output from the storage unit is switched and given to the arithmetic unit, the waveform can be switched instantaneously without increasing the circuit scale. According to the second aspect, since the register corresponding to the pipeline delay inside the arithmetic unit is provided in the signal line of the switching signal, the data output by the parameter of the storage unit is switched following the switching point of the waveform. In other words, the waveforms can be switched without instantaneously disturbing the waveforms at the time of output.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional signal generator.

FIG. 3 is a configuration diagram showing another conventional signal generator.

[Explanation of symbols]

 1a to 1d Parameter register bank 2 Calculation unit 2b, 2d, 2f, 2h, 4a to 4d register 3 D / A converter

Claims (2)

[Claims] 1. A storage unit for storing parameters, a calculation unit for performing calculation by data from the storage unit, and a D / A converter for converting the calculation result of the calculation unit into an analog signal and outputting the analog signal. Then, the signal generation device is characterized in that the parameters stored in the storage unit are switched and given to the arithmetic unit. 2. A register provided on the signal line of the switching signal for switching the parameters of the storage unit in correspondence with the pipeline delay inside the arithmetic unit and providing the switching signal to the storage unit. The signal generator according to claim 1.