JP3016258B2 - FSK signal modulation / demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK signal modulation / demodulation circuit, and more particularly to an FSK signal modulation / demodulation circuit having a built-in test circuit for easily testing digitally inside a circuit without requiring a large-scale analog signal measuring device. .

[0002]

2. Description of the Related Art In the marginal number shift keying (hereinafter referred to as FSK) system, data signals are allocated with "0" assigned to a high frequency and "1" assigned to a low frequency to transmit data. Used for

FIG. 8 shows a waveform diagram of an FSK modulation / demodulation signal.
8A shows the digital data (or demodulated data) of the original signal, and FIG. 8B shows the FSK signal. The “0” level and the “1” level of the digital data are the high level of FIG. 8B, respectively. It corresponds to frequency and low frequency period.

For digital data communication, F
Although an integrated circuit having a built-in SK modulation / demodulation function is used, an integrated circuit having a high-functionality and a complicated function is required to be able to easily test the function.

FIG. 7 is a block diagram showing an example of a conventional integrated circuit test circuit having a built-in FSK modulation / demodulation function.

First, the demodulation mode will be described. FSK
FSK signal input to signal input terminal 9 (FIG. 8 (b))
Is input to the filter circuit 2 via the multiplexer (MPX) circuit 1. This filter circuit 2 removes unnecessary frequency components from the input FSK signal and
The FSK signal is input to the FSK demodulation circuit 5 via the. The FSK demodulation circuit 5 demodulates the input FSK signal and outputs demodulated data from the FSK demodulated signal output terminal 11 (FIG. 8).
(A)) is output.

Next, in the modulation mode, the original data signal (FIG. 8 (a)) is input to the FSK modulation data input terminal 13 of the FSK modulation circuit 7a, and the FSK modulation circuit 7a
In FIG. 8, the input data signal is FSK-modulated (FIG. 8).
(B)), input to the filter circuit 2 via the MPX circuit 1; The filter circuit 2 removes unnecessary frequency components from the input signal in the same manner as at the time of demodulation, and the FSK signal from the filter circuit 2 is output from the modulation signal output terminal 12 to the FSK via the MPX circuit 3.

Next, in the test mode, the output terminal of the FSK modulation circuit 7a is connected to the MPX circuit 1, the filter circuit 2,
It is connected to the input terminal of the FSK demodulation circuit 5 via the MPX circuit 3. Accordingly, the original data signal (FIG. 8 (a)) input to the FSK modulation circuit 7a is FSK-modulated, and then FSK-demodulated again to reproduce the original data signal, and the FSK demodulation signal output terminal of the FSK demodulation circuit 5 1
1 is output. Therefore, by comparing the original data signal input to the FSK modulation circuit 7a with the demodulated signal output from the FSK demodulated signal output terminal 11,
The operation function of each circuit inside the integrated circuit can be tested.

[0009]

SUMMARY OF THE INVENTION The above-mentioned conventional FSK
In the signal modulation / demodulation circuit, an extra dedicated measuring instrument or dedicated tester is required externally in order to determine the functional operation test. Further, the FSK modulation data input terminal 13
Filter circuit 2 via signal input terminal 9 and MPX circuit 1
However, there is a disadvantage that it is not possible to test for a defect in a signal path inside the output circuit up to the input.

[0010] The object of the present invention is to eliminate F
An object of the present invention is to provide an FSK signal modulation / demodulation circuit capable of performing a self-test on the SK signal modulation / demodulation circuit by itself without requiring a dedicated measuring instrument and a dedicated tester.

[0011]

SUMMARY OF THE INVENTION An FSK modulation / demodulation circuit according to the present invention comprises: an FSK modulation circuit for modulating a frequency shift keying signal (hereinafter referred to as an FSK signal) whose frequency changes in response to a binary digital signal; An FSK demodulation circuit for demodulating the FSK signal; a filter circuit for passing a desired frequency band of the FSK signal; and an input terminal of the filter circuit for switching and connecting an FSK signal input terminal or an output terminal of the FSK modulation circuit. 1 multiplexer circuit, a second multiplexer circuit for switching the output terminal of the filter circuit to the input terminal of the FSK demodulation circuit or the FSK signal output terminal, and supplying a test timing signal and the FSK modulation circuit. A test control circuit for outputting test signal data having two or more frequencies, A judging circuit for outputting a judgment result of the determination to match with the incorporation predetermined set value in accordance with the test timing signal the output signal of the demodulating circuit, switched to the FSK signal input terminal and the output signal during a test of the FSK modulation circuit connected Te and a test switch circuit, external
The test control circuit according to the control signal input from the
A first multiplexer circuit, a second multiplexer circuit, and the test switch
The circuit is switched, and the F
Wherein the output signal of the SK modulation circuit is connected to the input of the previous SL first multiplexer circuit. In the present invention, the test switching circuit, the FSK signal FSK modulated signal to the output terminal consists of circuit connected switches to an input terminal of the FSK demodulator circuit during testing, the output of the FSK modulation circuit by the test signal data A signal may be input to the FSK demodulation circuit via the first multiplexer circuit, the filter circuit, the second multiplexer circuit, and the FSK signal output terminal.

[0012]

FIG. 1 is a block diagram of an FSK signal modulation / demodulation circuit including a test circuit according to an embodiment of the present invention.
MPX circuits 1 and 3, filter circuit 2, FSK modulation circuit 7, FSK demodulation circuit 5, determination circuit 4, test control circuit 8
It is composed of The operation of the test circuit in the demodulation mode and the modulation mode is the same as in the conventional example.

In the test mode, the control signal input terminal 1
4 controls the test control circuit 8 according to the control signal input to
A test data signal 16 for generating a test mode data signal is supplied to the SK modulation circuit 7. The test data signal 16 causes the FSK modulation circuit 7 to output a test mode FSK signal. Further, the control signal causes F
The output of the SK modulation circuit 7 is a switching circuit 6 for testing, FSK
Signal input terminal 9, MPX circuit 1, filter circuit 2, MP
The signal path is switched so that the signal is input to the FSK demodulation circuit 5 via the X circuit 3.

Therefore, the test mode FSK signal output from the FSK modulation circuit 7 is input to the determination circuit 4 after unnecessary frequency components are removed by the filter circuit 2 and demodulated again by the FSK demodulation circuit 5. In the determination circuit 4, FSK
A digital comparison and determination of a test data signal before being subjected to modulation and a data signal obtained by performing a modulation / demodulation signal processing on the test data signal are performed, and the determination result is digitally output from a determination result output terminal 10. As a result, the judgment result output terminal 1
The operation test result of the internal modulation / demodulation circuit function can be determined only by measuring the “H” and “L” levels of 0.

Next, a test operation will be described using a specific example of the determination circuit 4. FIG. 2 is a block diagram showing the internal configuration of the decision circuit 4, and FIG. 3 is a timing chart showing the operation of the decision circuit in the test mode.

In FIG . 2 , a decision circuit 4 includes registers 17 to 19 for storing demodulated output data 25 of the FSK demodulation circuit 5 and, based on the contents stored in each register, a judgment of coincidence between the demodulated output data and the input test data. , A data latch timing signal 21 to 23 for the registers 17 to 19, and a timing control circuit 27 for generating a determination timing signal 24 for the decision decoder 20.

The timing control circuit 27 generates various timing signals shown in FIG. 3 based on the timing control signal 26 input from the test control circuit 8. The test is performed at timings T1 to T4. FIG. 3A shows the timing of the signal input period, and FIG. 3B shows the original test data signal before receiving the FSK modulation.
5 shows a data signal subjected to SK modulation and demodulation. FIG. 3 (c),
(D) and (e) are timing signals 21, which determine the data latch timing of the registers 17, 18 and 19, respectively.
22 and 23, and FIG. 3F shows a timing signal 24 for determining the data decision timing of the decision decoder 20.

[0018] FIG. 3 (b) respectively latch the data of the registers 17, 18, 19 demodulated data signal is inputted "0", is "1", "0", the latches data, the decision decoder 20 of only the determination result output terminal 10 when it is determined that the inputted correct, "1" level outputs, that the FSK demodulation circuit operates correctly are tested, it is determined. The test switching circuit 6
Indicates that the output signal of the FSK modulation circuit 7 is FS
K signal input terminal 9 is switched and connected.
Test from the test control circuit 8 according to the control signal 14
The output signal of the FSK modulation circuit 7 based on the signal data 16 is F
Switch to SK signal input terminal 9 or MPX1 input to connect
Continued. Therefore, the signal path on the FSK signal input terminal 9 side
Can also be tested.

In the present embodiment, the case where the decision circuit 4 is constituted by three registers has been described. However, the present invention is not limited to three registers, and is constituted by at least two or more registers. Good.

FIG. 4 is a block diagram showing a second embodiment of the present invention. The same functional blocks and terminals as those in FIG. 1 are denoted by the same reference numerals. This embodiment is a test switching circuit.
6a indicates that the FSK modulation signal to the FSK signal output terminal 12 is
Circuit switched to input terminal of FSK demodulation circuit 5
And the test signal data 1 from the test control circuit 8
The output signal of the FSK modulation circuit 7 is MPX1,
Filter circuit 2, MPX3, and FSK signal output terminal 12.
Input to the FSK demodulation circuit 5. Therefore, the FSK signal
The signal path on the output terminal 12 side can also be tested.

In the test mode, the test control circuit 8 generates a test data signal 16 for generating a test mode data signal from the FSK modulation circuit 7 in response to a control signal input to the control signal input terminal 14. Supply.
The test data signal 16 causes the FSK modulation circuit 7 to output a test mode FSK signal. Further, the control signal causes the output of the FSK modulation circuit 7 to be input to the FSK demodulation circuit 5 via the MPX circuit 1, the filter circuit 2, the MPX circuit 3, the FSK modulation signal output terminal 12, and the test switching circuit 6a. Switch to signal path.

Therefore, as in the first embodiment, the FSK signal for the test mode output from the FSK modulation circuit 7 is obtained after the unnecessary frequency components are removed by the filter circuit 2 and demodulated again by the FSK demodulation circuit 5. Is input to the judgment circuit 4 and the judgment circuit 4 performs a digital comparison judgment of a test data signal before being subjected to FSK modulation and data obtained by modulating / demodulating the test data signal, and digitally judges the judgment result. The result is output from the result terminal 10, and a test result can be obtained in the same manner as described above.

FIG. 5 is a block diagram showing a third embodiment of the present invention. In this embodiment, it is shown that the FSK modulation / demodulation function and the central processing unit (hereinafter referred to as CPU) 30 are formed on the same integrated circuit. In this case, the functions of the determination circuit 4 and the test control circuit 8 can be easily realized by software as a part of the function of the CPU 30. FIG. 6 shows a flowchart for realizing the functions of the determination circuit 4 and the test control circuit 8 by the CPU 30.

[0024]

As described above, according to the present invention, a built-in test circuit can generate a test signal within the circuit to perform a self-test of the FSK modulation / demodulation operation function, and also has an analog signal path. It is possible to perform a connection test on the entire signal path, including the signal path, thereby greatly improving the test accuracy. Furthermore, there is a result that the test itself can be greatly simplified without requiring a large-scale analog measuring device or a tester required in the conventional test.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a determination circuit 4 of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 1;

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation of FIG. 5;

FIG. 7 is a block diagram showing a conventional FSK signal modulation / demodulation circuit.

FIG. 8 is a waveform diagram showing a general FSK signal.

[Explanation of symbols]

 1,3 Multiplexer circuit (MPX) 2 Filter circuit 4 Judgment circuit 5 FSK demodulation circuit 6,6a Test switching circuit 7,7a FSK modulation circuit 8 Test control circuit 9 FSK signal input terminal 10 Judgment result output terminal 11 FSK demodulation signal Output terminal 12 FSK modulation signal output terminal 13 FSK modulation data input terminal 14 Control signal input terminal 15, 26 Timing control terminal 16 Test data signal 17-19 Register 20 Judgment decoder 21-24 Timing signal 25 Demodulation output data 27 Timing control circuit 30 CPU

Claims (3)

(57) [Claims] 1. A frequency shift keying signal (hereinafter referred to as an FSK signal) whose frequency changes in response to a binary digital signal.
An FSK modulation circuit that modulates the FSK signal, a FSK demodulation circuit that demodulates the FSK signal, a filter circuit that passes a desired frequency band of the FSK signal, and an input terminal of the FSK signal input terminal or the FSK modulation circuit that is an input terminal of the filter circuit. A first multiplexer circuit that switches and connects an output terminal, a second multiplexer circuit that switches and connects an output terminal of the filter circuit to an input terminal or an FSK signal output terminal of the FSK demodulation circuit, and a test timing signal. A test control circuit for outputting test signal data having at least two or more frequencies to be supplied to the FSK modulation circuit; an output signal of the FSK demodulation circuit taken in accordance with the test timing signal; And a determination circuit for determining the result and outputting the determination result, and an output signal of the FSK modulation circuit. And a said FSK signal switching circuit for testing is connected by switching to the input terminal during the test, the test control circuit, before the control signal input from the outside
A first multiplexer circuit, a second multiplexer circuit, and the test switch
The circuit is switched, and the F
FSK modulation and demodulation circuit, wherein the output signal of the SK modulation circuit is connected to the input of the previous SL first multiplexer circuit. 2. A frequency shift keying signal whose frequency changes in response to a binary digital signal (hereinafter referred to as an FSK signal).
An FSK modulation circuit that modulates the FSK signal, a FSK demodulation circuit that demodulates the FSK signal, a filter circuit that passes a desired frequency band of the FSK signal, and an FSK signal input terminal or the FSK modulation circuit A first multiplexer circuit that switches and connects an output terminal, a second multiplexer circuit that switches and connects an output terminal of the filter circuit to an input terminal or an FSK signal output terminal of the FSK demodulation circuit, and a test timing signal. A test control circuit for outputting test signal data having at least two or more frequencies to be supplied to the FSK modulation circuit; an output signal of the FSK demodulation circuit taken in accordance with the test timing signal; And a determination circuit for determining the output of the FSK signal output terminal. The FSK K modulation signal during a test
A test switching circuit that is connected to the input terminal of the demodulation circuit by switching.
A test control circuit, the first and second multiplexer circuits
And the test switching circuit is switched, and the output signal of the FSK modulation circuit based on the test signal data is transmitted through the first multiplexer circuit, the filter circuit, the second multiplexer circuit, and the FSK signal output terminal. FSK input to an FSK demodulation circuit
Modulation / demodulation circuit. 3. The method according to claim 1, wherein the determination circuit and the test control circuit are a CPU.
3. The FSK modulation / demodulation circuit according to claim 1, wherein the FSK modulation / demodulation circuit is configured by using: