JPH09116761A - Jbig code decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the configuration small and to realize high speed processing. SOLUTION: A valve of an address counter 13 is fed to an adder 14, in which an adaptive picture element selection signal value is subtracted from the valve of the address counter 13. A 1st changeover switch 15 is operated in a 1 picture element shift period, a value of a counter and a value of the adder are alternately outputted as an address to, e.g. a line memory 12. Then image data whose address is designated by a counter is shifted by one picture element each in a shift register group 21 from the line memory 12 based on a shift clock, and image data whose address is designated by the adder is shifted by one picture element each in the shift register group 22 from the line memory 12 based on a signal the inverse of the shift clock. An arithmetic coding decoding circuit 25 applies 2-line template processing to picture elements from the shift register groups 19, 21 and the arithmetic coding decoding circuit 25 conducts coding decoding processing by using the picture element from the shift register group 22 as an adaptive picture element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a JBI for decoding binarized image data by the JBIG code decoding system.
The present invention relates to a G code decoding device.

[0002]

2. Description of the Related Art JBIG (Joint Bi-level Image Grou)
p) The encoding method is an encoding method of binary image information, and has a compatibility function of progressive transmission and sequential transmission,
It has the features of higher coding efficiency than the MMR (Modified MR) method and high coding efficiency for a wide variety of images. In the predictive coding / decoding method of binary image information studied by JBIG, the color of a pixel to be coded is predicted from a pattern of a plurality of reference pixels called a context. The JBIG context has a 2-line template and a 3-line template.

Further, in the JBIG code decoding system, there is a mode called adaptive pixel movement at the time of code decoding, which makes coding efficiency of an image having periodicity such as pseudo halftone image data advantageous. There is. According to the recommendation, it has an effect of about 80%. Also,
According to the recommendation, the moving range of adaptive pixels (hereinafter referred to as AT pixels) is 1 at maximum before the pixel to be coded and decoded.
Up to the 27th pixel is possible. FIG. 3 shows the moving range of AT pixels in the 2-line template used in the JBIG encoding method. In this figure? Indicates a pixel to be coded, X indicates a normal pixel to be referred to, and A indicates a special pixel to be referred to. Pixels X and A form a 2-line template. In addition, A is a special pixel called an AT pixel whose position is allowed to move for the purpose of improving the compression rate.

A is the standard position of the AT pixel, but is it a pixel to be encoded / decoded optionally? Up to 127 pixels before can be arranged.

For this reason, the conventional JBIG code decoding apparatus has the configuration shown in FIG. That is, a pair of line memories 1 and 2 for alternately storing image data for each line, and an address counter 3 for addressing in order to output image data pixel by pixel from the line memories 1 and 2, are provided. In one certain line, the pixels from the line memory 1 are sequentially shifted to the respective shift registers of the first shift register group 5 via the a contact of the first changeover switch 4, and the pixels from the line memory 2 are shifted to the first line. Two
The shift switches 6 are sequentially shifted to the respective shift registers of the second shift register group 7, and in the next one line, the changeover switches 4 and 6 are switched to shift the pixels from the line memory 1 to the second pixel. Of the shift switch 6 is sequentially shifted to each shift register of the second shift register group 7, and the pixel from the line memory 2 is transferred to the first shift switch 4 through the b contact of the first shift switch 4. The shift registers of the shift register group 5 are sequentially shifted.

The first shift register group 5 is composed of six shift registers S1 to S6 for storing each pixel of the first line of the two-line template, and is 1 when viewed from the line memory.
The AT register at the standard position is stored in the shift register S6 of the stage. The second shift register group 7 includes four shift registers S7 to S10 for storing each pixel on the second line of the two-line template, one shift register S11 for storing pixels to be code-decoded, and pixels to be code-decoded. It is composed of two shift registers S12 and S13 for storing pixels up to two pixels after the above. Then, before the second shift register group 7, an AT pixel shift register group 8 including a large number of shift registers capable of storing up to 127 pixels before the pixel to be coded is connected.

The pixel values of the shift registers S1 to S5 of the first shift register group 5 and the pixel values of the shift registers S7 to S10 of the second shift register group 7 are supplied to the arithmetic code decoding circuit 9 as normal reference pixels. ing. Also, the pixel value of the shift register S6 of the first shift register group 5 and the AT
The pixel value of each shift register of the pixel shift register group 8 is supplied to the AT pixel selection circuit 10. The AT pixel selection circuit 10 selects which pixel to use as an AT pixel based on the AT pixel selection signal, and supplies the selected pixel as an AT pixel to the arithmetic code decoding circuit 9.

In this conventional JBIG code decoding apparatus, for example, when one line of image data is stored in the line memory 2, the address counter 3 outputs an address value to output one pixel of image data from each of the line memories 1 and 2. Output one by one.
At this time, the reference value of the address output is set by the AT pixel selection signal. Thereby, the AT pixel at an arbitrary position can be obtained.

The address counter 3 counts up one by one, and in response thereto, the image data is output from the line memories 1 and 2 pixel by pixel. And line memory 1
Since the image data of one line before is stored in and the new image data is stored in the line memory 2, the image data of the line memory 1 is stored in the first contact via the a contact of the first changeover switch 4. The image data of the line memory 2 is sequentially shifted to each shift register of the shift register group 5, and the image data of the line memory 2 is transferred to the second shift register group 7 and the AT pixel shift register group 8 through the b contact of the second changeover switch 4. The shift registers are sequentially shifted. Address counter 3
When the address value is negative, that is, when the pixel data to be encoded / decoded is not present, the pixel data output from the line memories 1 and 2 is “0”. This is based on the recommendations specifications.

The AT pixel selection circuit 10 selects one position from all the positions of movable AT pixels by the AT pixel selection signal. When the pixel data output from the line memory 2 is shifted by the value set by the AT pixel selection signal, the pixel data at this time is selected by the AT pixel selection circuit 10 and supplied to the arithmetic code decoding circuit 9 as AT pixel information. To be done. Then, the arithmetic code decoding circuit 9 performs the arithmetic code decoding process together with the pixel information of the shift registers S1 to S5 and S7 to S10 of the two-line template.

If the AT pixel position is the 127th pixel, 12 pixels are required to perform arithmetic code decoding processing on the first pixel.
Seven shift operations are necessary, and the time required to start the arithmetic code decoding process becomes long. Further, if the AT pixel position is the 8th pixel, the shift operation is performed 8 times in order to perform the arithmetic code decoding process on the first pixel, and the time until the arithmetic code decoding process is started becomes short. FIG. 5 is a timing chart showing the output of the address counter 3, the output data of the line memory, the shift clock, the pixel values at the points P1 to P5 shown in FIG. 4, and the code decoding start timing. The point P3 is code-decoded. The pixel value of the pixel.

[0012]

As described above, the conventional J
Since the BIG encoding / decoding device is provided with the shift register capable of storing the pixel data up to the 127th pixel in accordance with that the moving range of the AT pixel can be up to the 127th pixel at the maximum before the pixel to be encoded / decoded. , An enormous number of shift registers are required, and the configuration becomes large and AT
When the pixel position is set in the vicinity of the 127th pixel, there is a problem that it takes a long time to start the arithmetic code decoding process and the processing speed becomes slow.

Therefore, according to the present invention, the moving range of the AT pixel can be up to 127th pixel in front of the pixel to be code-decoded without using the AT pixel shift register group consisting of a large number of shift registers. With this, it is possible to reduce the size of the configuration, and the time until the arithmetic code decoding process is started can be made constant in a short time regardless of the position of the AT pixel, thereby realizing a high speed process. provide.

[0014]

According to the first aspect of the present invention,
In a JBIG code decoding device for coding and decoding binarized image data by the JBIG code decoding system, a pair of line memories for alternately storing the image data for each line,
A shift register that shifts the image data from each of the line memories one pixel at a time and stores a plurality of reference pixels including adaptive pixels, which are used for predictive coding and decoding of the pixel to be coded and decoded together with the pixel to be coded and decoded. And an address counter that sequentially outputs the address value of the pixel output from each line memory to the shift register, and the value of the adaptive pixel selection signal is subtracted from the address value of this address counter to output the address value of the adaptive pixel position. The adder, first switching means for alternately fetching the address value of the address counter and the address value of the adder within the one-pixel system period, and supplying the address value of the address counter to one line memory and at the same time by the first switching means. The address value of the fetched address counter and the address of the adder Supplying the value to the other line memory,
In addition, the content of the address value supplied to each line memory is set to 1
Second switching means for switching on a line-by-line basis, adaptive pixel storage means for storing the pixel at the adaptive pixel position output from the line memory to which the address value of the adder is supplied, and adaptive pixel extraction from the shift register by the adaptive pixel selection signal An adaptive pixel selecting means for selecting whether to extract an adaptive pixel from the adaptive pixel storing means, a plurality of reference pixels excluding the adaptive pixel from the shift register, an adaptive pixel from the adaptive pixel selecting means, and a pixel to be encoded / decoded. An arithmetic code decoding circuit for performing predictive code decoding is provided.

In such a configuration, the adder, the first
By providing the switching means, the second switching means, the adaptive pixel storage means, and the adaptive pixel selection means, the address input method to the line memory is changed and the normal image data and the adaptive pixels are taken out substantially at the same time. Can be stored in the adaptive pixel storage means, selectively taken out by the adaptive pixel selection means, and supplied to the arithmetic code decoding circuit.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, a pair of line memories 11 and 12 are provided, and each of the line memories 11 and 1 is provided.
The image data is stored alternately in line 2 for each line. Further, an address counter 13 for sequentially outputting the address value of the pixel output from each of the line memories 11 and 12 is provided, and the address value of the address counter 13 is supplied to the adder 14 and is the first switching means. The third switching which supplies the line memory 12 through the a contact of the changeover switch 15 and further through the a contact of the second changeover switch 16 which constitutes the second changeover means and which constitutes the second changeover means. It is supplied to the line memory 11 via the a contact of the switch 17. Further, the address value of the address counter 13 is supplied to the line memory 12 via the b contact of the second changeover switch 16 and to the line memory 11 via the b contact of the third changeover switch 17. doing.

Each of the line memories 11 and 12 takes in the address value from the address counter 13 and outputs the image data pixel by pixel. The adder 14 subtracts the value of the selection signal of the adaptive pixel (hereinafter referred to as AT pixel) from the address value of the address counter 13 and outputs the address value of the AT pixel position. Then, the output of the adder 14 is supplied to the line memory 12 through the b contact of the first changeover switch 15 and further through the a contact of the second changeover switch 16, and the third changeover switch is also supplied. It is supplied to the line memory 11 via a contact point a of 17.

The first change-over switch 15 is adapted to change over the address corresponding to the line memory in the code decoding pixel line within one pixel shift period. That is, in the one pixel shift period, first, the contact b is turned on to selectively output the output of the adder 14, and then the switching operation is performed to turn on the contact a to turn on the address counter 13.
The address value of is selected and output. The second and third change-over switches 16 and 17 are switched and operated line by line. When the a contact of the second changeover switch 16 is turned on, the b contact of the third changeover switch 17 is turned on. However, when the b contact of the second changeover switch 16 is turned on, the a contact of the third changeover switch 17 is turned on.

The image data from the line memory 11 is sequentially shifted and stored in each shift register of the first shift register group 19 via the a contact of the fourth changeover switch 18, and the fifth changeover switch 20 is also stored. The data is sequentially shifted and stored in each shift register of the second shift register group 21 via the contact a. Further, the image data from the line memory 12 is sequentially shifted and stored in each shift register of the first shift register group 19 via the b contact of the fourth changeover switch 18, and the fifth changeover is performed. The data is sequentially shifted and stored in each shift register of the second shift register group 21 via the b contact of the switch 20.

The fourth changeover switch 18 and the fifth changeover switch 20 are switched and operated for each line. When the contact a of the fourth changeover switch 18 is turned on, the fifth changeover switch 20 is turned on. When the b contact of No. 4 is turned on and the b contact of the fourth changeover switch 18 is turned on, the a contact of the fifth changeover switch 20 is turned on. Therefore, in one line, the pixels from the line memory 11 are sequentially shifted to each shift register of the first shift register group 19 via the a contact of the fourth changeover switch 18, and the line memory 12 is also used. Pixels are sequentially shifted to the respective shift registers of the second shift register group 21 via the b contact of the fifth changeover switch 21, and in the next one line, the changeover switches 18 and 20 are changed.
To shift the pixels from the line memory 11 sequentially to the respective shift registers of the second shift register group 21 via the a contact of the fifth changeover switch 20, and the pixels from the line memory 12 to each other. The shift switches of the first shift register group 19 are sequentially shifted through the b contact of the fourth changeover switch 18.

The first shift register group 19 is composed of six shift registers S1 to S6 for storing each pixel of the first line of the two-line template.
The AT pixel at the standard position is stored in the shift register S6 of the first stage when viewed from the first and the second stages. The second
The shift register group 21 includes four shift registers S7 to S7 for storing each pixel on the second line of the two-line template.
S10 and one shift register S11 for storing pixels to be coded and decoded, and two shift registers S12 and S13 for storing pixels up to two pixels after the pixel to be coded and decoded, a total of seven shift registers.

The image data from the line memory 11 is sequentially shifted and stored in each shift register of the third shift register group 22 constituting the adaptive pixel storage means via the a contact of the fifth changeover switch 20. ,
The image data from the line memory 12 is sequentially shifted and stored in each shift register of the third shift register group 22 via the b contact of the fifth changeover switch 20. The third shift register group 22
Is composed of three shift registers S14 to S16.

The first and second shift register groups 19,
Each shift register 21 shifts in synchronization with the rising edge of the shift clock, and each shift register of the third shift register group 22 shifts the shift clock to the inverter circuit 2.
The shift clock is inverted in 3 and is shifted in synchronization with the rising edge of the inverted signal. The output of the first-stage shift register S6 of the first shift register group 19 (pixel value of point P10) and the third shift register group 2
The output of the shift register S14 at the final stage of 2 (point P9
(Pixel value of) is supplied to the switching circuit 24. The switching circuit 24 constitutes adaptive pixel selection means, and
The switching operation is performed in response to the T pixel selection signal, and the output of the shift register S6 or the output of the shift register S14 is selectively output.

The arithmetic code decoding circuit 25 uses the pixel values of the shift registers S1 to S5 of the first shift register group 19 and the pixel values of the shift registers S7 to S10 of the second shift register group 21 as normal reference pixels. At the same time, the output (pixel value) of the switching circuit 24 is supplied to the arithmetic code decoding circuit 25 as an AT pixel. The arithmetic code decoding circuit 25 is adapted to perform the arithmetic code decoding process by using the pixel information from the switching circuit 24 together with the pixel information of the shift registers S1 to S5 and S7 to S10 of the two line template.

In such a structure, for example, it is now assumed that the second to fifth changeover switches 16, 17, 18, 20 are as shown in the figure. That is, it is assumed that the a contact of the second changeover switch 16, the b contact of the third changeover switch 17, the a contact of the fourth changeover switch 18, and the b contact of the fifth changeover switch 20 are on. In this state, the image data stored in the line memory 12 becomes a code decoding line. It is also assumed that the AT pixel position is set to the tenth pixel (n = 10) before the coded pixel.

The address counter 13 outputs an address value for template reproduction. At this time, it operates so as to select from the fourth pixel before the image data of one line.
This is because when the first pixel is coded and decoded, the previous 4 pixels to the previous 1 pixel are required as a template excluding the AT pixel. The adder 14 outputs a value obtained by subtracting the value (n = 10) of the AT pixel selection signal from the address value of the address counter 13. Further, the first changeover switch 15 switches between the a contact and the b contact within one pixel shift period.

The address value from the address counter 13 is supplied to the line memory 12 via the a contact of the second changeover switch 16 and to the line memory 11 via the b contact of the third changeover switch 17. It In this way, the image data is output from each of the line memories 11 and 12.
Each shift register of the first shift register group 19 shifts and stores the image data from the line memory 11 pixel by pixel by a shift clock. In addition, each shift register of the second shift register group 21 shifts the image data from the line memory 12, that is, the image data of the code decoding line, by one pixel and stores the shifted image data. Further, each shift register of the third shift register group 22 outputs the image data from the line memory 12, that is, the image data of the code decoding line to 1 by the inversion signal of the shift clock.
The data is shifted pixel by pixel and stored. In this way, the third shift register group 22 shifts the value of the AT pixel.

The switching circuit 24 selects the output of the shift register S6, that is, the pixel value of the point P10 and the output of the shift register S14, that is, the pixel value of the point P9. When there is no movement of the AT pixel, the pixel value of the point P10 is selected and output, and when there is movement of the AT pixel, the pixel value of the point P9 is selected and output. Here, when there is no movement of the AT pixel, the value of the third pixel of the image data in the line memory 11 is output, and when there is movement of the AT pixel, the value of -9 pixel is output.

For example, when the value of -9 pixels is output when the AT pixel is moved, the arithmetic code decoding circuit 25
The arithmetic code decoding processing of the code decoding target pixel P3 is performed using each pixel value of the two-line template. The output timing, shift clock, and pixel value of each unit in the above are shown in FIG.

In this way, the adder 14, the first changeover switch 15, the second changeover switch 16, the third changeover switch 17 and the third shift register S14 to S16 are provided.
By providing the shift register group 22 and the switching circuit 24, the address input method for the line memories 11 and 12 is changed to take out the normal image data and the AT pixel substantially at the same time, and the AT pixel is set to the third shift register group. 22 and the switching circuit 24 selectively takes out the arithmetic code decoding circuit 2
5, it is not necessary to provide an enormous number of shift registers capable of storing pixel data up to the 127th pixel. Therefore, the size of the structure can be reduced. Also,
Since the value of the AT pixel position is specified by the address of the line memories 11 and 12 by the output of the adder 14, it takes a short time to start the arithmetic code decoding process regardless of the position of the AT pixel. It can be kept constant, which enables high-speed processing.

[0031]

As described above, according to the first aspect of the present invention, 127 pixels at the maximum before the pixel for which the AT pixel moving range is code-decoded without using the AT pixel shift register group including a large number of shift registers. It is possible to achieve up to the pixel, and this makes it possible to reduce the size of the structure, and the time until the arithmetic code decoding process is started can be made constant in a short time regardless of the position of the AT pixel, which enables high-speed processing. Can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example in the same embodiment.

FIG. 3 is a diagram showing a configuration of a two-line template.

FIG. 4 is a circuit configuration diagram showing a conventional example.

FIG. 5 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

11, 12 ... Line memory 13 ... Address counter 14 ... Adder 15 ... First changeover switch (first changeover means) 16 ... Second changeover switch (second changeover means) 17 ... Third changeover switch (first changeover switch) Switching means 2) 19 ... First shift register group 21 ... Second shift register group 22 ... Third shift register group (adaptive pixel storage means) 24 ... Switching circuit (adaptive pixel selection means) 25 ... Arithmetic code decoding circuit

Claims (1)

[Claims] 1. A JBIG code decoding device for coding and decoding binarized image data by a JBIG code decoding system, and a pair of line memories for alternately storing the image data line by line, and each line memory. Image data from 1
A shift register for shifting a pixel by pixel and storing a plurality of reference pixels including adaptive pixels, which are used together with a pixel to be code-decoded to predictively code the pixel to be code-decoded; and the shift from each line memory. An address counter that sequentially outputs the address value of the pixel to be output to the register, an adder that subtracts the value of the adaptive pixel selection signal from the address value of this address counter, and outputs the address value of the adaptive pixel position, and the address counter First switching means for alternately fetching the address value and the address value of the adder within one pixel system period, and the address value of the address counter is supplied to one line memory and fetched by the first switching means. Address value of address counter and address value of the adder It was supplied to the other line memory, and the supply contents of the address values for the line memories 1
Second switching means for switching on a line-by-line basis, adaptive pixel storage means for storing the pixel at the adaptive pixel position output from the line memory to which the address value of the adder is supplied, and adaptive pixel from the shift register in response to the adaptive pixel selection signal. An adaptive pixel selecting means for selecting whether to take out an adaptive pixel from the adaptive pixel storing means, a plurality of reference pixels excluding the adaptive pixel from the shift register, and an adaptive pixel from the adaptive pixel selecting means, and a code A JB characterized in that an arithmetic code decoding circuit for predictively coding and decoding a pixel to be decoded is provided.
IG code decoding device.