JPH05191635A - Picture reduction method and device - Google Patents

Abstract

PURPOSE:To attain the reduction processing with simple configuration while keeping its intermediate tone even when a picture of a pseudo intermediate tone is reduced. CONSTITUTION:An interleave signal generating circuit 1 generates an interleave signal in a timing corresponding to the reduction rate. Picture element data in an original picture are sequentially inputted to a shift register 2 along the main scanning direction. In this case, when no interleave signal is entered, the inputted picture element data are inputted by all bits and when the interleave signal is entered, after picture element data of a just preceding time are shifted and the inputted picture element data are inputted to a least significant bit and the result is outputted. The output is inverted by an inverting circuit 3 and a reference value (threshold value) and the output of the inverting circuit 3 are compared by a comparator 4 and a binary value is converted into '1' or '0' level therein. The binary data are latched or deleted in a register 5 at a timing of the interleave signal and the result is reduced then by an interleave circuit 6, in which the interleaved picture element data are stored by a prescribed ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reducing method and apparatus suitable for reducing image information such as a facsimile machine or a copying machine.

[0002]

BACKGROUND OF THE INVENTION Binary image information is often reduced in facsimile machines, copiers and the like.
Conventionally, reduction processing has been performed by a logical sum method, an area projection method, or the like described below.

The logical sum method is applied to the reduction in the main scanning direction. For example, when the image is reduced to 1/2, the logical sum of two consecutive pixels in the main scanning direction is calculated and used as one pixel after the reduction. 2 consecutively as shown in FIG. 3 (a).
When either of the pixels A and B is black, the same figure (b)
As shown in, the pixel C after reduction also becomes black.

Similarly, in the case of reducing to 1 / n, the logical sum of n consecutive pixels in the main scanning direction is calculated and this is made one pixel. Therefore, if at least one of the n pixels has black, the pixel after reduction also becomes black.

This logical sum method is suitable for reducing an image expressed in black and white such as a character image, and has an advantage that the structure of the device is simplified. When this logical sum method is applied, the reduction processing in the sub-scanning direction is separately performed by an appropriate method.

The area projection method is to reflect the area ratio of the original image and the reduced image, that is, (reduction rate) 2 = S, to each pixel of the original image. For example, as shown in FIG.
When the image consisting of 9 pixels is reduced to ⅔, that is, 4 pixels, the original image is divided into 4 blocks and each of the blocks A to D is divided.
A value obtained by multiplying S by the ratio of the area occupied by each pixel a to i in FIG.

For example, the data of the A pixel after reduction is expressed by the following equation. However, for convenience, the data value of each pixel is the same as the code (A to D, a to i) of the pixel. A = S {a + (1/2) b + (1/2) d + (1/4) e} = (2/3) 2 {a + (1/2) b + (1/2) d + (1/4) ) E} = 4/9 (1 + 1/4) = 5/9 Here, if the threshold value is set to 4/9, the A pixel becomes black as shown in FIG. In this example, the case of reducing a binary image has been described, but this area projection method is suitable for reducing a pseudo halftone image.

[0008]

In the above logical sum method,
If the decimated pixels are black, this information is always left, so the image is entirely blackish. Therefore, it is not suitable for reducing a pseudo-halftone image such as a photograph.

Further, the area projection method has a problem that the overall configuration becomes complicated because the configuration of the arithmetic circuit must be changed every time the reduction rate changes.

Therefore, the present invention solves the above-mentioned problems and proposes an image reducing method and apparatus capable of holding the halftone of an original image and performing a reducing process with a simple structure. ..

[0011]

In order to solve the above problems, in the present invention, when reducing a binarized image, image reduction is performed by thinning out pixels in the image to reduce in the main scanning direction. In the method, the pixel is multi-valued, the thinned pixel data is added to the remaining pixel data by a ratio corresponding to the reduction ratio, and the remaining pixel data is binarized. It is a thing.

Further, according to the present invention, when the binarized image is reduced, in the image reducing apparatus which performs the reduction in the main scanning direction by thinning out the pixels in the image, the thinning signal is generated at the timing corresponding to the reduction rate. , A shift register for sequentially inputting pixel data in the main scanning direction within the image and shifting the pixel data at the timing of the thinning signal, and an inverting means for inverting the output data of the shift register. And comparing means for comparing the output data of the inverting means with the reference data, a register for holding and outputting the output data of the comparing means or the immediately preceding output data at the timing of the thinning signal, and the timing of the thinning signal for the output data of the register. It is characterized by having a thinning means for thinning out.

[0013]

In FIG. 1, the thinning-out signal generating circuit 1 generates a thinning-out signal at a timing corresponding to the reduction rate (FIG. 2). Here, the case is shown in which the signal is reduced to 1/4, and the thinning-out signal is continuously generated for 3 clocks and stopped for the next 1 clock.

On the other hand, the pixel data in the image are sequentially input to the shift register 2 along the main scanning direction. In this example, a 5-bit shift register 2 is used. If a thinning signal is not input to the shift register 2, the input pixel data is input and output for all bits, and if a thinning signal is input, the immediately preceding pixel data is shifted and the input pixel data is the least significant bit. Input to and output.

The output of the shift register 2 is inverted by the inverting circuit 3, and then the reference value and the output of the inverting circuit 3 are compared by the comparator 4. In this example, the pixel data has 32 gradations (5 bits)
The intermediate value "15" was used as the reference value. If the input data is larger than the reference value, black, that is, "1" is output, and if it is less than the reference value, "0" is output.

The output of the comparator 4 is input to the register 5. At this time, when the thinning signal is not input, the input data is held and output as it is, and when the thinning signal is input, the immediately preceding data is held and output.

The output of the register 5 is thinned by the thinning circuit 6 at the timing of the thinning signal. In this case, the timing of the thinning signal is delayed by one clock.
This ends the reduction processing.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of an image reducing method and apparatus according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the arrangement of an image reducing apparatus according to the present invention. In the figure, the thinning-out signal generating circuit 1 generates a thinning-out signal at a predetermined timing corresponding to the input reduction rate. The thinning signal is supplied to the shift register 2, the register 5, and the thinning circuit 6.

Pixel data in the original image is sequentially input to the shift register 2 along the main scanning direction, and the shift operation is performed at the timing of the thinning signal. Here, the shift operation is performed only when the thinning signal is input.

The output of the shift register 2 is inverted in the upper bit and the lower bit by the inverting circuit 3 and supplied to the comparator 4. A reference value, that is, a threshold value is input to the comparator 4, and this reference value is compared with the output data of the inverting circuit 3. Here, the black and white of each pixel is judged and this is supplied to the register 5.

In the register 5, the input pixel data is held and output when the thinning signal is not input, and the immediately preceding pixel data is held and output when the thinning signal is input. The output of the register 5 is thinned and reduced by the thinning circuit 6 at the timing of the thinning signal.

FIG. 2 shows the timing of each signal and output data described above. In this example, the original image is reduced to 1/4, and the thinning-out signal is generated in a cycle of 3 clocks continuous and 1 clock stop.

Pixel data is sequentially input to the shift register 2 along the main scanning direction as described above. In this example, the shift register 2 has 5 bits, and the input pixel data is shifted at the timing of the thinning signal. That is, when the thinning signal is not input, the input data is all bits of the shift register. When a thinning signal is input, the immediately preceding data is shifted and the input data becomes the least significant bit.

In this way, the data output from the shift register 2 is inverted by the inverting circuit 3, that is, the least significant bit side and the most significant bit side are interchanged. For example, "11
“000” becomes “00011”. Here, since it has 5 bits, image processing can be performed with 32 gradations, and the output data of the inverting circuit 3 is shown in hexadecimal for convenience.

The output data of the inverting circuit 3 is compared with a reference value (threshold value) by the comparator 4. This is a black and white image 2 after reduction
This is performed for the purpose of expressing the value, and here, the value "0F", which represents the intermediate value "15" of 32 gradations in hexadecimal, was used as the reference value. When the input data is larger than the reference value, the comparator 4 outputs black, that is, "1", and otherwise outputs white, that is, "0".

In the register 5, the output data of the comparator 4 holds the input data when the thinning signal is not input and is output as it is. When the thinning signal is input, the immediately preceding data is held regardless of the input data. Is output. At this time, the timing of the thinning-out signal is one clock later than when it enters the shift register 2. As a result, in this example, "1" is continuously output for 4 clocks, and then "0" is continuously output for 4 clocks.

The output of the register 5 is thinned by the thinning circuit 6 at the timing of the thinning signal. At this time, the timing of the thinning signal is delayed by one clock from the time of entering the comparator 4. In this example, "1" and "0" for 4 clocks are subtracted for 3 clocks each and left for 1 clock. This ends the reduction processing.

As can be seen from the figure, according to the reduction method of the present invention, for example, when one pixel is black or "1" and two pixels are white or "0" among the three pixels thinned by the thinning signal. Indicates that white data is reflected to the image after being reduced to some extent. As a result, even when the halftone original image is reduced, the halftone can be reproduced almost faithfully and reduced.

[0030]

As described above, according to the present invention, the thinned pixel data is added to the remaining pixel data by a ratio corresponding to the reduction ratio. Therefore,
According to the present invention, even when a pseudo-halftone image is reduced, it is possible to perform reduction while maintaining the halftone.

Further, since the present invention does not require an arithmetic circuit, there is an effect that the structure of the image reducing device can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image reducing apparatus according to the present invention.

FIG. 2 is an explanatory diagram illustrating a signal timing of the image reducing apparatus according to the present invention.

FIG. 3 is an explanatory diagram illustrating reduction processing by a logical sum method.

FIG. 4 is an explanatory diagram illustrating reduction processing by an area projection method.

[Explanation of symbols]

 1 thinning signal generating circuit 2 shift register 3 inverting circuit 4 comparator 5 register 6 thinning circuit

Claims (2)

[Claims] 1. An image reducing method for reducing a binarized image in the main scanning direction by thinning out pixels in the image, the pixel data being multi-valued and thinned out. An image reduction method characterized in that the pixel data is added to the remaining pixel data by a ratio corresponding to a reduction ratio, and the remaining pixel data is binarized. 2. An image reducing apparatus for reducing a binarized image in the main scanning direction by thinning out pixels in the image, in which a thinning signal is generated at a timing corresponding to a reduction ratio. A signal generating means, a shift register for sequentially inputting pixel data in the main scanning direction within the image and shifting the pixel data at the timing of the thinning signal, and an inverting means for inverting the output data of the shift register. Comparing means for comparing the output data of the inverting means with reference data, a register for holding and outputting the output data of the comparing means or the immediately preceding output data at the timing of the thinning signal, and the output data of the register for An image reducing apparatus comprising thinning means for thinning at the timing of a thinning signal.