JP3454488B2 - Image processing circuit and image reduction method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit having a function of reducing an original image and an image reducing method thereof.

[0002]

2. Description of the Related Art In an information processing device having a conventional image reduction function, image data (dot data) is subjected to pixel thinning processing in dot units, and 2 dots are converted into 1 dot to output a reduced image. It is carried out. Part 2
2 dots OR when making 1 dot
May be taken or AND (and) may be taken.

[0003]

However, the above-mentioned conventional example has the following drawbacks.

1) When the OR of 2 dots of black and white is taken to form 1 dot, only 1 dot of black is left, and the output image has more black portions than the original image. As a result, the outline of the character may be lost.

2) AND the two dots of black and white to obtain 1
When dots are used, only one dot is white, and the output image has more white portions than the original image.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing circuit and an image reducing method therefor which can solve the above-mentioned problems and can perform a reducing process in which a reduced image is faithful to an original image.

[0007]

In order to achieve such an object, the invention of claim 1 is represented by bits "1" and "0", and adjacent compressions in the main scanning direction or the sub-scanning direction.
Two pixels of the small object, a determination circuit whether the same bit signals bit "1" or "0", the
If the judgment by the judgment circuit is affirmative, the reduction
The determination by the compression circuit that outputs the image signal obtained by compressing the two target pixels into one pixel, and the determination by the determination circuit are negative determinations.
The resolution of the two pixels to be reduced is doubled,
And a circuit for outputting the formed image signal for one pixel .

According to a second aspect of the present invention, a determination circuit and a compression circuit are provided.
And image output method of image processing circuit having output circuit
Is the modulo, represented by bits "1" and "0",
Two pixels to be reduced adjacent to each other in the scanning or sub-scanning direction
Is the same bit signal of bit "1" or "0"
Whether or not it is judged by the judgment circuit,
If the determination is positive, the two pixels to be reduced
The image signal compressed by 1 pixel is output by the compression circuit.
If the result of the judgment circuit is negative,
In this case, the resolution of the two pixels to be reduced is doubled and generated.
The image signal for one pixel is output by the output circuit.
It is characterized by

[0009]

According to the first and second aspects of the present invention, the image data whose signal level changes is not compressed and is left as it is in the form of high-resolution image data. As a result, in print output of a printer or the like, high-resolution image data, for example, two high-resolution data of black and white are output for each half dot.

[0011]

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

(First Embodiment) A first embodiment in which the present invention is applied to a printing apparatus will be described with reference to FIGS. 1 and 2.
FIG. 1 shows an example of the configuration of an image processing circuit for reduction.
In FIG. 1, 101 is a serial video signal for serially sending out dots of an image to be printed in the printing apparatus, and 102 is a shift clock used as a synchronous clock when the serial video signal 101 is sequentially sent out. Reference numeral 103 designates a D flip-flop (hereinafter abbreviated as FF) to which they are inputted, and 104 designates its output as an output A.

Reference numeral 105 is an FF and B, and an output A104 is input. A video clock 106 is a clock whose one cycle corresponds to one dot of the printing apparatus. The signal obtained by inverting the video clock 106 by the inverter 107 is F
It is used as a synchronous clock for F and B105. 108
Is the output of FF and B105. 109, 11
Reference numeral 0 denotes an OR (or) circuit and an EX-OR (exclusive OR) circuit, both of which have an output A104 and an output B1.
08 is input.

Reference numeral 111 is an FF and C, to which the output of the OR 109 is input, and reference numeral 112 is its output C. 113 is FF and D
The output of the EX-OR 110 is input at, and 114 is its output D. 115 is FF and E, the output B108 is input, and 116 is its output E.

FF, C111, FF, D113, FF,
The video clock 106 is used as the synchronization clock of E115. A selector A 117 receives the video clock 106 at the B input, the inverted video clock 118 at the B input, and the output E 116 at the S input. Selector A1
17 is A input when S input is "0", B when S input is "1"
The input is output to Y as the output F119. A selector B 120 has an output C 112 at the A input and an output F at the A input.
The output D114 is input to the 119 and S inputs. Similar to the selector A117, either A or B is set to 12 by S input.
1 is output to Y as a video output.

Next, the circuit operation will be described. FIG. 2 shows operation waveforms of each signal in FIG. In FIG. 2, 2
01 is a value of an adder (not shown in FIG. 1) when a predetermined value (0.25 in this embodiment) is sequentially added at each rising edge of the video clock 106. Reference numeral 202 denotes a carry signal which becomes "1" when the result of the sequential addition becomes 1 or more.

The serial video signal 101 of FIG. 1 is sequentially sent out in synchronization with the shift clock 102 from the first dot as the output A of FIG. In FIG. 2, the numbers in the frame represent the order of the serial video signals 101 that are sequentially sent. The output A104 is input to the FF and B105 and holds the data at the trailing edge of the video clock 106 in FIG.

As shown in the output B108 of FIG. 2, the output B108 is delayed by a half cycle of the video clock 106 with respect to the output A104. Attention is paid to the fourth and fifth serial video signals. Video clock 10
As a result of adding 0.25 for each one cycle of 6, as shown in FIG.
At 201, the value of the adder at 201 becomes 1.0. Then, the carry signal 202 becomes "1". Carry signal 202
Is "1", the shift clock 101 changes to a clock having a double frequency (see C1 in FIG. 2). When the carry signal 202 is "1", the video clock 10
A 2-dot serial video signal 101 is sent from the FFs and A 103 in 6 and 1 cycles. Reduction is performed by converting these two dots into one dot. Therefore, at the locations of C1, C2, C3, C4 and C5 in FIG.
The reduction processing to make dots is performed.

Since the synchronizing clock of FF and B105 is the falling edge of the video clock 106, the fourth data is held in FF and B105 before the output A104 changes from the fourth dot data to the fifth dot data in C1. To be done.

Therefore, the fifth data is not held in the FF and B105, and the sixth dot data is held at the next fall of the video clock 106. Consider a case where the fourth dot data is "0" and the fifth dot data is "1". It is assumed that “0” corresponds to a white dot and “1” corresponds to a black dot.

Outputs A104 of FF and A103 and outputs B108 of FF and A105 are input to the OR 109, respectively. Therefore, what is obtained by ORing the output A 104 and the output B is the rising edge of the video clock 106, and
It is held in F and C111. Since the carry signal 202 is "0" up to the 1st, 2nd and 3rd dot data, the output A104 and the output B108 are the same data when the video clock 106 rises, and the data is "0".
If so, the OR is also “0” and “0” is FF, C1.
Held at 1.

If the data is "1", "1" is FF, C.
It is held at 111. That is, when the carry signal 202 is "0", the dot data sent from the FF and A103 is output C1 with a delay of one cycle of the video clock 106.
Will appear in 12. When the carry signal 201 becomes “1” in C1, the fourth data (“0”, at the rising edge of the first shift clock 102 of C1).
White) is held in FF and A103, and is also held in FF and B at the next fall of the video clock 106.

However, at this time, since the shift clock 102 rises at the same timing as the video clock 106 falls, the fourth data is held in FF and B105 and at the same time the fifth data ("1" is stored in FF and A103). ", Black) is retained. Therefore, EX-OR110
"1" and "0" are input to the input terminal, and the output is "1". Then, at the next rise of the video clock 106, F
The output D114 of F, D113 changes from "0" to "1".

Since the output D114 is input to the selector B120, when the output D changes from "0" to "1", the output C112 was output as the video output 121 when the output D was "0". , The output F119 is output as the video output 121.

At this time, since the FF and E115 hold the fourth data ("0", white) at the rising edge of the video clock 106, the S input of the selector A117 is "0". Therefore, the inverted video clock 118 input to A appears at the output F119. Therefore, when the output D114 is "1", the inverted video clock 118 is output as the video output 121. As described above, when the process of making 2 dots into 1 dot is performed between the 4th (“0”, white) and the 5th (“1”, black), white and black are divided into half dots, that is, high resolution. Can be output with. For the 6th, 7th and 8th data, 1,
As with the second and third data, each dot is output.

Next, a case where the ninth data is "1", black, and the tenth data is "0", white will be described.
In C2 of FIG. 2, the 10th data (“0”, white) is held in the FF and A103, and the 9th data (“1”, black) is held in the FF and B105 similarly to the above-mentioned 4th and 5th. . Therefore, "1" and "0" are input to the EX-OR 110 and its output becomes "1". Then, at the next rise of the video clock 106, the output D114 of FF and D113
Changes from "0" to "1". When the output D114 becomes "1", the video output 121 becomes the output C.
The output F119 is switched from 112.

The output F119 at this time is 9 for FF and E.
Since the second data (“1”, black) is held, the B input video clock 106 of the selector A 117 appears. In this way, it is possible to output black and white half dots each when the process of making 2 dots into 1 dot is performed between the 9th ("1", black) and 10th ("0", white). Becomes

Next, the 14th data is "1", black, 15
A case where the second data is also “1” and black will be described (FIG. 2, C3). In this case, the 15th data (“1”, black) is held in the FFs and A103, and the 14th data (“1”, black) is held in the FFs and B105. Therefore, "1" and "1" are input to the EX-OR 110, and the output is "0". Therefore, FF, D113
Output D114 of the selector B12 remains "0".
0 remains in the A input selection state. O of the 14th data (“1”, black) and the 15th data (“1”, black)
The value obtained by R is held at the rising edge of the video clock 106 (the value is “1”) and output as the video output 121.

The 19th ("0", white) and 20th ("0", white) in FIGS. 2 and 4 will be described. Also in this case, the value of the EX-OR 110 is "0", and the output D114 of the FF and D113 is also "0".
Therefore, the OR of the 19th data (“0”, white) and the 20th data (“0”, white) is F
It is held in F and C111 at the rising edge of the video clock 106 (the value is "0"), and is output as the video output 121.

As described above, in this embodiment, the EX-OR 11 is used when reducing from 2 dots to 1 dot.
By providing 0, FF, 113 and selector B120, when the two dots are different, the OR of the two dots is performed.
It is possible to output the video output 12 by dividing the one dot into white and black by switching to the output F from the selector A 117 instead of the clock ("1") and white ("0"). It is possible to prevent the processing of becoming one black dot by OR and obtain a reduced image closer to the original image.

In this embodiment, the video clock 106 is used.
Although the inverted video clock 118 is output during the black and white reduction processing, any signal may be used as long as it is a signal in which black and white with a predetermined resolution or less appear alternately, for example, twice the video clock 106. You may use the clock of the frequency of.

(Second Embodiment) In the second embodiment, a case will be described in which when two dots are made into one dot, the AND of the two dots is output. The second embodiment is realized by changing the AND of OR109 in FIG. 1 (denoted as AND301). Carry signal 20 as in the first embodiment.
Assuming that 2 changes, in the second embodiment, in FIG. 2, only the output C112 is different from the first embodiment, and the other signals are the same as those in the first embodiment. In FIG. 2, 4
01 and output C are shown.

That is, in C1, the output C401 holds "0" by ANDing "0" and "1". At that time, the inverted video clock 118 is output as the video clock 121. Regarding C2, similarly, the output C401 becomes "0", but at that time, the video clock 106 is output as the video output 121. For white, the AND of “1” and “1” is output as it is (value is “1”), and for C4, the AND of “0” and “0” is output as it is (value is “0”).

As described above, in the second embodiment, when two dots are reduced when one dot is reduced to two dots, and when the two dots are different, the two dots are not ANDed, but one dot. Can be output as a video output 121 by dividing white into black and black, and the processing of black (“1”) and white (“0”) becoming one white dot can be prevented, and reduction closer to the original image can be achieved. Images can be obtained.

[0036]

As described above, according to the first and second aspects of the present invention, it is possible to obtain a reduced image closer to the original image when the reduction (compression) process is performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing operation timing.

[Explanation of symbols]

101 Serial video signal 102 shift clock 103 FF, A 104 Output A 105 FF, B 106 video clock 107 inverter 108 Output B 109 OR (circuit) 110 EX-OR (circuit) 111 FF, C 112 Output C 113 FF, D 114 output D 115 FF, E 116 Output E 117 Selector A 118 inverted video clock 119 Output F 120 Selector B 121 video output 201 Adder value 202 carry signal 301 AND (circuit) 401 Output C

Claims (2)

(57) [Claims] 1. A expressed in bits "1" and "0", the main
Two pixels to be reduced that are adjacent in the scan or sub-scan direction
Is the same bit signal of bit “1” or “0”, and if the judgment circuit makes an affirmative judgment,
If the determination by the compression circuit that outputs the image signal obtained by compressing the two pixels to be reduced to one pixel and the determination circuit is negative,
1 pixel generated by doubling the resolution of 2 pixels to be reduced
An image processing circuit including a circuit for outputting minute image signals . 2. A judgment circuit, a compression circuit, and a circuit for outputting.
An image processing method of an image processing circuit with bets, expressed in bits "1" and "0", the main scanning or sub-scanning read
Two pixels to be reduced that are adjacent in the scan direction
Check whether the same bit signal of "1" or "0"
If the judgment circuit makes a judgment and the judgment circuit makes an affirmative judgment,
The image signal obtained by compressing two pixels to be reduced into one pixel is described above.
When output by the compression circuit and the determination by the determination circuit is negative,
1 pixel generated by doubling the resolution of 2 pixels to be reduced
Minute image signal is output by the output circuit.
An image processing method of a characteristic image processing circuit.