JP4268696B2 - Image processing apparatus and processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus and a processing method for performing an interpolating process for maintaining an interlaced relationship of an original image when performing a line number conversion process using a field memory of a type in which an interlace signal is accessed in line units. .
[0002]
[Prior art]
Usually, transmission and processing of video signals are performed by an interlace method. In the interlace video signal, as is well known, one frame is composed of two fields, for example, an odd field and an even field, and an even field line scans between lines scanned in the odd field. In this case, a timing difference of 0.5H (horizontal frequency) is generated at the start position of scanning between the odd field and the even field, thereby maintaining the interlaced relationship.
[0003]
On the other hand, it is required to perform line number conversion on the video signal to enlarge or reduce the image. This line number conversion is performed by writing video signals in line units (1H units) to the field memory. Since writing is performed in line units, odd and even fields are written to the field memory in the same way. That is, the predetermined lines in the odd and even fields are written to the same address in the same memory, and the above-described shift of the scanning line start position by 0.5H is not reflected. For this reason, the interlace relationship described above cannot be maintained in this field memory space.
[0004]
Therefore, if the image enlargement process for increasing the number of lines in the in-field processing and reading the data as it is from the field memory is performed, there is a problem that the resolution after the process is deteriorated. This is because when the number of lines is converted, interpolation processing is performed by, for example, linear interpolation using two adjacent lines in the field, so that the line relationship between fields changes, and appropriate interpolation processing is performed. It is not done. Note that this is not particularly a problem when performing image reduction processing in which the number of lines in the field is reduced.
[0005]
For this reason, conventionally, when the line is read from the field memory, the timing of reading between the fields is shifted by an interlace equivalent time, that is, 0.5H, to cope with the problem of resolution degradation at the time of enlargement. It was. According to this method, there is an effect at the time of conversion in which the number of lines is an integral multiple, for example, enlargement of the image twice.
[0006]
FIG. 7 shows an example of a result of performing interpolation processing by linear interpolation by reading a line by a method of shifting the readout timing by 0.5H in order to convert the number of lines to double. Each pixel shown in FIG. 7 represents a representative point having the same horizontal position on each line. This representation is common in the following similar figures. “◯” represents a white level pixel, and “x” represents a black level pixel, and the pixels on the ODD field and the EVEN field line have an interlaced relationship. Further, “●” represents a dark gray of 50% or less, and a symbol with a hatched “◯” represents a light gray of 50% or more. Furthermore, the ODD line located at the top in the drawing is, for example, a pixel on the first line.
[0007]
The original signal written in the field memory as shown in FIG. 7A is handled in the same way in the ODD field and the EVEN field as shown in FIG. 7B and written into the field memory. When the number of lines is converted to double, interpolation processing is performed based on these pixels at the position indicated by the arrow in FIG. 7B, that is, at each half line position in each field. Then, timing control for 0.5H is performed at the time of reading, and a pixel as shown in FIG. 7C is obtained. A pixel interpolated between a white level pixel and a black level pixel is a gray pixel. As described above, in the conversion processing for doubling the number of lines, interpolation processing can be performed without any problem by this conventional method.
[0008]
In addition, in the conversion process for doubling the number of lines, for example, a method of continuously displaying one frame of video in which both the ODD field and the EVEN field are superimposed over two fields without performing the intra-field interpolation process. A method of doubling the number of lines by reading each field twice can be considered. However, in these methods, as shown in FIG. 8A, in the former method, images that are shifted in time are displayed on the same screen, so that the movement becomes unnatural. In the latter case, as shown in FIG. 8B, there is a problem that the resolution is lowered, which is not a good method.
[0009]
[Problems to be solved by the invention]
By the way, there is a case where a more free enlargement ratio is required for the enlargement of the image, and conversion in which the enlargement ratio does not become an integer value, for example, conversion such as enlargement of 4/3 times the image may be required. In such a case, there is a problem in that an optimal interlace relationship is not maintained, resolution is deteriorated, line flicker occurs, and the like, resulting in an unsightly image.
[0010]
FIG. 9 shows an example of the result of the interpolation process when the enlargement process of 4/3 is performed according to this conventional technique. The original pixel signal written in the field memory as shown in FIG. 9A is written into the field memory with the interlace relationship between the ODD field and the EVEN field lost as shown in FIG. 9B. When converting the number of lines to 4/3 times, interpolation is performed at the position indicated by the arrow in FIG. 9B, that is, every 1 / (4/3) line in each field, that is, every 3/4 line. Processing is done. Then, timing control for 0.5H is performed at the time of reading, and a pixel as shown in FIG. 9C is obtained. This is observed as flicker because the symmetrical shape in the original pixel signal is asymmetric.
[0011]
As described above, in the conventional method, since the interlaced relationship is not maintained when data is written to the field memory, the number of lines is, for example, 4/3 times, so that the enlargement ratio does not become an integer value. There is a problem that the image obtained by the above method is distorted with respect to the original signal image.
[0012]
Therefore, an object of the present invention is to perform interpolating with an interlace relationship of the original signal even when the enlargement ratio does not become an integer value when performing line number conversion using a field memory that accesses the interlaced signal in units of lines. An object of the present invention is to provide an image processing apparatus and a processing method capable of obtaining a processing result.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present invention provides a first field memory in which a video signal from a first line of an odd field or an even field of an interlaced video signal accessed in units of lines is stored;
A second field memory in which the video signal from the second line of the odd or even field of the interlaced video signal accessed in line units is stored;
From the first and second field memories by supplying the same read address to the first and second field memories, the two scanning lines adjacent to each other in the same field video signal A n and A n + 1 Address coefficient generating means for generating a vertical interpolation address and interpolation coefficients q n2 and q n1 to be read simultaneously;
The two video signals A n and A n + 1 read from the first and second field memories are respectively multiplied by the interpolation coefficients q n2 and q n1 and the two video signals multiplied by the interpolation coefficient Interpolating means for outputting a video signal obtained by adding
Address coefficient generation means
When Vdp = V1 / V2 (V1: number of effective lines of input video signal, V2: number of effective lines of output video signal), (odd field: 0.5) for each line of the odd field and even field. , 0.5 + Vdp, 0.5 + 2Vdp,..., Even field: 0, Vdp, 2Vdp,.
Of the output, the integer part is supplied to the first and second field memories as the vertical interpolation address,
The fractional part of the output is an image processing apparatus in which the vertical interpolation coefficient q n1 is supplied to the interpolation means and the vertical interpolation coefficient q n2 = 1−q n1 is supplied to the interpolation means .
[0014]
In order to solve the above-mentioned problem, the present invention stores the video signal from the first line of the odd field or even field of the interlaced video signal accessed in units of lines in the first field memory, Storing the video signal from the second line of the odd or even field of the interlaced video signal accessed in units of lines in a second field memory;
Vertical interpolation address and interpolation for simultaneously reading out video signals on two adjacent scanning lines in the same field from the first and second field memories by supplying the same readout address to the first and second field memories An address coefficient generation step for generating coefficients q n2 and q n1 ;
The two video signals A n and A n + 1 read from the first and second field memories are respectively multiplied by the interpolation coefficients q n2 and q n1 and the two video signals multiplied by the interpolation coefficient An interpolation step for outputting a video signal obtained by adding
The address coefficient generation step is
When Vdp = V1 / V2 (V1: number of effective lines of input video signal, V2: number of effective lines of output video signal), (odd field: 0.5) for each line of the odd field and even field. , 0.5 + Vdp, 0.5 + 2Vdp,..., Even field: 0, Vdp, 2Vdp,.
Of the output, the integer part is supplied to the first and second field memories as the vertical interpolation address,
The fractional part of the output is an image processing method in which the vertical interpolation coefficient q n1 is used in the interpolation step and the vertical interpolation coefficient q n2 = 1−q n1 is used in the interpolation step .
[0015]
As described above, according to the present invention, the interpolation processing at the time of converting the number of lines is performed based on the interpolation interval that is initialized and cumulatively added for each field with a value corresponding to the scanning start point of the odd and even fields. Therefore, the interlace accuracy is maintained in the interpolation processing result.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of the configuration of an image processing apparatus according to the present invention. In this example, an enlargement / reduction ratio is arbitrarily set for an input image signal, and linear interpolation is performed using two adjacent lines. Then, by appropriately selecting the interpolation position, the interlace relationship is maintained, and the image quality is improved.
[0017]
The divider 1 is supplied with the effective line number V _active in one field of the original signal and the converted effective line number V _size . These values are supplied from a system controller (not shown) based on, for example, user settings and system setting values. For example, if the image is enlarged and converted to 320, which is 4/3 times the number of effective lines in a 525 line / 50 Hz system, 240 lines, V _active = 240 (lines), V _size = 320 lines It is said. In the divider 1, the vertical interpolation interval Vdp is determined by V _active / V _size. This vertical interpolation interval Vdp is supplied to the vertical interpolation address / coefficient generator 2.
[0018]
Although not shown, based on the input image signal, a vertical blanking pulse V _blk indicating a vertical blanking period of the image signal, a line clock f _H generated every 1H, and the like are extracted by a predetermined means, This is supplied to the vertical interpolation address / coefficient generator 2.
[0019]
The vertical address / coefficient generator 2 generates an interpolation vertical address n and a vertical interpolation coefficient q _n1 based on the supplied vertical interpolation interval Vdp, vertical blanking pulse V _blk , and line clock f _H. In addition, q _n2 which is a complement of q _n1 to 1 is generated. Details of processing in the vertical address / coefficient generator 2 will be described later.
[0020]
As described above, in this embodiment, the image is enlarged / reduced by linear interpolation. As shown in FIG. 2, with respect to the pixels _An and A _{n + 1 at} the coordinates before enlargement, the position of the pixel x _{n at} the coordinates after enlargement is obtained. Then, based on the interior division ratio for the pixels A _n and A _{n + 1} position of the pixel x _n, data of the pixel x _n is obtained by the following equation (1). As the internal ratio, q _n1 and q _n2 which are the above-described vertical interpolation coefficients and their complements of 1 are used, respectively.
[0021]
x _n = q n2 · An + q n1 · An + 1 (1)
Line data At is sequentially supplied from the terminal 3 of FIG. 1 in accordance with, for example, scanning of an image signal. The line data At is composed of pixel data constituting the line, for example, a luminance signal Y, a color difference signal U / V, or an RGB signal. If necessary, it is filtered and supplied in a preceding stage (not shown).
[0022]
Line data A _t is accessed line by line is written in the field memory 4 and 5 are made. This writing is performed by shifting the line address by one line between the memories 4 and 5. FIG. 3 shows an example of address mapping in these memories 4 and 5 at this time. In this figure, there are addresses for N-1 lines in the vertical direction with respect to the number N of effective lines in one field. Here, the number N of effective lines in one field is, for example, 240 in a 525/60 Hz system and 288 in a 625/50 Hz system according to the video signal standard.
[0023]
In this example, line data from the first line to the (N-1) th line is written in the field memory 5 shown in FIG. 3A, and the field memory 4 shown in FIG. The line data up to the line is written. That is, for the same line address n, the line _An is written in the field memory 5 and the line _An-1 is written in the field memory 4.
[0024]
Reading of the line data from the field memories 4 and 5 is performed from the same address based on the vertical interpolation address n output from the vertical interpolation address / coefficient generator 3 described above. The line data read from the field memory 4 is supplied to one input terminal of the multiplier 6a in the product-sum calculator 6 including the multipliers 6a and 6b and the adder 6c. Similarly, the line data read from the field memory 5 is supplied to one input terminal of the multiplier 6b.
[0025]
The interpolation coefficient q _n1 is supplied to the other input terminal of the multiplier 6a, and the interpolation coefficient q _n2 is supplied to the other input terminal of the multiplier 6b. These multipliers 6a and 6b respectively multiply the interpolation coefficients and the above-described line data, and supply the multiplication results to one and the other input terminals of the adder 6c. The addition result of the adder 6 c is the calculation result of the product-sum calculator 6. In this way, the product-sum calculator 6 performs the calculation of the above formula (1) to obtain line data x _n .
[0026]
Next, the vertical interpolation address / coefficient generator 2 having the above-described configuration will be described. In this embodiment, the generator 2 makes an appropriate selection of the interpolation position of the line. FIG. 4 shows an example of the configuration of the vertical interpolation address / coefficient generator 2. The vertical interpolation interval Vdp is supplied to the terminal 10. Further, the line clock f _H and the vertical blanking pulse V _blk are supplied to the terminals 11 and 12, respectively. The line clock f _H is an operation clock for registers 13 and 15 described later. The vertical blanking pulse V _blk is supplied to the registers 13 and 15 and a selector 16 described later.
[0027]
The vertical interpolation interval Vdp supplied to the terminal 10 is stored in the register 13. The vertical interpolation interval Vdp is supplied to the register 15 via the adder 14. The vertical interpolation interval Vdp is delayed by one clock f _H in this register 15 and supplied to the other input terminal of the adder 14 via the selector 16. That is, the vertical interpolation interval Vdp is cumulatively added by the adder 14.
[0028]
On the other hand, an odd / even signal for discriminating odd / even fields of the input video signal is supplied to the selector 17. This signal is, for example, 'H' level when the input video signal is an odd field, and 'L' level when the input video signal is an even field. The selector 17 is supplied with a first value corresponding to the start point of the even field scan and a second value corresponding to the start point of the odd field scan. These first and second values correspond to, for example, 1H representing one horizontal period, and the first value is [0.5] and the second value is [0]. Based on the odd / even signal, the first value is selected when the input video signal is an odd field, and the second value is selected and output when the input video signal is an even field. This output is supplied to the selector 16.
[0029]
In the selector 16, the output of the selector 17 is selected as an input during the vertical blanking period. As a result, the initial value in the register 15 is set to the first or second value corresponding to the odd / even signal, and the vertical interpolation interval Vdp is initialized for each vertical blanking period. That is, the first or second value selected by the selector 17 based on the odd / even signal is set as an offset value for the vertical interpolation interval Vdp, and initialization is performed. Therefore, for example, when the first value is [0.5] and the second value is [0] as described above, the output of the register 15 in the effective line section is in each of the odd field and the even field. For each line:
[0030]
Odd field: 0.5, 0.5 + V dp, 0.5 + 2 V dp,..., 0.5+ (N−1) V dp
Even field: 0, V dp, 2 V dp,..., (N−1) V dp ”
Of the output of the register 15 obtained in this way, the integer part is derived to the terminal 18 as the vertical interpolation address n. On the other hand, the decimal part of the output of the register 15 is derived to the terminal 19 as the vertical interpolation coefficient qn1. The decimal part, that is, the vertical interpolation coefficient qn1 is subtracted from 1 in the subtracter 20 to be a coefficient qn2, which is derived to the terminal 21.
[0031]
Thus, in the present invention, a predetermined offset is added to each of the odd field and the even field with respect to the vertical interpolation interval Vdp. Thereby, the start position of the interpolation process is shifted by the added offset. The interpolation processing according to the present invention will be conceptually described with reference to FIGS.
[0032]
FIG. 5 shows an example in which the number of lines of the interlace signal is converted to twice per field and the image is enlarged twice. In this case, the interpolation interval is ½ of the line interval in one field. Of the pixels shown in FIG. 5A, the pixels in the ODD field are written into the field memories 4 and 5, respectively. In this example, since [0.5] is selected as the offset value in the selector 17 in the ODD field, the first interpolation position is shifted by 0.5H as shown on the left side of FIG. 5B. On the other hand, since [0] is selected as the offset value in the EVEN field, the first line is set as the interpolation start position as shown on the right side of FIG. 5B.
[0033]
FIG. 5C shows an example of the interpolation result in this case. In both the ODD field and the EVEN field, the pixel generated at the first interpolation position is the first line. In the ODD field, the first line is interpolated between “x” and “x”, the next line is output as “x”, and the next line is interpolated by half of “x” and “o”. Further, since the next line is generated as an output of “◯” as it is,..., An interpolation result as shown on the left side of FIG. 5C is obtained. Similarly, in EVEN, the first line is output as “x” as it is, the next line is interpolated by half of “x” and “o”, and so on, and is shown on the right side of FIG. 5C. Such an interpolation result is obtained.
[0034]
Therefore, in a one-frame image composed of the ODD field and the EVEN field, an image substantially equivalent to the original image shown in FIG. 5A is obtained.
[0035]
Next, FIG. 6 shows an example of using the present invention when the enlargement ratio is not an integer value, for example, when the original image is enlarged 4/3 times. In this case, the interpolation interval is 3/4 of the line interval in one field. Also in this example, as shown in FIG. 6B, the ODD field is shifted by 0.5H from the EVEN field as the interpolation start position.
[0036]
In the ODD field, the first line is interpolated between “×” and “×”, the next line is interpolated with the ratio of “×” and “◯” being 3/4: 1/4, and the next line is “ The line that has been interpolated with the ratio of “×” to “O” being 3/4: 1/4 is assumed to be a gray close to black, on the left side of FIG. 6C. An interpolation result as shown is obtained. On the other hand, in the EVEN field, the output of the first line is “X” as it is, the next line is an interpolation of the ratio of “×” and “O” to 1/4: 3/4, and the next line is “O”. ”And“ ◯ ”are interpolated, and an interpolation result as shown on the right side of FIG. 6C is obtained.
[0037]
Therefore, in the one-frame image composed of the ODD field and the EVEN field, as shown in FIG. 6C, an image as shown in the original image of FIG. 6A is obtained, and in the above-described conventional example, as shown in FIG. 9C. There is no distortion of the shape. As described above, by using the present invention, it is possible to maintain the accuracy of the interlace even in the line number conversion when the enlargement ratio does not become an integer value.
[0038]
In the above-described embodiment, it has been described that the present invention is applied to the case where linear interpolation with upper and lower two lines is performed, but this is not limited to this example. For example, the present invention can be applied to a case where linear interpolation is performed using a larger number of lines.
[0039]
【The invention's effect】
As described above, according to the present invention, when the number of lines is converted using a field memory having a format in which a signal having interlace accuracy is accessed in units of lines, the interpolation start position of the odd field is set. Since an offset of 0.5H is added to the even field, there is an effect that an optimum interlace relationship can be obtained even when the conversion ratio does not become an integer value.
[0040]
Therefore, by using the present invention, it is possible to suppress degradation of image resolution and occurrence of line flicker even when the number of lines is converted so that the conversion ratio does not become an integer value in image enlargement. It is said.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of the configuration of an image processing apparatus according to the present invention.
FIG. 2 is a schematic diagram for explaining linear interpolation;
FIG. 3 is a schematic diagram illustrating an example of field memory mapping;
FIG. 4 is a block diagram showing an example of the configuration of a vertical interpolation address / coefficient generator.
FIG. 5 is a schematic diagram for explaining conversion of twice the number of lines according to the present invention;
FIG. 6 is a schematic diagram for explaining a conversion of 4/3 times the number of lines according to the present invention.
FIG. 7 is a schematic diagram for explaining a conversion of twice the number of lines according to the prior art.
FIG. 8 is a schematic diagram for explaining frame superposition and twice-in-field reading.
FIG. 9 is a schematic diagram for explaining a conversion of 4/3 times the number of lines according to the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Divider, 2 ... Interpolation address / coefficient generator, 4, 5 ... Field memory, 6 ... Product-sum operation unit, 13, 15 ... Register, 14 ... Adder 16, 17 ... selector, 20 ... subtractor

Claims (4)

A first field memory in which video signals from a first line of odd or even fields of an interlaced video signal accessed in units of lines are stored;
A second field memory in which the video signal from the second line of the odd or even field of the interlaced video signal accessed in line units is stored;
Video signals of the first and the second field memories by supplying the same read address to the first and second field memories, two scanning lines adjacent to each other in the same field A n and A n + Address coefficient generating means for generating a vertical interpolation address for simultaneously reading 1 and interpolation coefficients q n2 and q n1 ;
With multiplying interpolation coefficients q n2 and q n1 for each of the two video signals A n and A n + 1 read out from the first and second field memories, two video interpolation coefficient is multiplied by Interpolating means for outputting a video signal obtained by adding the signals ,
The address coefficient generating means is
When Vdp = V1 / V2 (V1: number of effective lines of input video signal, V2: number of effective lines of output video signal), (odd field: 0.5) for each line of the odd field and even field. , 0.5 + Vdp, 0.5 + 2Vdp,..., Even field: 0, Vdp, 2Vdp,.
Of the output, the integer part is supplied to the first and second field memories as the vertical interpolation address,
Among the outputs, the decimal part is supplied to the interpolation means as the vertical interpolation coefficient q n1 and the vertical interpolation coefficient q n2 = 1−q n1 is supplied to the interpolation means . The image processing apparatus according to claim 1 .
An image processing apparatus in which V1 <V2 . The video signal from the first line of the odd or even field of the interlaced video signal accessed in line units is stored in a first field memory, and the odd field of the interlaced video signal accessed in line units or Storing the video signal from the second line of the even field in a second field memory;
A vertical interpolation address for supplying the same read address to the first and second field memories and simultaneously reading video signals on two scanning lines adjacent to each other in the same field from the first and second field memories. And an address coefficient generation step for generating interpolation coefficients q n2 and q n1 ,
With multiplying interpolation coefficients q n2 and q n1 for each of the two video signals A n and A n + 1 read out from the first and second field memories, two video interpolation coefficient is multiplied by An interpolation step for outputting a video signal obtained by adding the signals ,
The address coefficient generation step is
When Vdp = V1 / V2 (V1: number of effective lines of input video signal, V2: number of effective lines of output video signal), (odd field: 0.5) for each line of the odd field and even field. , 0.5 + Vdp, 0.5 + 2Vdp,..., Even field: 0, Vdp, 2Vdp,.
Of the output, the integer part is supplied to the first and second field memories as a vertical interpolation address,
The image processing method in which the decimal part of the output is used as the vertical interpolation coefficient q n1 in the interpolation step and the vertical interpolation coefficient q n2 = 1−q n1 is used in the interpolation step . The image processing method according to claim 3 .
An image processing method in which V1 <V2 .

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