JPH10240208A - Device and method for processing image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep precision in an original signal when line conversion whose expansion rate is not an integer value is performed by a video signal with interlace precision. SOLUTION: An interpolation interval Vdp obtained from an original image and an image size after conversion is stored in a register 13, and is acumulatively added by an adder 14 through a selector 16 from the register 15. By the selector 17, a [0.5] is selected in an ODD field, and a [0] is selected in an EVEN field based on an odd/even field discrimination signal to be supplied to the selector 16. The output of the selector 17 is selected by the selector 16 for a vertical blanking period, and the register 15 is initialized. Then, an offset value [0.5] is added to the cumulated value of the Vdp in the ODD field, and the Vdp is cumulatively added again. A read-out address (n), linear interpolation coefficients qn1 , qn2 of a line are obtained based on this cumulative addition value. Since the offsets corresponding to the start points of the scanning of the ODD field and EVEN field are added when the Vdp is cumulatively added, the interlace precision is kept.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs an interpolation process to maintain the interlace relationship of an original image when performing a line number conversion process using a field memory of a type in which an interlace signal is accessed line by line. The present invention relates to an image processing device and a processing method.

[0002]

2. Description of the Related Art Usually, transmission and processing of a video signal are performed by an interlace method. In the interlaced video signal, as is well known, one frame is composed of two fields, for example, an odd field and an even field, and the lines of the even field scan between the lines scanned in the odd field. In this case, a timing difference of 0.5H (horizontal frequency) occurs at the scan start position between the odd field and the even field, thereby maintaining the interlace relationship.

On the other hand, it is required that the video signal be subjected to line number conversion to enlarge or reduce an image. This line number conversion is performed by writing a video signal to the field memory in line units (1H units). Since writing is performed line by line, odd and even fields are written in the field memory in the same manner. That is, the predetermined lines of the odd and even fields are written at the same address of the same memory, and the above-described shift of the scanning line start position by 0.5H is not reflected. Therefore, the above-described interlace relationship cannot be maintained in the field memory space.

Therefore, if the process of enlarging an image or increasing the number of lines in the in-field processing is performed by directly reading the data from the field memory, the resolution after the processing is degraded. This is because when performing line number conversion, interpolation processing is performed using, for example, linear interpolation using two adjacent lines in a field, so that the relationship of lines between fields changes, and appropriate interpolation processing is performed. This is because it is not done. This is not particularly a problem when reducing the number of lines in a field or reducing an image.

Therefore, conventionally, when reading lines from the field memory, the timing of reading between fields is shifted by the interlace equivalent time, that is, 0.5H, to solve the problem of resolution degradation at the time of this enlargement. Was dealing. According to this method, there is an effect at the time of conversion such that the number of lines is an integral multiple, for example, when the image is enlarged twice.

FIG. 7 shows an example of a result obtained by reading a line by shifting the read timing by 0.5H and performing an interpolation process by linear interpolation in order to double the number of lines. Each pixel shown in FIG. 7 represents a representative point having the same horizontal position on each line. This expression is common in the following similar figures. “○” indicates a pixel at a white level, and “×” indicates a pixel at a black level.
The pixels on the N field lines maintain an interlaced relationship. “●” indicates dark gray of 50% or less, and “○” indicates a shaded shade of 50% or more of light gray. Further, the ODD line located at the top in the drawing is, for example, a pixel on the first line.

FIG. 7A, which is written in the field memory
The original signal as shown in FIG.
The ODD field and the EVEN field are handled in the same manner and written into the field memory. When the number of lines is doubled, the position indicated by the arrow in FIG. 7B based on these pixels, that is, 1 in each field,
Interpolation processing is performed at the position of every / 2 line. Then, timing control for 0.5H is performed at the time of reading, and a pixel as shown in FIG. 7C is obtained. Pixels interpolated between white level pixels and black level pixels are gray pixels. As described above, in the conversion processing for doubling the number of lines, the interpolation processing can be performed without any problem by the conventional method.

In the conversion process for doubling the number of lines, for example, an ODD field and an EVEN field are superimposed on both fields, and one frame image is continuously displayed over two fields without performing intra-field interpolation. Or a method of doubling the number of lines by reading each field twice. However, in these methods, in the former, FIG.
As shown in A, an image whose time is shifted is displayed on the same screen, so that the movement becomes unnatural. Also,
The latter has a problem that the resolution is reduced as shown in FIG. 8B, and is not a good method.

[0009]

By the way, a more flexible enlargement ratio is required in the enlargement of an image, and a conversion such that the enlargement ratio does not become an integer value, for example, a conversion such as 4/3 times enlargement of the image is required. In some cases. In such a case, there is a problem that an image is unsightly, because resolution is degraded and line flicker is generated without maintaining an optimal interlace relationship.

FIG. 9 shows an example of the result of the interpolation processing when the enlargement processing of 4/3 is performed by the conventional technique. The original pixel signal written in the field memory as shown in FIG. 9A is, as shown in FIG.
The interlace relationship between the D field and the EVEN field is lost, and the data is written to the field memory. When the number of lines is converted to 4/3 times, interpolation is performed at the position indicated by the arrow in FIG. 9B, that is, every 1 / (4/3) line in each field, ie, every 3/4 line. Processing is performed. Then, at the time of reading, timing control for 0.5H is performed, and pixels as shown in FIG. 9C are obtained. This is observed as flicker because the symmetric shape in the original pixel signal is made asymmetric.

As described above, in the conventional method, since the interlacing relationship is not maintained when data is written to the field memory, the enlargement ratio such that the number of lines is, for example, 4/3 times does not become an integer value. There is a problem that an image obtained by a simple conversion process is distorted with respect to an image of an original signal.

Accordingly, an object of the present invention is to provide a method of converting the number of lines using a field memory which accesses an interlace signal line by line, even if the enlargement ratio does not become an integer value. An object of the present invention is to provide an image processing apparatus and a processing method that can obtain a result of the interpolation processing.

[0013]

According to the present invention, there is provided an image processing apparatus for interpolating an interlaced video signal, comprising: a memory for writing the video signal; A reading unit for simultaneously reading signals on two adjacent scanning lines in a field from the memory unit; and an interpolation unit for performing an interpolation process on the two read signals. An image processing apparatus is characterized in that a read start address of a memory means is changed between a case where a field signal is read and a case where an even field signal is read.

According to another aspect of the present invention, there is provided an image processing method for interpolating an interlaced video signal, wherein the video signal is stored in a memory, and an odd field of the odd field is stored in the memory. The read start address is changed between the case where a signal is read and the case where a signal of an even field is read, and signals on two adjacent scanning lines in the field are simultaneously read, and interpolation processing is performed on the two read signals. And an image processing method characterized by performing the following.

As described above, the present invention is based on an interpolation interval initialized and accumulated for each field with a value corresponding to the start point of scanning of odd and even fields.
Since the interpolation processing at the time of the line number conversion is performed, the accuracy of the interlace is maintained in the interpolation processing result.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of an image processing apparatus according to the present invention. In this example, an enlargement / reduction ratio is arbitrarily set for an input image signal, and linear interpolation is performed using two adjacent lines. Then, by appropriately selecting the position of the interpolation, the interlace relationship is maintained, and the image quality is improved.

For the divider 1, the number of _active lines V _active within one field of the original signal and the number of _active lines V after conversion
_size is supplied. These values are supplied from a system controller (not shown) based on, for example, user settings and system setting values. For example, 525
Assuming that the number of active lines is 240 in a 50/50 Hz system,
In the case of enlarging an image and converting the number of lines into 320 lines of 4/3 times, V _active = 240 (lines) and V _size = 320
It is a book. In the divider 1, the vertical interpolation interval Vdp is obtained by V _active / V _size . This vertical interpolation interval Vdp is supplied to the vertical interpolation address / coefficient generator 2.

Although not shown, based on the input image signal, a vertical blanking pulse V _blk indicating a vertical blanking period of the image signal, a line clock f _H generated every 1H, and the like are provided by predetermined means. It is extracted and supplied to the vertical interpolation address / coefficient generator 2.

In the vertical address / coefficient generator 2, the supplied vertical interpolation interval Vdp, vertical blanking pulse V
_blk, and based on the line clock f _H, and interpolation vertical address n and a vertical interpolating coefficient q _n1 is generated. Further, q _n2 which is the complement of q _n1 to 1 is generated. Details of the processing in the vertical address / coefficient generator 2 will be described later.

As described above, in this embodiment, the image is enlarged / reduced by linear interpolation. As shown in FIG. 2, with respect to pixels A _n and A _{n + 1} in the before enlargement coordinates, the position of the pixel x _n is obtained at the enlarged coordinates. Then, based on the internal division ratio of the position of the pixel x _n to the pixels _An and _{An + 1} , data of the pixel x _n is obtained by the following equation (1). As the internal division ratio, q _n1 and q _n2 which are complements to the above-described vertical interpolation coefficient and its 1 are used, respectively.

[0021] are sequentially supplied in accordance with the scanning of the _{x n = q n2 · A n} + q n1 · A n1 ··· (1) line data A _t is for example an image signal from the terminal 3 of FIG. The line data A _t is,
Each pixel data forming the line is composed of, for example, a luminance signal Y, a color difference signal U / V, or an RGB signal.
If necessary, the data is filtered and supplied in a preceding stage (not shown).

The line data A _t is accessed line by line is written in the field memory 4 and 5 are made. This writing is performed by shifting the line addresses of the memories 4 and 5 by one line. FIG.
An example of address mapping in these memories 4 and 5 at this time will be described. In this figure, N-1 lines of addresses are provided in the vertical direction with respect to the number N of effective lines in one field. Here, the number N of effective lines in one field is, for example, 52 in accordance with the standard of the video signal.
240/625 in a 5/60 Hz system
In a system of 50/50 Hz, the number is 288.

In this example, line data from the first line to the (N-1) th line is written in the field memory 5 shown in FIG. 3A, and the second line data is written in the field memory 4 shown in FIG. 3B. To the Nth line are written. That is, for the same line address n, the line A
_n is written in the field memory 4 and the line A _n-1 is written.

The reading of line data from these field memories 4 and 5 is performed by using the above-described vertical interpolation address /
Based on the vertical interpolation address n output from the coefficient generator 3, they are made from the same address. The line data read from the field memory 4 is supplied to the multipliers 6a, 6
b, and the product-sum operation unit 6 including the adder 6c,
The signal is supplied to one input terminal of the multiplier 6a. Similarly, the line data read from the field memory 5 is supplied to one input terminal of the multiplier 6b.

The other input terminal of the multiplier 6a has an interpolation coefficient q
_n1 is supplied, and an interpolation coefficient _qn2 is supplied to the other input terminal of the multiplier 6b. Then, these multipliers 6a and 6
At b, the multiplication of these interpolation coefficients and the above-described line data is performed, and the multiplication result is supplied to one and the other input terminals of the adder 6c. The addition result of the adder 6c is used as the operation result of the product-sum operation unit 6. In this way, the operation of the above equation (1) is performed in the product-sum operation unit 6,
Line data _xn is obtained.

Next, the vertical interpolation address / coefficient generator 2 having the above configuration will be described. In this embodiment, the generator 2 makes an appropriate choice of the interpolation position of the line. FIG. 4 shows the vertical interpolation address /
An example of the configuration of the coefficient generator 2 is shown. Vertical interpolation interval Vdp
Is supplied to the terminal 10. Further, the line clock f _H and the vertical blanking pulse V _blk are _supplied to the terminals 11 and 1 respectively.
2 respectively. The line clock f _H is an operation clock of the registers 13 and 15 described later.
The vertical blanking pulse V _blk is _supplied to the register 1
3, 15 and a selector 16 described later.

The vertical interpolation interval Vdp supplied to the terminal 10
Is stored in the register 13. Vertical interpolation interval Vdp
Is supplied to the register 15 via the adder 14. The vertical interpolation interval Vdp is calculated by this register 15 for one clock f.
_{The signal is} delayed by _H and supplied to the other input terminal of the adder 14 via the selector 16. That is, the vertical interpolation interval Vdp
Are cumulatively added in the adder 14.

On the other hand, an odd / even field for discriminating odd / even fields of the input video signal is supplied to the selector 17.
An even signal is provided. This signal is set to the “H” level when the input video signal is in the odd field, and is set to the “L” level when the input video signal is in the even field. Further, the selector 17 is supplied with a first value corresponding to the start point of the scan of the even field and a second value corresponding to the start point of the scan of the odd field. These first and second values are, for example, 1H representing one horizontal period.
And the first value is [0.5] and the second value is

[0]
It is said. Then, based on the odd / even signal, when the input video signal is an odd field, the first value is:
In the case of an even field, the second value is selected and output. This output is supplied to the selector 16.

In the selector 16, the output of the selector 17 is selected as an input during the vertical blanking period. As a result, the initial value in the register 15 becomes odd / ev
The value is set to the first or second value corresponding to the en signal, and the vertical interpolation interval Vdp is initialized every vertical blanking period. That is, in the selector 17, odd / even
The first or second value selected based on the n signal is set as an offset value with respect to the vertical interpolation interval Vdp, and initialization is performed. Therefore, for example, as described above, the first value is [0.5] and the second value is

When [0] is set, the output of the register 15 in the effective line section is as follows for each line in each of the odd field and the even field.

Odd field: 0.5, 0.5 + dp,
0.5 + 2dp,..., 0.5+ (N−1) dp Even field: 0, dp, 2dp,.
1) dp The integer part of the output of the register 15 thus obtained is derived to the terminal 18 as the vertical interpolation address n. On the other hand, the decimal part of the output of the register 15 is derived to the terminal 19 as a vertical interpolation coefficient q _n1 . Further, the decimal part, that is, the vertical interpolation coefficient q _n1 is subtracted from ₁ in the subtracter 20 to obtain a coefficient q _n2 , which is derived to the terminal 21.

As described above, in the present invention, a predetermined offset is added to each of the odd field and the even field with respect to the vertical interpolation interval Vdp. As a result, the start position of the interpolation processing is shifted by the added offset. The interpolation processing according to the present invention will be conceptually described with reference to FIGS.

FIG. 5 shows an example in which the number of lines of the interlace signal is doubled per field and the image is doubled. In this case, the interpolation interval is set to の of the line interval in one field. Of the pixels shown in FIG. 5A, the pixels in the ODD field are written into the field memories 4 and 5, respectively. In this example, OD
In the D field, since the selector 17 selects [0.5] as the offset value, the first interpolation position is shifted by 0.5H as shown on the left side of FIG. 5B. In contrast, in the EVEN field, the offset value

Since [0] is selected, the first line is set as the interpolation start position as shown on the right side of FIG. 5B.

FIG. 5C shows an example of the interpolation result in this case. Both the ODD field and the EVEN field
The pixel generated at the first interpolation position is the first line. In the ODD field, the first line is interpolated between "x" and "x", the next line is output as "x",
The next line is interpolated by 1/2 of "x" and "o", and the next line is output with "o" as it is ...
Thus, an interpolation result as shown on the left side of FIG. 5C is obtained. Similarly, in EVEN, the first line is output as it is as “x”, the next line is interpolated by half of “x” and “１ ／”,.
An interpolation result as shown on the right side of FIG. 5C is obtained.

Therefore, in the one-frame image composed of the ODD field and the EVEN field, an image substantially equivalent to the original image shown in FIG. 5A can be obtained.

Next, FIG. 6 shows an example in which the present invention is used to enlarge the original image to 4/3 times when the enlargement ratio is not an integer value. In this case, the interpolation interval is set to ／ of the line interval in one field. Also in this example, as shown in FIG. 6B, the ODD field is shifted from the EVEN field by 0.5H at the start position of the interpolation.

In the ODD field, the first line is interpolated between "x" and "x", and the next line is "x" and "o".
Is 3/4: 1/4 interpolation, and the next line is output with "o" as it is, ..., "x" and "o"
The line on which the interpolation with the ratio of 3/4: 1/4 was performed is
The color becomes gray close to black, and an interpolation result as shown on the left side of FIG. 6C is obtained. On the other hand, in the EVEN field, the output of the first line is “x” as it is, the next line is interpolation of a ratio of “x” to “○” of ４: 3/4,
Further, the next line is interpolated between “○” and “○”,..., And an interpolation result as shown on the right side of FIG. 6C is obtained.

Therefore, in the one-frame image composed of the ODD field and the EVEN field, as shown in FIG. 6C, an image substantially similar to the original image of FIG. 6A is obtained. There is no distortion of the shape that can be caused. As described above, by using the present invention, it is possible to maintain the accuracy of the interlace even in the conversion of the number of lines when the enlargement ratio is not an integer value.

In the above-described embodiment, it has been described that the present invention is applied to the case where the linear interpolation is performed by two upper and lower lines. However, the present invention is not limited to this example. For example, the present invention can be applied to a case where linear interpolation is performed using a larger number of lines.

[0039]

As described above, according to the present invention, when converting the number of lines using a field memory of a type in which a signal having interlaced accuracy is accessed in units of lines, an odd number Since the interpolation start position of the field has an offset of 0.5H with respect to the even field, even when the conversion ratio does not become an integer value, there is an effect that an optimum interlace relationship can be obtained.

Therefore, by using the present invention, even when the number of lines is converted so that the conversion ratio does not become an integer value in image enlargement, deterioration of the image resolution and generation of line flicker are suppressed. It is made possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of an image processing device according to the present invention.

FIG. 2 is a schematic diagram for explaining linear interpolation.

FIG. 3 is a schematic diagram illustrating an example of mapping of a field memory.

FIG. 4 is a block diagram showing an example of a configuration of a vertical interpolation address / coefficient generator.

FIG. 5 is a schematic diagram for explaining conversion of twice the number of lines according to the present invention;

FIG. 6 is a schematic diagram for explaining conversion of 4/3 times the number of lines according to the present invention.

FIG. 7 is a schematic diagram for explaining conversion of twice the number of lines according to the related art.

FIG. 8 is a schematic diagram for explaining frame superposition and twice-in-field reading.

FIG. 9 is a schematic diagram for explaining conversion of 4/3 times the number of lines according to the related art.

[Explanation of symbols]

1 ... divider, 2 ... interpolation address / coefficient generator,
4, 5: Field memory, 6: Product-sum operation unit,
13, 15 ... register, 14 ... adder, 16,
17 ... selector, 20 ... subtractor

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 7/01 H04N 7/01 G (72) Inventor Nobuo Ueki 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Stock In company

Claims (13)

[Claims] 1. An image processing apparatus for performing an interpolation process on an interlaced video signal, comprising: a memory unit in which the video signal is written;
Reading means for simultaneously reading signals on the scanning lines; and interpolating means for performing the interpolation processing on the two read signals. An image processing apparatus wherein the read start address of the memory means is changed between when a field signal is read. 2. An image processing apparatus according to claim 1, wherein said memory means is divided into a first memory and a second memory, and the same address of said first and second memories. Wherein signals of scanning lines adjacent to each other in the field are stored, and the read means supplies the same read address to the first and second memories. 3. The image processing apparatus according to claim 2, wherein the signal output from said interpolation means is a signal obtained by enlarging a signal stored in said memory means. apparatus. 4. An image processing apparatus according to claim 3, wherein said reading means generates an initial value which is different between a case where a signal of an odd field is read and a case where a signal of an even field is read. An image processing apparatus comprising: cumulative addition means for cumulatively adding the reciprocal of the enlargement ratio to the generated initial value. 5. The image processing apparatus according to claim 4, wherein said reading means further supplies an integer part of said accumulative adding means to said first and second memories as a reading address. Image processing device. 6. The image processing apparatus according to claim 5, wherein said interpolating means multiplies each of said two read signals by an interpolation coefficient, and said two signals multiplied by said interpolation coefficient. An image processing apparatus characterized by outputting a signal obtained by adding a signal. 7. An image processing apparatus according to claim 6, wherein said reading means further supplies a decimal part of said cumulative addition means to said interpolation means as said interpolation coefficient. . 8. An image processing method for performing an interpolation process on an interlaced video signal, wherein the video signal is stored in a memory, and a signal of an odd field is read from the memory, and a signal of an even field is read from the memory. The read start address is changed depending on the case, and two adjacent addresses in the field are changed.
An image processing method, wherein signals on two scanning lines are simultaneously read out, and the above-described interpolation processing is performed on the two read out signals. 9. The image processing method according to claim 8, wherein the memory is divided into a first memory and a second memory, and the first memory and the second memory have the same address. Respectively, stores signals of scanning lines adjacent to each other in the field. By supplying the same read address to the first and second memories, signals on two scanning lines adjacent to each other in the field are simultaneously read. An image processing method characterized by reading. 10. The image processing method according to claim 9, wherein said interpolated signal is a signal obtained by enlarging a signal stored in said memory. 11. The image processing method according to claim 10, wherein the read address has a different initial value between a case of reading a signal of an odd field and a case of reading a signal of an even field. A reciprocal of the enlargement ratio is cumulatively added to the initial value, and an integer part of the cumulative addition result is used. 12. The image processing method according to claim 11, wherein the interpolation process includes multiplying each of the two signals read out by an interpolation coefficient, and the two signals multiplied by the interpolation coefficient. An image processing method characterized by performing by adding signals. 13. The image processing method according to claim 12, wherein the interpolation coefficient uses a decimal part of the cumulative addition result.