JP2004165828A - Processing apparatus for graphics data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processing apparatus for graphics data capable of preventing the generation of flickers in compositing an image obtained by applying scaling processing to a non-interlaced graphics image with an interlaced moving image. <P>SOLUTION: The processing apparatus for graphics data is provided with a depiction storage means on which the graphics data are depicted, a scaling means for applying scaling processing to the graphics data read from the depiction storage means in a non-interlaced state, a frame memory for storing the graphics data obtained from the scaling means, and a reading control means for reading even line data or odd line data from the frame memory synchronously with whether the moving data to which the graphics data are composited are odd fields or even fields. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an apparatus for processing graphics data such as OSD data.
[0002]
[Prior art]
The present applicant has already developed an image data output device for combining moving image data and graphics data (OSD data) by scaling processing as disclosed in Japanese Patent Application Laid-Open No. 2002-199277. .
[0003]
FIG. 1 shows the configuration of the image data output device developed by the present applicant.
[0004]
The graphics data is stored in the drawing memory 111. The graphics data read from the drawing memory 111 is multiplied by a weight coefficient a by a weight coefficient multiplying circuit 112. Then, the graphics data multiplied by the weighting coefficient a is subjected to scaling processing by the scaling circuit 113 in accordance with the resolution of the display. The graphics data on which the scaling processing has been performed is sent to the synthesis circuit 131.
[0005]
The moving image data is subjected to scaling processing in the scaling circuit 121 according to the resolution of the display. The moving image data on which the scaling processing has been performed by the scaling circuit 121 is sent to the weight coefficient multiplication circuit 122.
[0006]
In the weight coefficient multiplying circuit 122, the moving image data corresponding to the pixel position where the image obtained from the graphics data is displayed is multiplied by the weight coefficient (1-fa). f is a value corresponding to the resolution of the display, and changes according to the enlargement ratio of the scaling processing performed by the scaling circuit 121.
[0007]
Note that moving image data corresponding to a pixel position where an image obtained from the scaled graphics data does not display an image is output as it is without being multiplied by a weighting factor. The moving image data output from the weight coefficient multiplication circuit 122 is sent to the synthesis circuit 131.
[0008]
The moving image data from the weight coefficient multiplying circuit 122 and the graphics data from the scaling circuit 113 are synchronized with the synthesizing circuit 131 so that the moving image data and the graphics data at the same pixel position are given to the synthesizing circuit 131. Is output. Therefore, at the pixel position where the image obtained from the graphics data is not displayed, only the moving image data is output as the image data, and at the pixel position where the image obtained from the graphics data is displayed, the added data of the graphics data and the moving image data is Output as image data.
[0009]
By the way, usually, moving image data is input in interlace, but there is no concept of interlace in graphics data. Japanese Patent Application Laid-Open No. 2002-199277 does not describe a method of combining interlaced moving image data and graphics data without the concept of interlace.
[0010]
Japanese Patent Application Laid-Open No. 11-143441 also discloses a technique in which moving image data and graphics data are individually subjected to scaling processing and then combined.
[0011]
FIG. 2 shows the configuration of the image display control device disclosed in Japanese Patent Application Laid-Open No. 11-143441.
[0012]
The moving image data is sent to the scaling circuit 151, and the scaling processing is performed for each field. The moving image data on which scaling processing has been performed by the scaling circuit 151 is sent to the synthesis circuit 161.
[0013]
The graphics data is stored in the drawing memory 141. Then, the graphics data is read from the drawing memory 141 every line skipping in accordance with the moving image data, and is sent to the scaling circuit 142. That is, the graphics data of the odd field and the graphics data of the even field are read from the graphics data for one frame stored in the drawing memory 141. The graphics data that has been subjected to the scaling processing by the scaling circuit 142 is sent to the combining circuit 161 and combined with the moving image data.
[0014]
By the way, the scaling circuit 142 in the image display control device of FIG. 2 performs scaling only in the horizontal direction and does not perform scaling in the vertical direction. Assuming that vertical scaling has been performed in the scaling circuit 142, the following problem occurs.
[0015]
In general, it is assumed that the scaling target image is an image having one horizontal line on a white background as shown in FIG. In the scaling process, in the case of reduction, aliasing noise occurs, and therefore, a low-pass filter process is usually performed. As a result, one horizontal line in the scaling target image shown in FIG. 3A becomes, for example, three gray horizontal lines after the scaling process, as shown in FIG. 3B.
[0016]
Assume that graphics data as shown in FIG. 3A is stored in the drawing memory 141 of the image display control device in FIG. In the image display control device of FIG. 2, among the graphics data stored in the drawing memory 141, first, only the odd lines are read and sent to the scaling circuit 142, where the scaling processing is performed. That is, of the graphics data stored in the drawing memory 141, only a portion corresponding to an odd field is read out and scaling processing is performed.
[0017]
Next, only the even-numbered lines of the graphics data stored in the drawing memory 141 are read out and sent to the scaling circuit 142 to perform scaling processing. That is, of the graphics data stored in the drawing memory 141, only the portion corresponding to the even field is read out and the scaling process is performed.
[0018]
When such scaling processing is performed, three gray lines are displayed in one field including the horizontal line in FIG. 3A, and a pure white image is displayed in the other field not including the horizontal line in FIG. Is displayed, there is a problem that flicker occurs.
[0019]
[Patent Document 1] JP-A-2002-199277 [Patent Document 2] JP-A-11-143441
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a graphics data processing apparatus that does not cause flicker when an image obtained by scaling a graphics image that is a non-interlaced image is combined with a moving image that is an interlaced image. .
[0021]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a graphics data processing apparatus which is used in a case where data obtained by scaling data of graphics data which is non-interlace data is combined with video data which is interlace data and displayed. Storage means for drawing graphics data, scaling means for scaling graphics data read from the drawing storage means in a non-interlaced state, frame memory for storing graphics data obtained from the scaling means And read control means for reading out the odd line data or the even line data from the frame memory in synchronization with whether the moving image data to be combined with the graphics data is an odd field or an even field. To.
[0022]
According to a second aspect of the present invention, there is provided a graphics data processing apparatus which is used in a case where data obtained by performing scaling processing on graphics data which is non-interlace data is combined with video data which is interlace data and displayed. A first field memory, a second field memory, a drawing storage unit on which graphics data is drawn, a scaling unit for scaling graphics data read from the drawing storage unit in a non-interlaced state, a scaling unit Write control means for alternately writing the graphics data obtained from the first field memory and the second field memory line by line, and whether the moving image data to be combined with the graphics data is an odd field Even number In synchronization with either a field, characterized in that it comprises a read control means for reading interlaced graphics data from any of the field memory.
[0023]
According to a third aspect of the present invention, there is provided a graphics data processing apparatus which is used in a case where data obtained by performing scaling processing on graphics data which is non-interlace data is combined with video data which is interlace data and displayed. A first field memory, a second field memory, a drawing storage unit on which graphics data is drawn, a scaling unit for scaling graphics data read from the drawing storage unit in a non-interlaced state, a scaling unit And a means for reading only odd-numbered line data from the frame memory and storing the same in the first field memory, and reading only even-numbered line data from the frame memory and storing in the second field Means for storing the graphics data in the memory, and reading control means for reading out interlaced graphics data from any of the field memories in synchronization with whether the moving image data to be combined with the graphics data is an odd field or an even field. It is characterized by having.
[0024]
According to a fourth aspect of the present invention, there is provided a graphics data processing apparatus which is used in a case where graphics data which is non-interlaced data is combined with video data which is interlaced data and displayed after being synthesized. A memory, a drawing storage unit on which the graphics data is drawn, a scaling unit for scaling the graphics data read from the drawing storage unit in a non-interlaced state, and moving image data to be synthesized with the graphics data. A control means for storing only one of the odd line data and the even line data in the graphics data obtained from the scaling means in the field memory in synchronization with whether the field is an odd field or an even field; And wherein the door.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, with reference to FIGS. 4 to 9, the present invention combines a video data (moving image data) of a broadcast program and graphics data such as an EPG in a digital broadcast receiver after performing scaling processing, and synthesizes them. An embodiment will be described in which the present invention is applied to a case in which a combined image is displayed on a display.
[0026]
[1] Description of First Embodiment FIG. 4 shows the configuration of an image data output device according to the first embodiment.
[0027]
Graphics data that is non-interlace data is stored in the drawing memory 11. The graphics data stored in the drawing memory 11 is read from the drawing memory 11 without being interlaced. The graphics data read from the drawing memory 11 is multiplied by a weight coefficient a by a weight coefficient multiplying circuit 12.
[0028]
The graphics data multiplied by the weighting factor a is subjected to horizontal and vertical scaling processes by the scaling circuit 13 in accordance with the resolution of the display. In this case, the scaling processing is performed in a state where the graphics data is not interlaced. The graphics data on which the scaling process has been performed is temporarily stored in the frame memory 14.
[0029]
On the other hand, moving image data that is interlaced data is subjected to horizontal and vertical scaling processes in the scaling circuit 21 in accordance with the resolution of the display. The moving image data on which the scaling processing has been performed by the scaling circuit 21 is sent to the weight coefficient multiplication circuit 22.
[0030]
In the weight coefficient multiplying circuit 22, the moving image data corresponding to the pixel position where the image obtained from the graphics data is displayed is multiplied by the weight coefficient (1-fa). f is a value corresponding to the resolution of the display, and changes according to the enlargement ratio of the scaling process performed by the scaling circuit 21.
[0031]
Note that moving image data corresponding to a pixel position where an image obtained from the scaled graphics data does not display an image is output as it is without being multiplied by a weighting factor. The moving image data output from the weight coefficient multiplying circuit 22 is sent to the synthesizing circuit 31.
[0032]
From the graphics data stored in the frame memory 14, data of only odd lines or only even lines is read depending on whether the moving image data output from the weight coefficient multiplying circuit 22 is an odd field or an even field. It is sent to the synthesis circuit 31.
[0033]
The timing control circuit 15 controls the timing of reading the interlaced graphics data from the frame memory 14 so that the moving image data and the graphics data at the same pixel position are given to the synthesizing circuit 31 in synchronization. Therefore, at a pixel position where an image obtained from interlaced graphics data is not displayed, only moving image data is output as image data, and at a pixel position where an image obtained from interlaced graphics data is displayed, graphics data is output. And the moving image data are output as image data.
[0034]
The principle of scaling in the vertical direction in the scaling circuit 13 (also in the scaling circuit 21) will be described with reference to FIG.
[0035]
FIG. 5 shows the principle of scaling when the magnification is 4/5. When the magnification is 4/5, the input line interval is divided into four equal parts, and an output line is generated every 5/4 line. Values Yn of each output line, the value of the upper input line of the output lines n and X _i, the value of the input line of the lower side of the output line n and X _{i + 1,} the distance between adjacent two input lines When the distance from the upper input line to the output line n when b is normalized to 1 is represented by b, the distance is represented by the following equation (1).
[0036]
_{Yn = b * X i + (} 1-b) * X i + 1 ... (1)
[0037]
In the case where the output line is in the same line as the input line, X _i and X _{i + 1} both the value of the input lines of the same line with the output line.
[0038]
FIG. 6 shows a configuration of a circuit for performing scaling in the vertical direction in the scaling circuit 13 (similarly for the scaling circuit 21).
[0039]
The circuit for performing vertical scaling includes a line memory 41, multipliers 42 and 43, and an adder 44.
[0040]
The number of input lines of the signal input to the multiplier 42 via the line memory 41 is N, the value and X _N. The number of the input line of the signal input to the multiplier 43 is N + 1. The value of the signal input to the multiplier 43 is _{XN + 1} . The multiplier 42 multiplies the input signal (X _N ) by a coefficient b. The multiplier 43 multiplies the input signal (X _{N + 1} ) by a coefficient (1-b). The adder 44 adds the outputs of both the multipliers 42 and 43, the output line number and outputs the signal value Y _M in M.
[0041]
Assuming that the scaling ratio is 1024 / k and the line numbers are 0, 1, 2,..., N and M have a relationship of N = M * k / 1024 (decimal points are rounded down). The coefficient b is b = (modulo 1024 of M * k) / 1024. The modulo 1024 of M * k is the remainder when M * k is divided by 1024. However, when M * k = 0, the modulo 1024 of M * k is 1024.
[0042]
For example, when the scaling ratio is 4/5, k = 1280. When M = 1, N = 1. Also, b = (modulo 1024 of 1 * 1280) / 1024 = 256/1024 = 1/4. Note that the scaling circuit is not limited to the above-described circuit. However, if the above-described scaling circuit is used, data on the scaled line can be obtained from only the two related lines, so that the circuit can be simplified.
[0043]
[2] Description of Second Embodiment
FIG. 7 shows a configuration of an image data output device according to the second embodiment. 7, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.
[0045]
In the image data output device of FIG. 7, two field memories 16a and 16b are used instead of the frame memory 14 in the image data output device of FIG. The graphics data subjected to the scaling processing by the scaling circuit 13 is alternately written to the field memories 16a and 16b line by line. Therefore, for example, the odd-numbered line data of the scaled graphics data is written to one field memory 16a, and the scaled graphics data of the scaled graphics data is written to the other field memory 16a. Even line data is written. As a result, the interlaced graphics data is stored in each of the field memories 16a and 16b.
[0046]
If the moving image data output from the weight coefficient multiplying circuit 22 is an odd field, the corresponding graphics data is read from one of the field memories, and the moving image data output from the weight coefficient multiplying circuit 22 is replaced with the even field. In the case of, the corresponding graphics data is read from the other field memory.
[0047]
The timing control circuit 15 controls the read timing of the interlaced graphics data from each of the field memories 16a and 16b so that the moving image data and the graphics data at the same pixel position are given to the synthesizing circuit 31 in synchronization. I do. Therefore, at a pixel position where an image obtained from interlaced graphics data is not displayed, only moving image data is output as image data, and at a pixel position where an image obtained from interlaced graphics data is displayed, graphics data is output. And the moving image data are output as image data.
[0048]
[3] Description of Third Embodiment
FIG. 8 shows a configuration of an image data output device according to the third embodiment. 8, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.
[0050]
In the image data output device of FIG. 8, two field memories 17a and 17b are provided at the subsequent stage of the frame memory 14 in the image data output device of FIG. The graphics data subjected to the scaling processing by the scaling circuit 13 is stored in the frame memory 14. Only the data of the odd lines of the graphics data stored in the frame memory 14 is read out and written into one field memory 17a, and then the data of the even lines of the graphics data stored in the frame memory 14 is read out. Only data is read and written to the other field memory 17b. As a result, the interlaced graphics data is stored in each of the field memories 17a and 17b.
[0051]
If the moving image data output from the weight coefficient multiplying circuit 22 is an odd field, the corresponding graphics data is read from one field memory 17a, and the moving image data output from the weight coefficient multiplying circuit 22 is an even number. If it is a field, the corresponding graphics data is read from the other field memory 17b.
[0052]
The timing control circuit 15 controls the read timing of the interlaced graphics data from each of the field memories 17a and 17b so that the moving image data and the graphics data at the same pixel position are given to the synthesizing circuit 31 in synchronization. I do. Therefore, at the pixel position where the image obtained from the interlaced graphics data is not displayed, only the moving image data is output as the image data, and at the pixel position where the image obtained from the interlaced graphics data is displayed, the graphics data is output. And the moving image data are output as image data.
[0053]
[4] Description of Fourth Embodiment
FIG. 9 shows a configuration of an image data output device according to the fourth embodiment. In FIG. 9, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.
[0055]
In the image data output device of FIG. 9, the scaling circuit 13 repeatedly performs scaling processing and repeatedly outputs the scaled graphics data even when the graphics data does not change. The timing control circuit 18 outputs the data of the odd-numbered lines or the data of the even-numbered lines of the non-interlaced graphics data output from the scaling circuit 13 in accordance with the type of the field of the moving image data output from the weight coefficient multiplication circuit 22 Is written in the field memory 19 and the other is discarded.
[0056]
That is, when the moving image data output from the weight coefficient multiplying circuit 22 is the data of the odd field, the timing control circuit 18 determines the data of the odd line among the non-interlaced graphics data output from the scaling circuit 13. Only is written in the field memory 19. When the moving image data output from the weight coefficient multiplying circuit 22 is data of an even field, the timing control circuit 18 converts only the data of the even line out of the non-interlaced graphics data output from the scaling circuit 13. Write to the field memory 19.
[0057]
The interlaced graphics data written in the field memory 19 is sent to the synthesizing circuit 31 and synthesized with the moving image data output from the weight coefficient multiplying circuit 22.
[0058]
In the fourth embodiment, the number of memories can be reduced as compared with the first to third embodiments. On the other hand, the first to third embodiments require only one scaling operation, and thus have the advantage of lower power consumption than the fourth embodiment.
[0059]
【The invention's effect】
According to the present invention, flicker does not occur when an image obtained by scaling a graphics image that is a non-interlaced image is combined with a moving image that is an interlaced image.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a conventional image data output device.
FIG. 2 is a block diagram illustrating a configuration of a conventional image display control device.
FIG. 3 is a schematic diagram for explaining vertical scaling processing.
FIG. 4 is a block diagram illustrating a configuration of an image data output device according to the first embodiment.
FIG. 5 is an explanatory diagram for explaining a vertical scaling principle in a scaling circuit.
FIG. 6 is a block diagram showing a configuration of a circuit for performing vertical scaling in a scaling circuit.
FIG. 7 is a block diagram illustrating a configuration of an image data output device according to a second embodiment.
FIG. 8 is a block diagram illustrating a configuration of an image data output device according to a third embodiment.
FIG. 9 is a block diagram illustrating a configuration of an image data output device according to a fourth embodiment.
[Explanation of symbols]
11 Drawing Memory 12, 21 Weight Coefficient Multiplying Circuit 13, 21 Scaling Circuit 14 Frame Memory 15, 18 Timing Control Circuit 16a, 6b, 17a, 17b, 19 Field Memory 31 Synthesizing Circuit

Claims (4)

In a graphics data processing apparatus used when combining and displaying scaling data on graphics data that is non-interlace data with video data that is interlace data,
Drawing storage means for drawing graphics data,
Scaling means for scaling the graphics data read from the drawing storage means in a non-interlaced state;
A frame memory for storing graphics data obtained from the scaling means, and an odd line data or an even line from the frame memory in synchronization with whether the moving image data to be combined with the graphics data is an odd field or an even field. Read control means for reading data,
A graphics data processing device comprising: In a graphics data processing apparatus used when combining and displaying scaling data on graphics data that is non-interlace data with video data that is interlace data,
A first field memory,
A second field memory,
Drawing storage means for drawing graphics data,
Scaling means for scaling the graphics data read from the drawing storage means in a non-interlaced state;
Writing control means for alternately writing the graphics data obtained from the scaling means into the first field memory and the second field memory for each line, and moving picture data to be synthesized with the graphics data in an odd field Reading control means for reading out interlaced graphics data from any of the field memories in synchronization with whether the field is an even field or
A graphics data processing device comprising: In a graphics data processing apparatus used when combining and displaying scaling data on graphics data that is non-interlace data with video data that is interlace data,
A first field memory,
A second field memory,
Drawing storage means for drawing graphics data,
Scaling means for scaling the graphics data read from the drawing storage means in a non-interlaced state;
A frame memory for storing graphics data obtained from the scaling means, and a means for reading out only odd-numbered line data from the frame memory and storing the data in the first field memory;
Means for reading out even line data only from the frame memory and storing it in the second field memory; and any one of the fields in synchronization with whether the moving image data to be combined with graphics data is an odd field or an even field. Read control means for reading interlaced graphics data from the memory,
A graphics data processing device comprising: In a graphics data processing apparatus used when combining and displaying scaling data on graphics data that is non-interlace data with video data that is interlace data,
Field memory,
Drawing storage means for drawing graphics data,
Scaling means for scaling the graphics data read from the drawing storage means in a non-interlaced state, and synchronizing whether the moving image data to be combined with the graphics data is an odd field or an even field. Control means for storing only one of the odd line data and the even line data in the graphics data obtained from the scaling means in the field memory,
A graphics data processing device comprising:

Images