JPH09116108A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an easy-to-handle, anti-fuse type storage device with a long service life which can be used digitally and analogically by providing to the end part of the anti-fuse type storage device a pair of reading contact areas which are connected to an internal circuit. SOLUTION: An n-type area 103 and a p-type area 104 are formed on the main surface of a semiconductor substrate 100 with an insulator area 101 in between, thereby forming a diode 120. An n<+> type area 102 is formed in contact with the end part of the area 103 and a p<+> type area 105 is formed in contact with the end part of the area 104. Then a contact area 106 is formed on the main surface of the area 102 and a first aluminum wiring 110 is connected therewith. A contact area 109 is formed on the main surface of the area 105 and a second aluminum wiring 111 is connected therewith. Further, a third aluminum wiring 113 is connected with the major surface of the area 102, and a fourth aluminum wiring 114 is connected with the major surface of the area 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called antifuse type semiconductor memory device which has a high resistance value in an initial state and stores information by reducing the resistance value.

[0002]

2. Description of the Related Art As a so-called antifuse type semiconductor memory device, there is, for example, the one shown in FIG. 8 disclosed in Japanese Patent Laid-Open No. 57-3292. Hereinafter, FIG.
The structure and operation of the conventional example of the antifuse type semiconductor memory device will be described below. The antifuse memory device is composed of a diode 9 composed of an n-type region 4 and a p-type region 5 formed on the main surface of a semiconductor substrate 1 with an insulating film 2 interposed therebetween. The cathode of the diode 9 is connected to the n + type region 3, and the anode of the diode 9 is connected to the p + type region 6. The n + type region 3 is the contact region 7
The first terminal 10 is connected to an internal circuit (not shown) via the contact, and the p + region 6 is connected to the second terminal 11 to the internal circuit via the contact region 8. In this antifuse memory device, the reverse characteristic of the diode 9 is in a high resistance state in the initial state. That is,
It is turned off. Then to the diode 9, the terminal 1
From 0 and 11, a reverse bias voltage larger than the breakdown voltage of the diode 9 is applied. If this reverse bias voltage is large enough, the diode 9 is thermally destroyed. Therefore, the reverse characteristic of the diode 9 is in a low resistance state. That is,
It turns on. This means that the information is stored in this antifuse type storage device. That is, information is obtained by causing the internal circuit to detect a change in the reverse characteristic of the diode 9 of the antifuse memory device, that is, a difference between so-called off resistance (off-state resistance) and on-resistance (on-state resistance). Remember.

However, the conventional antifuse type memory device as described above has the following problems. First,
If the pn junction of the diode 9 is simply destroyed by heat, only the portion of the pn junction where a local defect occurs is destroyed. Therefore, the on-resistance does not become sufficiently small. In this case, although it can be used digitally, it is not suitable for analog use such as high precision trimming. Then
The following phenomenon occurs when a reverse bias voltage having sufficiently high voltage and energy is applied to the diode 9 to break the pn junction until it melts. Even if the application time of the reverse bias voltage applied to the diode 9 is set to 1 ms, the diffusion length of heat is about 200 μm due to the thermal conductivity of silicon. Therefore, if the distance between the pn junction of the diode 9 and the contact region 7 or 8 is normal (about 1 μm to several tens of μm), the heat generated at the pn junction reaches the contact regions 7 and 8. As a result, when the temperature of the contact regions 7 and 8 rises to about 450 ° C., a eutectic reaction occurs between the aluminum wiring and silicon, and as shown in FIG. It is formed so as to groin the pn junction. This aluminum elution region 13
On the other hand, the on-state resistance becomes sufficiently small, and it becomes possible to use not only digitally but also analogically, but on the other hand, new problems described below occur. That is, when the aluminum elution region 13 is formed, voids or defects may occur or silicon may be deposited at the interface between the contact 7 and the n + type region 3 and at the interface between the contact 8 and the p + type region 6. . Therefore, even if the on-resistance immediately after writing is small, the on-resistance may increase due to deterioration over time due to thermal stress in a normal use environment. That is, the reliability is not high. Furthermore, if the occurrence of voids or defects or the precipitation of silicon is significant, the on-resistance may not be sufficiently reduced even immediately after the diode 9 is destroyed.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned various problems of the conventional antifuse type memory device and can be used digitally or analogically, and is easy to use and reliable. It is an object of the present invention to provide an antifuse type storage device which is expensive and has a long life.

[0005]

In order to solve the above-mentioned problems, in the present invention, the resistance value is high in the initial state on the main surface of the semiconductor substrate or on the main surface of the semiconductor substrate through the insulator region. A so-called antifuse type memory device for storing information by reducing the value is formed, and a first wiring to which a first wiring is connected is formed on an end main surface on one end side of the antifuse type memory device. A contact region is formed, and a second contact region to which the second wiring is connected is formed on the end main surface on the other end side of the antifuse type memory device, and the antifuse type memory device is also provided. A third contact region, to which the third wiring is connected, is formed inside the first contact region on the end main surface on one end side of
Further, the fourth contact region to which the fourth wiring is connected is formed inside the second contact region on the end main surface on the other end side of the antifuse memory device. Connecting the first and second contact regions to an internal circuit,
The third and fourth contact regions are connected to the write electrode, or the first and second contact regions are connected to the internal circuit and the write electrode, and the third and fourth electrodes are electrically opened. .

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described with reference to FIG. FIG. 1A is a diagram showing a cross-sectional structure of the first embodiment, and FIG. 1B is a diagram showing a planar structure of the first embodiment. On the main surface of the semiconductor substrate 100,
The diode 120 is formed by forming the n-type region 103 and the p-type region 104 via the insulator region 101. The n + region 102 is formed in contact with the end of the n type region 103, and the p + type region 105 is formed in contact with the end of the p type region 104.
To form Then, a contact region 106 is formed on the main surface of the n + type region 102 to form a first aluminum wiring 110.
Connect. On the other hand, the contact region 109 is formed on the main surface of the p + type region 105 to form the second aluminum wiring 111.
Connect. Further, a contact region 107 is formed on the main surface of the n + -type region 102 at a position closer to the pn junction of the diode 120 than the contact region 106, and the third aluminum wiring 113 is connected. Further, the contact region 10 is provided on the main surface of the p + -type region 105 at a position closer to the pn junction of the diode 120 than the contact region 109.
8 is formed and the fourth aluminum wiring 114 is connected. The first aluminum wiring 110 is connected to a first write electrode (not shown), and the second aluminum wiring 111 is connected to a second write electrode (not shown). Further, the first aluminum wiring 110 and the second aluminum wiring 111 are both connected to an internal circuit (not shown).

Next, the operation of this embodiment will be described with reference to FIG. In the initial state, the off resistance is high due to the reverse characteristic of the diode 120. Then, the diode 1 is applied to the first write electrode with reference to the second write electrode.
When writing is performed by applying a positive voltage equal to or higher than the breakdown voltage of 20, the diode 120 breaks down and generates heat. Here, even if the application time of the positive voltage is 1 ms, the heat diffusion length is about 200 μm due to the thermal conductivity of silicon. The contact regions 107 and 108 are close to the diode 120 (1 μm
Since it is formed in the order of several to several tens of μm), the diode 1
The heat generated by 20 causes the temperature of contacts 107 and 108 to rise quickly and fully. Eventually contact 1
When the temperature of 07 and 108 exceeds about 450 ° C., a eutectic reaction between aluminum and silicon occurs, and an aluminum elution region 150 is formed at the pn junction portion of the diode 120. Thus, in this first embodiment, the first
In addition, the on-resistance is sufficiently small due to the elution region 150 of aluminum.

Second, contact regions 107 and 108
Is not related to the reading of information. Therefore, even if voids, defects, or deposition of silicon occurs at the interface between the contact region 107 and the n + -type region 102 and at the interface between the contact region 108 and the p + -type region 105, the on-resistance does not increase. Moreover, it does not change due to deterioration over time.

Thirdly, because of the effect described in the second aspect, the contact regions 107 and 108 can be formed in the vicinity of the pn junction, so that the elution region 150 of aluminum spreads inside the pn junction. Therefore, the on-resistance is further reduced. Fourth, the heat generated by the diode 120 is
After being absorbed by the aluminum wiring 113 or 114 through the contact region 107 or 108, the heat is radiated to the surroundings. Therefore, the temperature rise in the contact regions 106 and 109 can be suppressed. Therefore, the contact region 10
No voids or defects are generated in the portions 6 and 109. Therefore, there is no increase in on-resistance or deterioration with time.

Next, a second embodiment of the present invention will be described with reference to FIG.
It will be explained by. FIG. 3 is a diagram showing a planar structure of the second embodiment, in which the fifth aluminum wiring 200 is connected to the contact region 107 (similar to the case of the first embodiment) and the (first embodiment). Similar to the case of
A sixth aluminum wiring 201 is formed in the contact region 108.
Connect. Then, the fifth aluminum wiring 200 is connected to the first write electrode (not shown), and the sixth aluminum wiring 201 is connected to the second write electrode (not shown). Further, each of the first aluminum wiring 110 and the second aluminum wiring 111 is connected only to the internal circuit. Other configurations are the same as those in the first embodiment.

Next, the operation of the second embodiment will be described.
The off resistance is high as in the case of the first embodiment. The write operation is also similar to that in the first embodiment. The second embodiment has the following effects in addition to the four effects described in the first embodiment.

The first effect will be described with reference to FIG. The resistor 202 is a resistor from the first write electrode to the pn junction of the diode 120. The resistor 203 is a resistor from the second write electrode to the pn junction of the diode 120. In the second embodiment, since the write voltage is applied to the aluminum wirings 200 and 201 near the pn junction, the values of the resistors 202 and 203 are smaller than those in the first embodiment. Therefore, the energy consumed by the resistors 202 and 203, that is, the diode 1
Energy consumed at locations other than 20 is reduced.
Therefore, the voltage and current required for writing are reduced, and writing can be performed more easily.

As a second effect, it is generally known that an aluminum elution region is likely to occur in the current flow path, and is more likely to occur when a current is flowing. In this embodiment, since current flows through both contact regions 107 and 108, an aluminum elution region is more effectively generated at the pn junction of diode 120.
Therefore, the ON resistance is further reduced in the second embodiment.

Next, a third embodiment of the present invention will be described with reference to FIG.
It will be explained by. FIG. 5 is a diagram showing a planar structure. At the end of the p-type region 104 in the case of the second embodiment, a p + -type region 301 is provided as shown. p + type region 301
Of the contact region 108 on one main surface on the p-type region 104 side of
The aluminum wiring 201 is connected via. On the other hand,
The width of the other end of the p + type region 301 is increased. Then, the aluminum wiring 111 is connected to this portion through a contact region 303 composed of a plurality of contacts. Further, an n + type region 300 is provided at the end of the n type region 103. The aluminum wiring 2 is formed on the main surface at one end of the n + -type region 300 on the n-type region 103 side via the contact region 107.
00 is connected. On the other hand, the width of the other end of the n + type region 300 is increased. The aluminum wiring 110 is connected to this portion via a contact region 302 composed of a plurality of contacts, which is the difference from the second embodiment. Other configurations are similar to those of the second embodiment.

Next, the operation of the third embodiment will be described. In this embodiment, the same operation as in the case of the second embodiment is performed, but in addition to the effects described in the case of the second embodiment, there are the following effects. That is, the contact region 302 is composed of a plurality of contacts, and the n + -type region 300 of the contact region 302 portion is formed.
Since the width of the wiring is large, the resistance from the aluminum wiring 110 to the diode 120 becomes small. Similarly, the resistance from the aluminum wiring 111 to the diode 120 also decreases. That is, the ON resistance at the time of reading can be further reduced without impairing the ease of writing. Furthermore, the contact regions 107 and 10 during writing
Since the current density of No. 8 remains high, the formation of the aluminum elution region is not impaired. Furthermore, the area of the wiring on the contact regions 302 and 303 is set to the contact region 1
If the area of the wiring on 07 and 108 is made larger, the temperature rise of the contact areas 302 and 303 can be suppressed even if the contact areas 107 and 108 become sufficiently hot. For example, if the former area is 10 times the latter area, the former temperature rise is 1/10 of the latter temperature rise. Therefore,
Even when the temperature of the latter part reaches 450 ° C. where the aluminum elution region is formed, the temperature of the former is about tens of degrees,
The reliability of the contact regions 302 and 303 is not impaired. Heat capacity per unit volume of aluminum (2.4
Since J / ℃ · cm ³⁾ is greater than the thermal capacity per unit volume of silicon ^{(1.7J / ℃ · cm 3)} , by heating the aluminum wiring, because the temperature gradient occurs in the silicon.

Even in the case of the first embodiment, the third
With the same configuration as that of the third embodiment, the effect described in the third embodiment is obtained in addition to the effect described in the first embodiment.

Next, a fourth embodiment will be described with reference to FIG. FIG. 6 is a diagram showing the plane structure thereof, and the configuration is similar to that of the second embodiment already described, but the contact region 107 and the contact region 108 are as shown in FIG. This is different from the second embodiment in that it is not arranged on one horizontal line (horizontal line). The other points are similar to those of the second embodiment.

FIG. 7 is a diagram for explaining the operation when the fourth embodiment is adopted. As described above, since the contact regions 107 and 108 are not arranged on one horizontal line, the aluminum elution region 401 diagonally crosses the pn junction of the diode 120 as shown in FIG. . Therefore, the aluminum elution region 401 from the contact region 106 to the contact region 109 is p
The ratio existing in the n-junction portion is higher than that in the second embodiment, and the on-resistance is further reduced.

Even in the case of the first embodiment, if the same configuration as that of the above-mentioned fourth embodiment is adopted, in addition to the effect of the case of the first embodiment, the above-mentioned fourth embodiment is also provided. The same effect as in the case of the above form occurs.

(1): In the first to fourth embodiments, the case where the antifuse type memory device is formed on the main surface of the semiconductor substrate 100 via the insulator region 101 has been described.
However, the same effect can be obtained when the antifuse type memory device is formed on the main surface of the semiconductor substrate 100 without interposing the insulator region.

(2): In the first to fourth embodiments and the above (1), if the first contact region 106 and the second contact region 109 are formed of silicide such as titanium silicide or tungsten silicide. ,
First contact region 106 and second contact region 1
The aluminum elution region in 09 further reduces the possibility of problems such as deterioration of reliability and increase of on-resistance over time.

(3): In the first to fourth embodiments and the above (1) and (2), if the impurity concentration of the n-type region 103 is high enough to realize ohmic contact, the contact regions 106 and 107. Directly to the n-type region 10
The effect is the same even if it is provided in No. 3. In addition, the p-type region 104
If the impurity concentration is high enough to realize ohmic contact, the effect is the same even if the contact regions 108 and 109 are directly provided in the p-type region 104.

(4): In each of the first to fourth embodiments and the cases of (1) to (3) described above, the case where the antifuse storage device is formed by using the diode has been described. However, in each of the first to fourth embodiments and the cases (1) to (3), the pn of the diode is
Even when the resistance region formed by the low-concentration impurity layer is used as the antifuse type memory device instead of the junction, the first to fourth
The effects described in the above embodiment and the cases of the above (1) to (3) similarly occur. That is, although the resistance is high in the initial state, an aluminum elution region is formed inside the resistance region similarly to the pn junction portion of the diode.
The resistance value becomes sufficiently small without impairing reliability.

(5): In each of the second to fourth embodiments and the cases of (1) to (4), the contact region 107, 108, or 400 connected to the write electrode.
Is not formed on the main surface of the n + type region or the p + type region, but is formed on the main surface of the low concentration impurity region,
If these contact regions and the low-concentration impurity regions are Schottky contacts, the following effects will be produced. That is, at the time of writing, if a reverse bias voltage equal to or higher than the breakdown voltage of the Schottky contact is applied to this Schottky contact, the temperature of this Schottky contact portion rises more quickly and the aluminum elution region is It is easily formed. Therefore, writing becomes easier and the on-resistance decreases.

Further, in each of the above-described embodiments, the case where aluminum is used for the wirings 110, 111, 113, 114, 200 and 201 has been described. But,
Even if these wirings are formed of aluminum wiring containing silicon or copper or silicide of titanium or tungsten, the same effect is obtained.

If each of the contact regions 107 and 108 is formed of a plurality of contact regions, a plurality of metal wirings and a conductive region of silicon are formed inside the pn junction, and the on resistance is further reduced.

[0027]

As described above, according to the present invention, in an antifuse type semiconductor memory device including a diode or a high resistance region, a pair of antifuse type memory devices are connected to an internal circuit at an end of the antifuse type memory device. A read contact region is provided, a new contact region is provided at the end of the antifuse memory device inside at least one of the read contact regions, and the write electrode is read. Is connected to a new contact region or a new contact region, and an aluminum elution region is generated from the new contact region to the inside of the antifuse memory device, so that the on resistance is reduced without lowering the off resistance. It can be made small enough for digital use only. , Now also suitable for analog use, such as high-precision trimming, prevents the on-resistance varies due to deterioration over time or the like, more reliable,
It was possible to obtain the effect that writing could be performed with a lower voltage and current.

[Brief description of the drawings]

1A and 1B are diagrams showing a first embodiment of the present invention, in which FIG. 1A is a sectional view and FIG. 1B is a top view.

FIG. 2 is a diagram for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a diagram showing a planar structure according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining a first effect of the second exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a planar structure according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a planar structure according to a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation when the fourth embodiment of the present invention is adopted.

FIG. 8 is a diagram illustrating the structure and operation of a so-called antifuse type semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 57-3292 as a conventional example.

FIG. 9 shows a pn junction when a reverse bias voltage having sufficiently large voltage and energy is applied to a diode of a conventional example of an antifuse type memory device to break the pn junction until it melts.
It is a figure which shows the elution area | region of the aluminum formed so that a junction might be formed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating film 3 ... N + type area 4 ... N type area 5 ... P type area 6 ... P + area 7, 8 ... Contact area 9 ... Diode 10 ... 1st terminal 11 ... 2nd Terminal 12 ... Interlayer insulating film 13 ... Aluminum elution region 100 ... Semiconductor substrate 101 ... Insulator region 102 ... N + type region 103 ... N type region 104 ... P type region 105 ... P +
Shape region 106, 107, 108, 109 ... Contact region 110 ... First aluminum wiring 111 ... Second
Aluminum wiring 112 ... Interlayer insulating film 113 ... Third
Aluminum wiring 114 ... Fourth aluminum wiring 120 ... Diode 150 ... Aluminum elution region 200 ... Fifth
Aluminum wiring 201 ... Sixth aluminum wiring 202, 20
3 ... Resistor 300 ... N + type region 301 ... P +
Shape region 302, 303 ... Contact region 401 ... Aluminum elution region

Claims (10)

[Claims] 1. A so-called antifuse type which has a high resistance value in the initial state on the main surface of a semiconductor substrate or on the main surface of a semiconductor substrate via an insulator region and stores information by lowering the resistance value. A memory device is formed, and a first contact region to which the first wiring is connected is formed on an end main surface on one end side of the antifuse memory device, and the other end of the antifuse memory device is formed. A second contact region to which the second wiring is connected is formed on the end main surface on the side of the first contact region, and the first contact region is formed on the end main surface on the side of one end of the antifuse storage device. A third contact region to which the third wiring is connected is formed on the inner side of the second contact region, and on the end main surface on the other end side of the antifuse storage device, on the inner side of the second contact region. Fourth contact to which the fourth wiring is connected The semiconductor memory device, and forming a band. 2. An antifuse memory device is formed of a diode having a pn junction composed of a first conductivity type semiconductor region and a second conductivity type semiconductor region, or a resistance region of a first conductivity type semiconductor region. The semiconductor memory device according to claim 1, wherein: 3. A first wiring is connected to a first write electrode, a second wiring is connected to a second write electrode, and the first wiring and the second wiring are respectively connected to an internal circuit. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to. 4. The first wiring and the second wiring are respectively connected to an internal circuit, and the third wiring is connected to the first electrode and the fourth wiring is connected to the second electrode. The semiconductor memory device according to claim 1 or 2. 5. The semiconductor memory device according to claim 1, wherein at least one of the first contact region and the second contact region is formed of silicide. 6. The width of the antifuse memory device in the first contact region portion is set to the width of the antifuse memory device in the third contact region portion or between the third contact region and the fourth contact region. Wider and second
The width of the anti-fuse memory device in the contact region portion of the second fuse is larger than the width of the anti-fuse memory device in the fourth contact region portion or between the third contact region and the fourth contact region, and 6. The semiconductor memory device according to claim 1, wherein each of the first contact region and the second contact region is composed of a plurality of contacts. 7. The individual contacts of the third contact area and the individual contacts of the fourth contact area are arranged so as not to be on the same straight line in the lateral direction. 7. The semiconductor memory device according to any one of items 6 to 6. 8. At least one contact region among the first, second, third and fourth contact regions is connected via a high-concentration impurity region as a means for making ohmic contact with an antifuse type memory device. 8. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 9. A Schottky connection of at least one of the third contact region and the fourth contact region to an antifuse type memory device.
9. The semiconductor memory device according to claim 8. 10. The first, second, third and fourth wirings are
It is formed of aluminum wiring, aluminum wiring containing silicon, copper, or the like, or silicide of titanium, tungsten, or the like.
9. The semiconductor memory device according to any one of items 9.