JPH0897418A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing a semiconductor device which can realize simplification of a manufacturing process and reduction of a contact resistance. CONSTITUTION: In the title semiconductor device, an n-type source region and a drain region are formed in a surface of a p-type well 2 on a p-type silicon substrate 1 to allow a channel region to be interposed between both regions, a gate electrode 4 is formed on a channel region with a gate oxide film 3 therebetween, and a contact hole 9 is formed in a layer insulation film 8 and a wiring structure made of aluminum alloy 10 electrically connected to each of a source region and a drain region by the contact hole 9. Therefore, the contact hole 9 is formed in a position which is near a channel region and does not overlap with it and impurity implantation into a source region and a drain region at a high dosage is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an LDD (Light
The present invention relates to a semiconductor device having a y Doped Drain) structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art An LDD structure is one in which an n ^-- region (n-type low concentration impurity region) is provided in a source region and a drain region adjacent to a channel region.
By relaxing the electric field, it is possible to reduce the influence of hot electrons, which is a problem particularly in a fine MOSFET.

A conventional method of manufacturing a MOSFET will be described with reference to FIG. First, as shown in FIG. 3A, boron (B) ions are implanted into the p-type silicon substrate 1 and the boron is diffused to form the p-type well 2. Next, FIG.
As shown, a thermal oxidation film 3 which forms an element isolation region (field oxide film) and an element formation region by a selective oxidation method and serves as a gate insulating film (first insulating film) on the surface of the element formation region.
To form. Subsequently, as shown in FIG. 3C, an impurity-doped polycrystalline silicon film is deposited on the thermal oxide film 3 and a gate electrode 4 is formed by a photo-etching method. The thermal oxide film 3 is formed using the gate electrode 4 as a mask.
An n ⁻ layer 5 is formed by implanting phosphorus (P) ions underneath.

Next, as shown in FIG. 2D, C is entirely formed.
A silicon dioxide (SiO ₂ ) film 6 is deposited by the VD method, and this is etched by reactive ion etching to leave the silicon dioxide film (SiO ₂ ) 6 only on both side walls of the gate electrode 4 (sidewall formation). Process).
Thereafter, as shown in FIG. 6E, arsenic (As) ions are implanted using the gate electrode 4 and the silicon dioxide film 6 as a mask to form an n ⁺ layer 7. At this time, since the silicon dioxide film 6 is present, the gate electrode 4
The n ⁻ layer is left in the vicinity of both sides of. Then, a silicon dioxide film 8 serving as an interlayer insulating film (second insulating film) is formed on the entire surface of the substrate.
After depositing by CVD method, contact hole 9 for wiring to drain and source by photo-etching method
To form. After that, aluminum (Al) is formed on the entire surface of the substrate.
10 is deposited and patterned by photolithography to form a wiring structure.

[0005]

However, in the above conventional manufacturing method, as shown in FIG.
A silicon dioxide film 6 is deposited, and the silicon dioxide film 6 is formed on both side walls of the gate electrode 4 by reactive ion etching.
However, the number of steps is increased and the yield is reduced due to the difficulty of manufacturing.

Further, due to the etching at the time of forming the contact hole, the contact surfaces of the source region and the drain region made of the n ⁺ layer 7 become rough and the contact portion resistance becomes high.

Further, particularly in a semiconductor device having a gate length of less than 0.5 μm, flatness is improved, reliability of electrical connection with wiring is improved, and local disconnection due to electromigration or stress migration is caused. For the purpose of avoiding the above problem, a metal or the like is embedded in the contact hole before the formation of the wiring structure. However, if the filling is defective at this time, the reliability of the wiring structure is deteriorated.

By the way, when the contact hole 9 needs to be enlarged, the length of each side of the conventional substantially square contact hole 9 shown in FIGS. 6A and 6B is increased. As shown in FIGS. 7A and 7B, it is possible to increase the size of the contact hole 9 while keeping the square shape.

However, for example, assuming that the contact hole 9 on the gate electrode 4 has a conventional size and the contact hole 9 on the source region and the drain region is large in a square shape, as shown in FIG. 7B. In the enlarged contact hole 9, a metal (for example, tungsten) 11 is imperfectly embedded, and as described above, the reliability of the wiring structure deteriorates.

In view of the above circumstances, the present invention provides a semiconductor device that can simplify the manufacturing process and reduce the contact resistance, and does not cause defective filling of contact holes, and a manufacturing method thereof. To aim.

[0011]

The semiconductor device of the present invention comprises:
A second conductive type source region and a drain region are formed on the surface of the first conductive type semiconductor substrate with a channel region interposed therebetween, and a gate electrode is formed on the channel region via a first insulating film. In a semiconductor device in which a wiring structure electrically connected to each of the source region and the drain region is formed by the contact hole formed in the second insulating film formed on the surface of the substrate, the contact hole is It is characterized in that it is formed in the vicinity of the channel region and at a position not overlapping the region, and only the region below the contact hole is a high concentration impurity region.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a second conductivity type source region and a drain region on a surface of a first conductivity type semiconductor substrate so that a channel region is interposed between the two regions. A step of forming a gate electrode on the channel region via a first insulating film, a step of forming a second insulating film on the surface of the substrate, a step of forming a contact hole in the second insulating film, and this contact hole Forming a wiring structure electrically connected to each of the source region and the drain region by a method of manufacturing a semiconductor device, wherein the contact hole is located in the vicinity of the channel region and does not overlap the region. And a high dose of impurities are implanted into the source region and the drain region through the contact hole.

In the method of manufacturing a semiconductor device described above, the contact hole may be formed in a rectangular shape so that the length of its short side is the same for all contact holes.

[0014]

According to the first structure, the contact hole is formed in the vicinity of the channel region and at a position not overlapping the region, and only the region below the contact hole is the high concentration impurity region. Therefore, the LDD structure is realized, and the effect of hot electrons can be reduced by relaxing the electric field.

According to the second structure, the contact hole is formed in the vicinity of the channel region and at a position not overlapping the region, and a high dose is provided to the source region and the drain region through the contact hole. Since the impurities are implanted in a large amount, a semiconductor device having an LDD structure can be manufactured without requiring a sidewall process, and the semiconductor manufacturing process can be simplified and the manufacturing can be facilitated. Furthermore, after forming the contact hole, impurity implantation is performed at a high dose to obtain a high concentration source region and drain region, so that the surface roughness of the contacted portion of the source region and drain region is reduced, and the contact portion resistance is reduced. Can be lowered.

By the way, as described above, if only the lower region of the contact hole is a high concentration impurity region,
In the conventional size contact hole, the high concentration impurity regions of the source region and the drain region are insufficient. In this case, if the length of each side of the contact hole having a conventional shape of a substantially square shape is lengthened to make the contact hole large in a square shape, the defective filling of the contact hole may occur as described in the conventional example. Occurs.

In the case of the third structure described above, since the contact hole is formed in a rectangular shape and the length of its short side is the same for all contact holes, the contact hole is buried. The unevenness of the surface can be reduced by eliminating the variation in the embedded amount, and the reliability of the wiring structure formed on the substrate can be improved.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. In addition, the same reference numerals are added to the same functional units as the conventional ones.

FIGS. 1A to 1E show n according to the present invention.
FIG. 7 is a process drawing showing the method for manufacturing the type MOSFET.

First, as shown in FIG. 1A, boron (B) which is a p-type impurity ion is added to the p-type silicon substrate 1.
Ions are implanted and boron is diffused to form the p-type well 2.

Next, as shown in FIG. 3B, an element isolation region (field oxide film) and an element formation region are formed by a selective oxidation method. Then, a thermal oxide film 3 serving as a gate insulating film (first insulating film) is grown on the surface of the silicon substrate 1 in the element formation region by about 10 nm. After that, a non-doped polycrystalline silicon film is deposited on the entire surface of the substrate to a thickness of about 200 nm, and arsenic (As) ions are implanted into the entire surface so that the strength is 1
Implantation is performed under the conditions of 0 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . Then, heat treatment is performed at 800 ° C. for 30 minutes to pattern the diffusion-activated polycrystalline silicon film by photolithography to form the gate electrode 4. In this embodiment, the non-doped polycrystalline silicon film is deposited, but instead of this, a polycrystalline silicon film pre-doped with impurities such as arsenic may be deposited.

Next, as shown in FIG. 3C, with the gate electrode 4 as a mask, phosphorus (P), which is an n-type impurity ion, has an implantation strength of 90 keV and a dose amount of 2 ×.
Ions are implanted under the thermal oxide film 3 under the condition of 10 ¹³ cm ^-2 and heat-treated at about 900 ° C. to form diffusion-activated n ⁻ layers (source regions, drain regions) 5 and 5. By the ion implantation using the gate electrode 4 as a mask, a channel region is formed between the n ⁻ layers 5 and 5 (between the source region and the drain region).

Next, as shown in FIG. 3D, a silicon dioxide film 8 to be an interlayer insulating film (second insulating film) is formed on the entire surface of the substrate.
Is deposited to a thickness of about 500 nm by the CVD method, and then contact holes 9 for forming wirings to the drain and the source are formed by the photoetching method. At this time, the contact holes 9 ... Are formed in the vicinity of the channel region and at a position not overlapping the region. Further, as shown in FIG. 2, the contact hole 9 has an opening shape of a rectangular shape, and the length of the short side of the contact hole 9 is all the contact holes 9.
Are formed to have the same length.

Next, as shown in FIG. 1E, the silicon dioxide film 8 is used as a mask to reach the n ⁻ source and drain regions through the contact hole 9.
Arsenic, which is an n-type impurity ion, is implanted under the condition that the implantation strength is 50 keV and the high dose amount is 5 × 10 ¹⁵ cm ⁻² . After that, heat treatment at about 900 ° C.
^{The +} layer (source region, drain region) 7 is activated.

Next, tungsten 11 is deposited on the entire surface of the substrate by the tungsten CVD method and is etched by reactive ion etching until the interlayer insulating film 8 is exposed. As a result, the tungsten 11 is buried in the contact holes 9. Then, the aluminum alloy 10 is deposited on the substrate by a method such as sputtering, and is patterned by a photo-etching method to form a wiring structure.

According to the above manufacturing method, the contact hole 9 is formed in the vicinity of the channel region and at a position not overlapping the region, and the contact hole 9 is formed.
Since the impurity is implanted into the source region and the drain region of the n ⁻ layer 5 at a high dose through the n ⁻ layer 5, an n-type MOSFET having an LDD structure can be manufactured without the need for a sidewall process, and the semiconductor manufacturing process can be simplified and Manufacturing can be facilitated.

Further, since the high-concentration source region and drain region (n ⁺ layer) are obtained after forming the contact hole 9, the surface roughness can be reduced and the contact portion resistance can be lowered.

Further, as in the above-mentioned embodiment, the contact holes 9 are formed in a rectangular shape and the lengths of the short sides of all the contact holes 9 are the same. In embedding hole 9,
It is possible to eliminate variations in the embedded amount. That is, as shown in FIG. 3, for example, the contact hole 9 on the gate electrode 4 is left as the conventional size, and the tungsten CVD condition is set so that the contact hole 9 of this size is appropriately filled. Even so, as shown in FIG. 4, since the length of the short side of the contact hole 9 on the source region and the drain region is the same as the length of the side of the contact hole 9 on the gate electrode 4, It meets the above-mentioned tungsten CVD conditions and does not cause defective filling.

In the n-type MOSFET manufactured by the above-described manufacturing method, the n-type source region and the drain region are provided on the surface of the p-type well 2 on the p-type silicon substrate 1 with the channel region interposed therebetween. The gate electrode 4 is formed on the channel region via the gate oxide film 3, and the contact hole 9 is formed in the interlayer insulating film 8.
In the structure having a wiring structure 10 electrically connected to each of the source region and the drain region, the contact hole 9 is formed in the vicinity of the channel region and at a position not overlapping the region. With
Of the source region and drain region of the n ⁻ layer 5, only the region below the contact hole 9 has an n ⁺ layer 7. Thereby, the LDD structure is realized, and the effect of hot electrons can be reduced by relaxing the electric field.

Although the first conductivity type is p-type and the second conductivity type is n-type in this embodiment, it is needless to say that it is not limited to this.

[0031]

As described above, according to the present invention, LDD
The manufacturing process of the semiconductor device having the structure can be simplified, and the contact resistance between the source region and the drain region and the wiring can be reduced. Also,
By forming the contact hole in a rectangular shape so that the length of the short side thereof is the same for all contact holes, defective contact hole filling defects are reduced and the reliability of the wiring structure is improved. Will also be played.

[Brief description of drawings]

FIG. 1 is a process drawing showing a method for manufacturing an n-type MOSFET of the present invention.

FIG. 2 is an n-type MO showing a contact hole of the present invention.
It is a top view of SFET.

3A and 3B are explanatory views of a contact hole having a square-shaped opening, FIG. 3A is a plan view, and FIG. 3B is a sectional view taken along the line CC of FIG. 3A. is there.

4A and 4B are explanatory views showing a contact hole having a rectangular opening of the present invention, in which FIG. 4A is a plan view and FIG. 4B is a view taken along the line D-D in FIG. 4A. FIG.

FIG. 5 is a process chart showing a method of manufacturing a conventional n-type MOSFET.

6A and 6B are explanatory views of a contact hole having a square opening, FIG. 6A is a plan view, and FIG. 6B is a sectional view taken along the line AA of FIG. 6A. is there.

7A and 7B are explanatory views showing a square contact hole in which each side is enlarged to increase an opening area. FIG. 7A is a plan view and FIG. 7B is B in FIG. 7A. FIG. 6 is a cross-sectional view of a main part taken along the arrow B.

[Explanation of symbols]

1 p-type silicon substrate 2 p-type well layer 3 thermal oxide film (first insulating film) 4 gate electrode 5 n ^- layer (n-type low-concentration impurity layer) 7 n ⁺ layer (n-type high-concentration impurity layer) 8 Interlayer insulation film (second insulation film) 9 Contact hole 10 Aluminum alloy

Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 29/78 301 Y (72) Inventor Yasuyuki Shindo 1-3-6 Nakamagome, Ota-ku, Tokyo Ricoh Company, Ltd. Within

Claims (3)

[Claims] 1. A second conductive film is formed on the surface of a semiconductor substrate of the first conductivity type.
A conductive type source region and a drain region are formed with a channel region interposed between both regions, a gate electrode is formed on the channel region via a first insulating film, and a second insulating film is coated on the surface of the substrate. In a semiconductor device in which a wiring structure electrically connected to each of the source region and the drain region is formed by the contact hole formed in the above, the contact hole is in the vicinity of the channel region and does not overlap the region. A semiconductor device, wherein the semiconductor device is formed at a position and only the lower region of the contact hole is a high concentration impurity region. 2. A second conductive film is formed on the surface of the semiconductor substrate of the first conductivity type.
Forming a source and drain regions of conductivity type so that a channel region is interposed between the two regions; forming a gate electrode on the channel region via a first insulating film; A semiconductor device including a step of forming an insulating film, a step of forming a contact hole in a second insulating film, and a step of forming a wiring structure electrically connected to each of the source region and the drain region by the contact hole. In the manufacturing method of the above method, the contact hole is formed in the vicinity of the channel region and at a position not overlapping the region, and impurity implantation is performed with a high dose amount into the source region and the drain region through the contact hole. A method for manufacturing a semiconductor device, comprising: 3. The semiconductor device according to claim 2, wherein the contact hole is formed in a rectangular shape so that the length of its short side is the same for all contact holes. Production method.