JPH0887457A - Acquisition device for battery abnormality information on ram - Google Patents

Abstract

PURPOSE: To record the fact of destruction when the storage contents of the RAM backed up by a battery are destroyed due to a stop of electricity supply to the RAM. CONSTITUTION: The acquisition device for battery abnormality information on the RAM 5 is equipped with the RAM 5, a main power source 1 which supplies a driving voltage to the electric feed terminals of the RAM 5, a backup power source 3 which can supply voltages similar to signal voltages that the chip selector terminal and read/write terminal of the RAM 5 require and supplies a power to the electric feed terminals at the time of interruption of the main power source 1, and delay circuits 8 and 14 which are interposed between the backup power source 3 and the chip selector terminal and read/write terminal of the RAM 5 and delay a voltage rise for the chip selector terminal and read/write terminal than a voltage rise for the electric feed terminal when electricity begins to be fed only from the backup power source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery abnormality information acquiring device for a RAM that acquires battery abnormality information for a battery backup RAM.

[0002]

2. Description of the Related Art A RAM (random access memory) used in recent years is equipped with a battery so that the contents of the RAM can be retained even if the main power source of the system main body such as a computer is cut off for some reason. There are many things that have become (Battery backup RA
M ”).

However, the battery backup RA
Even for M, the backup power supply is interrupted due to some reason such as turning off the main power supply while the battery is exhausted, or the operator accidentally removing the battery while the main power supply was cut off. The contents of RAM may be destroyed.

Since the user thinks that the RAM is backed up, the abnormality detection may be delayed in such a case. Therefore, in the conventional battery backup RAM, a keyword is written in a specific address of the RAM, and then the keyword is referred to for every event to confirm whether or not the content of the RAM is correct.

[0005]

However, such a keyword does not positively indicate that the RAM contents have been destroyed, and at least the RAM contents of the keyword portion are destroyed due to the fact that the keyword is correct. It can only be confirmed that there is no.

Therefore, even if all the power supply to the RAM is stopped and the content of the RAM is destroyed, if the content of the keyword part remains unaltered by accident, the system main body is It operates assuming that the information has not been destroyed.

Therefore, the RAM is
However, the abnormal operation occurs and the reliability of the entire system (entire apparatus) is reduced.

The present invention has been made in consideration of such a situation, and is an RA in which battery backup is performed.
An object of the present invention is to provide a battery abnormality information acquisition device for a RAM, which records the fact of destruction when the contents stored in the RAM are destroyed when power supply to M is stopped.

[0009]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a RAM and a RAM.
A backup power supply that can supply a voltage equivalent to the signal voltage required by the RAM chip selector terminal and read / write terminal to the main power supply that supplies the drive voltage to the power supply terminal, and that supplies power to the power supply terminal when the main power is cut off. When the power supply is inserted between the backup power supply and the chip selector terminal and read / write terminal of the RAM, and the power supply is started only from the backup power supply, the chip selector terminal and the read / write operation are performed rather than the voltage increase to the power supply terminal. R with a delay circuit for delaying the voltage rise to the terminal
It is a device for acquiring battery abnormality information of AM.

The invention according to claim 2 is a RAM
And a main power supply for supplying a drive voltage to the power supply terminal of the RAM, and a voltage equivalent to the signal voltage required by the chip selector terminal and the read / write terminal of the RAM, and the power supply terminal when the main power supply is cut off. When a backup power supply for supplying power to the power supply is inserted between the backup power supply and the chip selector terminal and read / write terminal of the RAM, and power supply is started from only the backup power supply,
A delay circuit that delays the voltage rise to the chip selector terminal and read / write terminal rather than the voltage rise to the power supply terminal, and the voltage application to the chip selector terminal and read / write terminal corresponding to the start of power supply from only the backup power supply writes data to RAM It is a device for acquiring the battery abnormality information of the RAM, which is provided with a flag writing means for writing the specific information to the specific address of the RAM when the available voltage is reached.

[0011]

Therefore, first, in the RAM battery abnormality information acquiring apparatus according to the first aspect of the invention, the operation of the RAM is guaranteed by the main power source in the normal state.

The contents of the RAM are held by the backup power source when the power supply from the main power source provided in the main body of the system is stopped. Next, for some reason, the power supply to the RAM is stopped,
When power supply is started only from the backup power supply,
That is, for example, when the main power supply is stopped and the backup power supply is also replaced, power supply to the power supply terminal of the RAM is started, and the wiring between the chip selector terminal and the read / write terminal and the backup power supply causes the chip selector terminal. Voltage is also applied to the read / write terminal.

However, due to the delay circuit, the timing of applying this voltage is delayed from the power feeding to the power feeding terminal.
Then, when the chip selector terminal and the read / write terminal reach the specified voltage, that is, when each terminal is turned on, the power supply from the power supply terminal to the RAM has already been completed, and the RAM is in the operable state. There is.

If the RAM is in the operable state and the chip selector terminal and the read / write terminal are in the ON state, data is written to the RAM. Here, "when power supply is started from only the backup power supply" means, for example, that the system main body having the main power supply is disconnected from the RAM for some reason, or the main body of the system main body is disconnected. Since the power is cut off, null is written at the head address of the RAM under the above conditions.

Therefore, when the connection with the system main body or the system main body itself is restored, it is possible to determine whether or not the contents of the RAM are destroyed by checking the above-mentioned address of the RAM. .

Further, in the battery abnormality information acquisition device of the RAM of the invention according to claim 2, the same operation as in the invention according to claim 1 is performed, and the flag writing means is used to "use only the backup power source. If the RAM is in an operable state and the chip selector terminal and the read / write terminal are turned on after "power supply is started", specific information is written to a specific address, so whether the content of the RAM is destroyed or not. Can be determined.

In this case, since free information can be written in a location other than the head address of RAM, RA
Even when the head address of M must be used for another purpose, the above determination can be performed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram showing an example of a system to which the present invention is applied, and FIG. 2 is a configuration diagram showing an embodiment of a battery abnormality information acquisition device of a RAM according to the present invention.

In FIG. 1, the battery backup RAM which is the object of this embodiment is usually provided on the option board 2 connected to the system body 1. FIG. 1 shows that the option board 2 is removed while the system body 1 is operating. The main power supply that supplies power to the battery backup RAM in a normal state is provided in, for example, the system body 1.

In the RAM battery abnormality information acquisition apparatus of FIG. 2, one end of the battery 3 is connected to the power supply terminal Vcc of the RAM 5 through the backflow preventing diode 4, and the other end of the battery 3 is grounded. Further, a power supply line 6 from the system body 1 is connected between the diode 4 and the power supply terminal Vcc through a backflow preventing diode 7.
When the system body 1 and the option board 1 are connected, power is supplied to the RAM 5 from the power supply line 6.

A resistor 8 and a Schmitt trigger 9 are connected in series between the diode 4 and the power supply terminal Vcc,
The output terminals of the Schmitt trigger 9 are connected to the WR selector 10 and the CS selector 11, respectively. further,
The other ends of the WR selector 10 and the CS selector 11 are connected to the read / write terminal WR and the chip select terminal CS of the RAM 5, respectively. The RAM 5 can read and write data in a state where there are inputs to the chip select terminal CS and the read / write terminal WR, that is, in an ON state.

Here, the WR and CS selectors 10, 1
1 is connected to the input lines 12a and 13a from the respective batteries when the power supply to the power supply terminal Vcc is cut off. Further, when there is an input from the input lines 12b, 13b from the system body 1 side, the connection of the input lines 12a, 13a from the battery side is cut off.

The battery 3 is also provided with a read / write terminal W via the input lines 12b and 13b from the system body 1.
A voltage equivalent to the voltage input to the R and chip select terminals CS can be supplied via the input lines 12b and 13b. That is, the battery 3 can guarantee the operation of the RAM 5 as a signal supply source for the read / write terminal WR and the chip select terminal CS. Further, the voltage supplied from the battery 3 to the power supply terminal Vcc guarantees the operation of the RAM 5.

On the other hand, the capacitor 8 is connected to the resistor 8 and the Schmitt trigger 9, and the other end is grounded. Here, the resistor 8 and the capacitor 14 constitute a delay circuit that delays the rise of the voltage, and further, the voltage is applied to the selectors 10 and 11 side only when the Schmitt trigger 9 raises the voltage above a certain voltage. It is like this.

Therefore, for example, when power supply from only the battery 3 is started, such as when the battery 3 is replaced, when no power is supplied from the system body 1 and no power is supplied from the battery 3, first, power is supplied to the power supply terminal Vcc. Rises, and a little later, the signal input to the chip select terminal CS and the read / write terminal WR rises.

On the other hand, the address terminal AD of the RAM 5 is connected to the address bus of the system body 1 via the address input line 15, and the data terminal DATA is connected to the data bus of the system body 1 via the data input line 16. .
The address input line 15 and the data input line 16 are respectively provided with a resistor 17 and a resistor 18 for protecting the circuit.
Has been inserted.

Next, the operation of the battery abnormality information acquisition device of the RAM of the present embodiment configured as described above will be described. As a case where the device of this embodiment works effectively, for example, 1) when the option board is removed while the system body 1 is operating and the battery 3 is further replaced because the battery is exhausted, 2) When the system body 1 is stopped and the battery 3 is replaced, 3) When the option board 2 is removed, or when the system body 1 is stopped and a worker accidentally removes the battery 3, the following may be considered. To be It should be noted that the battery backup RAM does not have to be on the option board when the system body is stopped in 2) and 3).

In the present embodiment, the case of 1) will be considered for convenience of explanation. FIG. 3 is an operation timing chart of each unit of the battery abnormality information acquisition device of the RAM of this embodiment, and FIG.
It is an operation | movement flowchart of the same apparatus, and operation | movement is demonstrated along these.

First, the system is operating normally by being supplied with power from the power supply terminal Vcc, and under the control of the system body, the chip select terminal CS and the read / write terminal W.
R, address terminals AD, data terminals DATA, etc. are provided with on / off inputs, data inputs, etc. (A in FIG. 3).
Until).

In this state, the option board 2 is removed from the system body 1 (ST1 in FIG. 4), and the battery 3
Are exchanged (ST2 in FIG. 4, A to C in FIG. 3). At this time, in FIG. 3, by removing the battery 3 (A in FIG. 3), each terminal Vcc, CS, WR, AD, DATA
Voltage gradually decreases to an inoperable voltage near 0 V (B in FIG. 3).

After mounting the battery 3 (C in FIG. 3), first, the voltage of the power supply terminal Vcc gradually rises to the RAM operating voltage (ST3 in FIG. 4, C to D in FIG. 3). RAM5
Requires a certain amount of time until a prescribed voltage is applied to the power supply terminal Vcc and stable operation becomes possible. However, in the device of this embodiment, the voltage applied to the chip select terminal CS and the read / write terminal WR rises with a delay with respect to the power supply by the circuit including the resistor 8, the capacitor 14, and the Schmitt trigger 9 (ST4 in FIG. 4, FIG. 3). D ~
E) Therefore, when the voltage to the chip select terminal CS and the read / write terminal WR reaches the specified voltage, the RAM
5 is fully operational.

At this time, the chip select terminal C
The reason why the voltage of the S and read / write terminals WR rises is that the input lines 12a and 13a are in a connected state depending on the conditions of the CS and WR selectors 10 and 11 described above.

Next, when the RAM 5 is supplied with power and the specified voltage is applied to the chip select terminal CS and the read / write terminal WR, that is, when the RAM 5 is turned on, the power supply is completely cut off,
A flag indicating that the contents are destroyed is written in the RAM 5 (ST5 in FIG. 4, E in FIG. 3).

The flag corresponds to the data input to the address terminal AD and the data terminal DATA,
Here, since the option board 1 is removed from the main body and the terminals AD and DATA are open, specifically, null is written at the head address of the RAM 5, that is, 0 is written at address 0. This also applies to the cases 2) and 3).

The above is the flag write operation when the power supply to the battery backup RAM is completely cut off and the content data is destroyed. Further, the recovery procedure of the RAM 5 based on this flag will be described below.

First, the option board 2 is attached to the system body 1 and the RAM 5 is returned to a state accessible from the system body (E in FIG. 3). The system main body accesses the flag address, that is, the head address of the RAM 5 at regular intervals, for example, and checks whether the flag is set (ST6 in FIG. 4).

If the flag is set, that is, null
If there is data (ST7 in FIG. 4), it is considered that the contents of RAM5 may have been destroyed, and the necessary corrections are made to the contents of RAM5 (ST8 in FIG. 4).

On the other hand, if the flag is not set (ST7 in FIG. 4), the contents of the RAM 5 have not been destroyed, so the system main body considers that the contents of the RAM 5 have not been destroyed and returns to normal operation ( ST9 of FIG. 4).

As described above, the apparatus for acquiring the battery abnormality information of the RAM according to the present embodiment has the battery 3, the power supply terminal Vcc, the chip select terminal CS, and the read / write terminal W.
Wiring between R, battery 3 and chip select terminal C
Resistor 8 and capacitor 14 between S and read / write terminal WR
Since the chip selector terminal and the read / write terminal are turned on after the RAM is ready to operate by providing a delay circuit consisting of, the power supply to the RAM is stopped, and then the battery 3 restarts the power supply. When the contents of the RAM are destroyed, that is, nu is set in the head address of the RAM 5 as a flag indicating the destruction of the RAM contents.
ll is written.

Therefore, the system main body can determine whether or not the state of the RAM is normal by examining this flag. Also, unlike the keyword method, this flag is set based on the fact that the RAM contents are destroyed, so at least for the above reason, RA
When the contents of M are destroyed, they can be the target of the check.

Further, by providing such a flag means, for example, if the system main body checks the flag at regular intervals, it is possible to realize an automatic return function at the time of boat exchange and other state changes. .

As described above, R according to this embodiment
The battery abnormality information acquisition device of AM is the system main unit 1
The selectors 10 and 11 are provided between the input lines 12b and 13b from the battery 3 and the input lines 12a and 13a from the battery 3 so that the input lines 12a and 13a are valid only when the power supply from the battery 3 rises. Since the system main unit is operating and connected to this,
Normal operation can be ensured.

FIG. 5 is a block diagram showing another embodiment of the battery abnormality information acquisition device of the RAM according to the present invention.
The same parts as those of the above are denoted by the same reference numerals, and the description thereof will be omitted. Here, only different parts will be described.

In FIG. 5, the battery 3 and the diode 4 are shown.
The flag writing unit 19 is connected between the two, and power is supplied from the battery 3 to the flag writing unit 19. Further, from the flag writing unit 19 to the signal line 20 and the amplifier 2
Is connected to the address terminal AD of the RAM 5 via 1,
On the other hand, through the signal line 22 and the amplifier 23, the data terminal DA
Connected to TA.

The flag writing section 19 is provided with a storage section containing an address address and a storage section containing data, and, for example, only once when the power supply to the main body of the flag writing section is interrupted and then restored again. The accommodation data are output via the signal lines 20 and 22. After each data (address and data) is output, the flag writing unit 19 is disconnected from the signal lines 20 and 22.

By the way, the above address and data are
When electric power is supplied to the amplifiers 21 and 22 provided on the corresponding signal lines 20 and 22, and the operating state is reached, the RAM 5 is supplied from the address terminal AD and the data terminal DATA.
Is input to

Power supply lines 24 and 25 from the battery 3 are provided to supply this power. The power supply line 24 is connected to a resistor 26 from the output of the Schmitt trigger 9.
It is connected to the amplifier 21 via. Also, the resistance 26
The capacitor 27 is connected between the amplifier 21 and the amplifier 21 and is further grounded. On the other hand, the power supply line 25 is also connected to the amplifier 23 via the resistor 28 from the output end of the Schmitt trigger 9. A capacitor 29 is connected between the resistor 28 and the amplifier 23, and is further grounded.

The resistor 26 and the capacitor 27 and the resistor 28 and the capacitor 29 respectively form a delay circuit. Due to these delay circuits, the amplifiers 21 and 23 are provided.
To the chip select terminal CS and the read / write terminal WR is delayed.
Therefore, the above-mentioned data output from the flag writing unit 19 to the RAM 5 is performed after the RAM 5 becomes the writable state.

Next, the operation of the battery abnormality information acquiring apparatus for the RAM of the present embodiment configured as described above will be described. First, when the apparatus of this embodiment works effectively, it is the same as that of the previous embodiment. Also, the operation flow is the same except for the flag write operation, and therefore FIG.
Only different parts will be described with reference to the operation timing charts of the respective parts of the apparatus.

First, in FIG. 6, the operation from A to E is the same as the case of FIG. 3 except the power feeding operation of the amplifiers 21 and 23. Unlike the case of the previous embodiment, the power supply terminal Vc
The flags are not written even if the necessary voltage rises to the c, chip select terminal CS, and read / write terminal WR (E in FIG. 6). Actually, n is set in the head address of RAM5.
This is because the writing of "ull" is performed, but in this embodiment, the head address is not always the designated address of the flag.

Next, because of the delay circuit described above, the power supply to the amplifiers 21 and 23 rises after the chip select terminal CS and the read / write terminal WR (E to E2 in FIG. 6).
When this power supply rises and the amplifiers 21 and 23 are in the operating state, each data of the address and the data of the flag writing unit 19 is addressed only once by the address terminal A under the above-mentioned conditions.
It is output to D and the data terminal DATA. By this output, the flag data is written in the specific flag address on the RAM 5 (E2 in FIG. 6).

The following operation is the same as that of the previous embodiment and will not be described. However, the address and the content in which the flag is written are not always the same as those in the previous embodiment, and the system main body 1 checks the address and the content specified by the flag writing unit 19 to check the state of the RAM. become.

As described above, the battery abnormality information acquiring device of the RAM according to the present embodiment can obtain the same effect as that of the above-mentioned embodiment, and the flag writing unit 19 flags any information at any address. Therefore, even if the head address of the RAM must be used for another purpose, it is possible to determine whether the RAM content state is destroyed.

Further, since the flag has a high degree of freedom, it is possible to provide a more reliable state discriminating means. If, for example, the setting of a hard switch such as a DIP switch is used as the value of the address and the data output by the flag writing unit 19, automatic reference can be made when the RAM 5 starts up, without human or software intervention. Writing is possible. Further, the present invention can be variously modified without departing from the gist thereof.

[0055]

As described above in detail, according to the present invention, when the power supply to the RAM backed up by the battery is stopped and the stored contents of the RAM are destroyed, the fact of the destruction is recorded. It is possible to provide a device for acquiring RAM battery abnormality information.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an example of a system to which the present invention is applied.

FIG. 2 is a configuration diagram showing an embodiment of a battery abnormality information acquisition device of a RAM according to the present invention.

FIG. 3 is an operation timing chart of each unit of the battery abnormality information acquisition device of the RAM of the embodiment.

FIG. 4 is an operation flow chart of each unit of the apparatus for acquiring battery abnormality information in the RAM of the same embodiment

FIG. 5 is a configuration diagram showing another embodiment of the battery abnormality information acquisition device of the RAM according to the present invention.

FIG. 6 is an operation timing chart of each unit of the battery abnormality information acquisition unit of the RAM of the embodiment.

[Explanation of symbols]

1 ... System main body, 3 ... Battery, 5 ... RAM, 6 ... Feed line, 8 ... Resistor, 19 ... Flag writing section, 26 ... Resistor, 2
7 ... Capacitor, 28 ... Resistor, 29 ... Capacitor, AD
... Address terminal, CS ... Chip select terminal, DATA
... data terminal, Vcc ... power supply terminal, WR ... read / write terminal.

Claims (2)

[Claims] 1. A RAM, a main power supply for supplying a drive voltage to a power supply terminal of the RAM, a voltage equivalent to a signal voltage required by a chip selector terminal and a read / write terminal of the RAM, and A backup power supply that supplies power to the power supply terminal when the main power supply is cut off, and is inserted between the backup power supply and the chip selector terminal and read / write terminal of the RAM, and power supply is started only from the backup power supply. At this time, the battery abnormality information acquisition device of RAM, comprising: a delay circuit that delays a voltage increase to the chip selector terminal and the read / write terminal rather than a voltage increase to the power supply terminal. 2. A RAM, a main power supply for supplying a drive voltage to a power supply terminal of the RAM, a voltage equivalent to a signal voltage required by a chip selector terminal and a read / write terminal of the RAM, and A backup power supply that supplies power to the power supply terminal when the main power supply is cut off, and is inserted between the backup power supply and the chip selector terminal and read / write terminal of the RAM, and power supply is started only from the backup power supply. At this time, a delay circuit that delays the voltage increase to the chip selector terminal and the read / write terminal rather than the voltage increase to the power supply terminal, and the voltage application to the chip selector terminal and the read / write terminal corresponding to the start of the power supply from only the backup power supply. When the voltage reaches a voltage at which data can be written to the RAM, Acquisition device battery abnormality information in the RAM, characterized in that a flag writing means for writing the specific information to a specific address of the AM.