CN116414599A - Method and device for handling abnormal power failure and electronic equipment - Google Patents

Method and device for handling abnormal power failure and electronic equipment Download PDF

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Publication number
CN116414599A
CN116414599A CN202211655736.3A CN202211655736A CN116414599A CN 116414599 A CN116414599 A CN 116414599A CN 202211655736 A CN202211655736 A CN 202211655736A CN 116414599 A CN116414599 A CN 116414599A
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storage device
storage
controller
power supply
memory
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谢修鑫
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Rockchip Electronics Co Ltd
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Rockchip Electronics Co Ltd
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Priority to CN202211655736.3A priority Critical patent/CN116414599A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3013—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
    • G06F11/3093—Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a method and a device for handling abnormal power failure and electronic equipment. The method comprises the following steps: detecting a power supply voltage output to a storage device to determine whether a power supply abnormality occurs based on the power supply voltage; if the power supply abnormality occurs, a test signal is sent to a storage controller of the storage device; if the storage controller sends out a response signal aiming at the test signal, controlling the storage device to prevent hard reset operation and prolonging operation time; and if the storage controller does not send out the response signal aiming at the test signal, controlling the storage device to carry out hard reset operation; according to the invention, the working state of the storage device is tested through the response signal, so that the data is protected in a targeted manner according to different states of the data when power failure occurs.

Description

Method and device for handling abnormal power failure and electronic equipment
Technical Field
The invention relates to the field of embedded technologies, in particular to a method and a device for processing abnormal power failure and electronic equipment.
Background
The embedded system is easy to start after abnormal power failure because residual storage medium data is in a cache inside the disk, and cannot be written into the disk or is solidifying. Abnormal power failure may cause the participating storage media data to be abnormal or lost, resulting in data or device anomalies.
To prevent such events, one way is to start from the hardware direction, for example, to add a large number of filter capacitors to ensure power stability and to improve the resistance to momentary power failures. Another way is to start from the software direction, for example, to scan the disk for abnormal power loss after each power-on, and recover corrupted data. However, in the prior art, no matter which direction is from, only the probability of the data integrity being destroyed is reduced. This is because if there is a cache in the disk (storage medium), if a power failure causes the controller to be abnormal, even if there is a residual quantity, it is insufficient to cause the data in the cache to be written into the flash memory, so that the abnormal process of the data or the device cannot be prevented, and repair can only be attempted after occurrence. In addition, the software means can only recover part of the damaged data.
Disclosure of Invention
The invention provides a method and a device for processing abnormal power failure and electronic equipment, which can realize data protection when the abnormal power failure occurs.
In one aspect of the invention, a method for handling an abnormal power loss is provided. The method comprises the following steps: detecting a power supply voltage output to a storage device to determine whether a power supply abnormality occurs based on the power supply voltage; if the power supply abnormality occurs, a test signal is sent to a storage controller of the storage device; if the storage controller sends out a response signal aiming at the test signal, controlling the storage device to prevent hard reset operation and prolonging operation time; and if the storage controller does not send out the response signal aiming at the test signal, controlling the storage device to carry out hard reset operation.
In some embodiments, the method further comprises: and if the power supply abnormality occurs, cutting off the power supply output of other paths so as to maintain the power supply to the storage equipment.
In some embodiments, controlling the storage device to prevent a hard reset operation and to extend an operation time includes: and controlling the storage controller to prevent the hard reset operation of the storage device and solidifying the data in the cache of the storage device into the storage unit of the storage device.
In some embodiments, after the data is solidified into the memory element, the method further comprises: and controlling the storage controller to execute power-off reset, so that the storage controller reads configuration information from the memory of the storage device, and restoring the storage device to the working state before the power-off reset according to the configuration information.
In some embodiments, controlling the memory device to perform a hard reset operation includes: and enabling the hard reset of the storage device to be effective, enabling the storage controller to read configuration information from the memory of the storage device after the hard reset, recovering the storage device to a working state according to the configuration information, and solidifying data in the cache of the storage device into a storage unit of the storage device.
In some embodiments, the method further comprises: and if the power supply abnormality occurs, controlling the clock so that the data to be stored is not input to the storage equipment any more.
In another aspect of the invention, an apparatus for handling an abnormal power loss is provided. The device comprises: a power supply output module configured to output a power supply voltage to the storage device; a voltage detection module configured to detect the power supply voltage to determine whether a power supply abnormality occurs based on the power supply voltage, and to transmit a test signal to a memory controller of the memory device if the power supply abnormality occurs; and a main controller configured to control the memory device to prevent a hard reset operation and to extend an operation time if a response signal for the test signal is received from the memory controller, and to control the memory device to perform a hard reset operation if the response signal is not received from the memory controller.
In some embodiments, the power output module is further configured to: and if the power supply abnormality occurs, cutting off the power supply output of other paths so as to maintain the power supply to the storage equipment.
In some embodiments, the master controller is configured to: and if the response signal is received, controlling the storage controller to prevent the hard reset operation of the storage device and solidifying the data in the cache of the storage device into the storage unit of the storage device.
In some embodiments, the master controller is further configured to: and after the data is solidified into the storage unit, controlling the storage controller to execute power-off reset, so that the storage controller reads configuration information from the memory of the storage device, and restoring the storage device to the working state before the power-off reset according to the configuration information.
In some embodiments, the master controller is configured to: and if the response signal is not received, enabling the hard reset of the storage device to be effective, enabling the storage controller to read configuration information from the memory of the storage device after the hard reset, recovering the storage device to a working state according to the configuration information, and solidifying data in the cache of the storage device into a storage unit of the storage device.
In some embodiments, the voltage detection module is further configured to: and if the power supply abnormality occurs, controlling the clock of the main controller so that the data to be stored is not input to the storage equipment any more.
In some embodiments, the voltage detection module is configured to perform a potential operation on a signal line electrically connected between the main controller and the memory controller if a power supply abnormality occurs, such that the memory controller issues the response signal in response to the operation, the main controller being configured to receive the response signal from the memory controller via the signal line.
In some embodiments, the master controller is a memory controller in a chip that stores data to be stored in the memory device, the power output module and the voltage detection module are integrated in a power management integrated circuit that is integrated inside the chip or that is disposed outside the chip.
In yet another aspect of the present invention, an electronic device is provided. The electronic equipment comprises the device for processing abnormal power failure; the storage device comprises a storage controller and a memory, wherein the storage controller is configured to read configuration information from the memory and restore the working state of the storage device according to the configuration information.
In yet another aspect of the invention, a computer-readable medium is provided. The medium has stored thereon a computer program to be executed by a processor to implement the above-described method for handling abnormal power loss.
According to the invention, the power supply voltage condition in the system is monitored in real time, if the phenomenon of power supply abnormality occurs, a corresponding test signal is sent to the storage controller of the storage device, if the response signal sent by the storage controller of the storage device can also be received at the moment, the abnormal power failure is indicated that the storage device is not influenced, the persistence of data is immediately carried out at the moment, the data which is being processed during the power failure is stored, and the data abnormality can be avoided after the power failure; if the response signal is not received, the storage device is indicated to be subjected to the electric effect of falling, and at the moment, the hard reset operation is carried out, so that the storage device can recover the function; and the working state of the storage equipment is tested through the response signal, so that the data is subjected to targeted protection according to different states of the data when power failure occurs.
Drawings
FIG. 1 is a flow chart of a method for handling an abnormal power loss in accordance with an embodiment of the present invention;
FIG. 2 is a block diagram of an apparatus for handling an abnormal power loss in accordance with an embodiment of the present invention;
fig. 3 is a block diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings.
In the prior art, the processing of the power failure exception usually focuses on the recovery of data and the restoration of a scene after the power failure condition occurs, but no scheme for protecting the data when the power is lost exists.
To address at least the above technical problems, the present disclosure provides a method for handling abnormal power loss. According to the method and the device, when the abnormal power supply phenomenon is determined, a test signal is sent to the storage controller of the storage device, the state of the storage device after power failure occurs is judged, if the storage controller of the storage device can work normally, data are immediately subjected to persistence, and if the storage controller of the storage device is affected by power failure, hard reset operation is performed to restore the function of the storage device. In this way, according to the embodiment of the disclosure, when power failure occurs, data can be protected by judging a strategy corresponding to state confirmation of the storage controller of the storage device, and abnormal data after power failure can be avoided to a certain extent.
Hereinafter, a technical scheme according to the present disclosure will be described with reference to specific embodiments and with reference to the accompanying drawings.
FIG. 1 is a flow chart illustrating a method 100 for handling an abnormal power loss in accordance with an embodiment of the present disclosure. Referring to fig. 1, the method 100 includes the following steps 102-108.
In step 102, a supply voltage output to a storage device is detected to determine whether a supply abnormality occurs based on the supply voltage. In some embodiments, the method 100 may further include storing configuration information in a memory of the storage device prior to step 102. In this way, the configuration information is backed up in advance, and after power failure occurs, the data in the memory cannot be lost, so that the function of the storage device can be recovered through the configuration information in the memory.
In some embodiments, whether an abnormal power down signal corresponding to the storage device is received is detected by a real-time voltage detection module. In this way, when the storage device is abnormally powered down, corresponding protection measures are carried out, so that the integrity of the data can be ensured to the greatest extent, and the data is prevented from being lost in the abnormal power down process.
In some embodiments, the storage device may be an SSD (Solid State Disk), UFS (Universal Flash Storage, universal flash memory storage), eMMC (Embedded Multi Media Card ), or the like.
In step 104, a test signal is sent to a storage controller of a storage device, and it is determined whether a response signal sent by the storage controller for the test signal is received, if yes, step 106 is executed, otherwise step 108 is executed.
In some embodiments, the method 100 may further include cutting off other paths of power output to maintain power to the storage device if a power abnormality occurs. In this way, when abnormal power failure occurs, the power supply of the residual electric quantity to the storage device is preferentially ensured, the power supply to other parts is cut off, the operable time of the storage device is prolonged, the rescue success rate of data in the power failure is improved, and the residual electric quantity is ensured to be mainly used for backing up the data.
In some embodiments, the method 100 may further include controlling the clock such that data to be stored is no longer input to the storage device if a power abnormality occurs. For example, the memory controller clock potential of the chip may be pulled low so that the data to be stored is no longer input to the memory device. In this way, the clock potential of the memory controller of the chip is pulled down, so that the memory controller of the chip cannot send out abnormal data on the chip side, and therefore after the chip side sends out the abnormal data, the residual electric quantity is consumed and the memory is not stored in the magnetic disk; closing the transmission of the abnormal data further saves electricity for the power-down recovery operation of the storage device.
In some embodiments, the test signal is sent by pulling down the corresponding IO port.
In step 106, the storage device is controlled to prevent a hard reset operation and to extend the operation time. In some embodiments, the memory controller is controlled to block a hard reset operation of the memory device and solidify data in a cache of the memory device into a memory location of the memory device. In this way, the data in the cache is solidified into the storage unit by using a tiny time period that the power supply is normal after abnormal power failure, so that the situation that the data in the cache is lost after the power failure of the storage device is avoided, the data after the power failure is avoided, and the subsequent recovery of the data is not needed.
In some embodiments, after step 106, the method 100 may further include: and controlling the storage controller to execute power-off reset, so that the storage controller reads configuration information from the memory of the storage device, and restoring the storage device to the working state before the power-off reset according to the configuration information. In this way, when the storage device is further responsive, the hard reset is prevented to prevent information in the cache from being lost after the reset, then the data in the cache of the storage device is persisted into the flash memory, and then the prevented hard reset operation is continuously executed, so that the storage device can be normally used after the power-down restart.
In step 108, the storage device is controlled to perform a hard reset operation. In some embodiments, the storage controller is controlled to execute power-off reset, so that the storage controller reads configuration information from a memory of the storage device, restores the storage device to a working state before the power-off reset according to the configuration information, and solidifies data in a cache of the storage device into a storage unit of the storage device. In this way, in the case where the storage device has been affected by a power failure, restoration of the function can be achieved by the configuration information stored in advance, and the data in the cache is attempted to be solidified after the restoration of the function.
In some embodiments, the memory is RAM (Random Access Memory ), so that the RAM is not powered down, so that information in the RAM is not lost, and meanwhile, erasing and writing are convenient.
Fig. 2 is a block diagram illustrating an apparatus 200 for handling an abnormal power loss according to an embodiment of the present invention. As shown in fig. 2, the apparatus 200 includes a power output module 202, a voltage detection module 204, and a main controller 206.
The power output module 202 is configured to output a power supply voltage to the storage device 208. In some embodiments, the power output module 202 may be further configured to cut off other paths of power output to maintain power to the storage device 208 if a power abnormality occurs.
The voltage detection module 204 is configured to detect the supply voltage to determine whether a power failure has occurred based on the supply voltage and to send a test signal to a memory controller of the memory device 208 if a power failure has occurred.
The master controller 206 is configured to control the storage device 208 to prevent a hard reset operation and extend an operation time if a response signal to the test signal from the storage controller is received, and to control the storage device 208 to perform a hard reset operation if the response signal from the storage controller is not received.
In some embodiments, the master controller 206 may be configured to control the storage controller to block a hard reset operation of the storage device 208 and to solidify data in the cache of the storage device 208 into the storage cells of the storage device 208 if the response signal is received. The main controller 206 may be configured to enable the hard reset of the storage device 208 if the response signal is not received, so that after the hard reset, the storage controller reads configuration information from the memory of the storage device 208, restores the storage device 208 to a working state according to the configuration information, and solidifies data in the cache of the storage device 208 into the storage unit of the storage device 208.
In some embodiments, the main controller 206 is further configured to control the storage controller to perform a power-off reset after the data is solidified into the storage unit, so that the storage controller reads configuration information from the memory of the storage device 208, and restores the storage device 208 to an operating state before the power-off reset according to the configuration information.
In some embodiments, the voltage detection module 204 may be configured to perform a potential operation on a signal line electrically connected between the main controller 206 and the memory controller if a power supply abnormality occurs, so that the memory controller issues the response signal in response to the operation. In some embodiments, the master controller 206 may be configured to receive the response signal from the memory controller via the signal line.
In some embodiments, the voltage detection module 204 may be further configured to control the clock of the master controller 206 such that data to be stored is no longer input to the storage device 208 if a power abnormality occurs.
In some embodiments, the master controller 206 is a memory controller in a chip that stores data to be stored in the memory device 208. In some embodiments, the power output module 202 and the voltage detection module 204 are integrated in a power management integrated circuit that is integrated within the chip or that is disposed external to the chip.
According to another aspect of the invention, fig. 3 is a block diagram illustrating an electronic device 300 according to an embodiment of the invention. Referring to fig. 3, the electronic device 300 includes an apparatus 200 for handling abnormal power loss and a storage device 208.
The apparatus 200 includes a PMIC 201 (Power Management IC, power management integrated circuit) and a memory controller 206. The PMIC 201 includes a voltage detection module 204 and a power supply output module 202.
The storage device 208 includes a storage controller 2086. The storage controller 2086 is coupled to the storage controller 206 of the device 200. The voltage detection module 204 is connected to the power supply output module 202 and the memory controller 2086 of the memory device 208, respectively.
In this way, the voltage detection module 204 is capable of detecting the abnormal power supply condition of the power supply output module 202 in real time, and sending a test signal to the storage controller 2086 of the storage device 208 according to the detection result, that is, correspondingly pulling the IO port potential of the storage controller 2086 of the storage device 208 low, so as to make a determination on the operation condition of the storage controller 2086 of the storage device 208, that is, perform the steps 102 and 104 of the method described above with reference to fig. 1.
In some embodiments, the device 200 is a SoC (System on Chip). In some embodiments, the device 200 and the PMIC 201 may be two separate chips or may be one chip sealed.
In some embodiments, the power output module 202 includes a plurality of output ports, one of which connects to a power input interface of the storage device 208. In this manner, the power output module 202 provides power to the storage device 208 and provides a separate power channel to the storage device 208, which can reserve a separate power channel for the storage device 208 when an abnormal power failure occurs, and extend the runtime of the storage device 208.
In some embodiments, the storage device 208 further includes a cache module 2084, a flash memory module 2082, and a memory module 2088. The buffer module 2084, the flash memory module 2082, and the memory module 2088 are respectively connected to the memory controller 2086 of the memory device 208, and the buffer module 2084 is connected to the flash memory module 2082. In this way, the storage controller 2086 of the storage device 208 is able to obtain the pre-stored configuration information from the memory module 2088 to restore its own function, and control the data in the buffer module 2084 to be solidified into the flash module 2082, i.e. to perform the steps 106 and 108 of the method described above with reference to fig. 1.
In some embodiments, the apparatus 200 includes a memory controller 206. The voltage detection module 204 is also coupled to a memory controller 206 of the device 200. In this way, when an abnormal power-down signal occurs, the corresponding IO port potential of the memory controller 206 of the device 200 can be pulled down, so that the transmission of the abnormal data on the device 200 side can be stopped, and the available electric quantity can be further saved.
In summary, the method and the device for processing abnormal power failure and the electronic device provided by the invention judge whether an abnormal power failure signal is received, if so, power supply except power supply to the storage device is cut off, working time of the storage device is prolonged, meanwhile, a test signal is sent to the storage device to judge whether the storage device can respond or not, if so, normal operation of the storage device is indicated, and at the moment, data in a cache is directly stored into a flash memory for solidification without a recovery step; if the response signal can not be received, the function of the storage device is indicated to be abnormal, at the moment, after the configuration data is recovered from the memory, the data in the cache is stored into the flash memory, so that the solidification of the data being processed during power failure is realized, the influence on the data caused by power failure is avoided from the source, the abnormal situation of the data during power failure is avoided, the abnormal power failure processing is transferred from the recovery after the influence of abnormal power failure to the reduction of the loss probability of the data during the abnormal power failure, the later recovery operation is saved, and the working efficiency is improved.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.

Claims (15)

1. A method for handling an abnormal power loss, comprising:
detecting a power supply voltage output to a storage device to determine whether a power supply abnormality occurs based on the power supply voltage;
if the power supply abnormality occurs, a test signal is sent to a storage controller of the storage device;
if the storage controller sends out a response signal aiming at the test signal, controlling the storage device to prevent hard reset operation and prolonging operation time; and
and if the memory controller does not send out the response signal aiming at the test signal, controlling the memory device to carry out hard reset operation.
2. The method as recited in claim 1, further comprising:
and if the power supply abnormality occurs, cutting off the power supply output of other paths so as to maintain the power supply to the storage equipment.
3. The method of claim 1, wherein controlling the storage device to prevent a hard reset operation and to extend an operation time comprises:
and controlling the storage controller to prevent the hard reset operation of the storage device and solidifying the data in the cache of the storage device into the storage unit of the storage device.
4. The method of claim 3, further comprising, after the data is solidified into the memory element:
and controlling the storage controller to execute power-off reset, so that the storage controller reads configuration information from the memory of the storage device, and restoring the storage device to the working state before the power-off reset according to the configuration information.
5. The method of claim 1, wherein controlling the memory device to perform a hard reset operation comprises:
and enabling the hard reset of the storage device to be effective, enabling the storage controller to read configuration information from the memory of the storage device after the hard reset, recovering the storage device to a working state according to the configuration information, and solidifying data in the cache of the storage device into a storage unit of the storage device.
6. The method as recited in claim 1, further comprising:
and if the power supply abnormality occurs, controlling the clock so that the data to be stored is not input to the storage equipment any more.
7. An apparatus for handling an abnormal power loss, comprising:
a power supply output module configured to output a power supply voltage to the storage device;
a voltage detection module configured to detect the power supply voltage to determine whether a power supply abnormality occurs based on the power supply voltage, and to transmit a test signal to a memory controller of the memory device if the power supply abnormality occurs;
and a main controller configured to control the memory device to prevent a hard reset operation and to extend an operation time if a response signal for the test signal is received from the memory controller, and to control the memory device to perform a hard reset operation if the response signal is not received from the memory controller.
8. The apparatus of claim 7, wherein the power output module is further configured to:
and if the power supply abnormality occurs, cutting off the power supply output of other paths so as to maintain the power supply to the storage equipment.
9. The apparatus of claim 7, wherein the master controller is configured to:
and if the response signal is received, controlling the storage controller to prevent the hard reset operation of the storage device and solidifying the data in the cache of the storage device into the storage unit of the storage device.
10. The apparatus of claim 9, wherein the master controller is further configured to:
and after the data is solidified into the storage unit, controlling the storage controller to execute power-off reset, so that the storage controller reads configuration information from the memory of the storage device, and restoring the storage device to the working state before the power-off reset according to the configuration information.
11. The apparatus of claim 7, wherein the master controller is configured to:
and if the response signal is not received, enabling the hard reset of the storage device to be effective, enabling the storage controller to read configuration information from the memory of the storage device after the hard reset, recovering the storage device to a working state according to the configuration information, and solidifying data in the cache of the storage device into a storage unit of the storage device.
12. The apparatus of claim 7, wherein the voltage detection module is further configured to:
and if the power supply abnormality occurs, controlling the clock of the main controller so that the data to be stored is not input to the storage equipment any more.
13. The apparatus of claim 7, wherein the voltage detection module is configured to perform a potential operation on a signal line electrically connected between the main controller and the memory controller if a power supply abnormality occurs, so that the memory controller issues the response signal in response to the operation,
the main controller is configured to receive the response signal from the memory controller via the signal line.
14. The apparatus of claim 7, wherein the master controller is a memory controller in a chip that stores data to be stored in the memory device,
the power supply output module and the voltage detection module are integrated in a power management integrated circuit, which is integrated inside the chip or provided outside the chip.
15. An electronic device, comprising:
the apparatus of any one of claims 7 to 14; and
the storage device comprises a storage controller and a memory, wherein the storage controller is configured to read configuration information from the memory and restore the working state of the storage device according to the configuration information.
CN202211655736.3A 2022-12-22 2022-12-22 Method and device for handling abnormal power failure and electronic equipment Pending CN116414599A (en)

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Application Number Priority Date Filing Date Title
CN202211655736.3A CN116414599A (en) 2022-12-22 2022-12-22 Method and device for handling abnormal power failure and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211655736.3A CN116414599A (en) 2022-12-22 2022-12-22 Method and device for handling abnormal power failure and electronic equipment

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Publication Number Publication Date
CN116414599A true CN116414599A (en) 2023-07-11

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