JPH0878633A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To recover a drop in impurity concentration near the oxide film interface of a boron implantation region as a channel stopper. CONSTITUTION: Using a nitride film as mask for forming LOCOS, boron is ion-implanted and a boron implantation region 107 is formed inside the p-well 102. An oxide film 108 for element separation is formed by thermal oxidation. A transistor and a capacitor are formed on an active region. An interlayer insulation film is formed and a contact hole 111 is formed on this. Boron is ion-implanted and a contact reinforcing implantation region 112 is formed. Heat treatment for activation of the implantation region 112 is performed at a temperature higher than the maximum temperature for heat treatment in the transistor and capacitor forming process (such as 1,000 deg.C, 10sec.).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation film in a silicon semiconductor device.

[0002]

2. Description of the Related Art Isolation of elements must ensure that there is no electrical interference between the elements during operation of the elements and that the individual elements operate completely independently, and therefore, sufficiently high punch-through breakdown voltage and It is required to have a field inversion voltage. As a method of forming an element isolation region inside a semiconductor device, LOCOS (abbreviation of LOCal Oxidation of Silicon) is used.
Law is common.

A conventional manufacturing method using this LOCOS method will be described with reference to FIGS. First, as shown in FIG. 9, a 100 Å thick silicon oxide film 203 is formed as a pad oxide film on a cleaned p-type silicon substrate 201, and a 1500 Å thick silicon nitride film 204 is formed thereon. After applying a photoresist film 205 thereon, the photolithography technique and the dry etching technique are applied to remove the silicon nitride film 204 and the silicon oxide film 203 in the element isolation region, and boron is ion-implanted for channel stop. A boron implanted region 207 is formed.

Next, as shown in FIG. 10, after removing the photoresist film 205, thermal oxidation is performed in an oxidation furnace to form an element isolation oxide film 208 in the removed region of the silicon nitride film 204. . By carrying out this thermal oxidation under high pressure, the amount of boron taken into the oxide film becomes smaller than that in the case where the oxidation is carried out under normal pressure, and the energy of boron ion implantation shown in FIG. It is possible to improve the punch-through breakdown voltage by selecting the concentration of the formed boron to be maximum at the interface between the oxide film 208 and the silicon.
It is disclosed in Japanese Patent Laid-Open No. 2-112273.

Next, as shown in FIG. 11, the silicon nitride film 204 and the silicon oxide film 203 are removed. afterwards,
Although not shown in the drawing, elements such as transistors and capacitors are formed in the element region by a known method, and necessary wirings are provided to complete the manufacturing process of the semiconductor device.

[0006]

However, in the element isolation film forming method by the conventional manufacturing method as described above,
There are the following problems. Since boron tends to enter the oxide film more than silicon, part of the implanted boron is taken into the oxide film during the thermal oxidation for forming the oxide film for element isolation, and especially the oxide film in the silicon substrate. In the vicinity of the interface with and, the boron concentration is significantly reduced.

As described above, since the amount of boron near the interface is reduced, the field inversion voltage is reduced. Also,
Since the boron concentration is drastically reduced in the vicinity of the interface, the depletion layer extends in the vicinity of the interface as compared with the inside of the substrate, and the punch-through breakdown voltage decreases. That is, the oxide film for element isolation by the conventional method may not be able to fully fulfill the element isolation function.

In FIG. 12, the implantation energy is set to 50 keV so that the boron after ion implantation has a maximum concentration distribution in the vicinity of the interface between the element isolation oxide film formed later and the silicon.
Immediately after implanting 8 × 10 ¹² cm ⁻² of boron and after performing element isolation oxidation of about 3500 Å at 980 ° C.,
It is a simulation result of boron distribution when heat treatment is performed at 850 ° C. for 1 hour as heat treatment for element formation.

As a result of the incorporation of boron into the oxide film, the interface between the oxide film and silicon is located near the peak of the implantation distribution, but the interface with the oxide film at the time when the heat treatment for element formation is completed. The boron concentration in the vicinity is significantly reduced. That is, even if the peak of the implantation distribution coincides with the interface, it is not possible to prevent the decrease in the boron concentration near the interface. Therefore, it is necessary to implant a large amount of boron in order to obtain a sufficient punch-through breakdown voltage and field inversion voltage.

However, the implantation of a large amount of boron causes an increase in implantation defects near the edge of the element isolation oxide film, and as a result, the leakage current of the element may increase and the element characteristics may deteriorate. For example, in a DRAM, the charge retention time is reduced. Japanese Unexamined Patent Application Publication No. 2-112273 discloses that element isolation oxidation is performed under high pressure to suppress boron incorporation into the oxide film to a low level. However, subsequent heat treatment changes the boron concentration. However, it is not a basic solution, although it is better than the case of atmospheric oxidation.

The present invention has been made in view of the above circumstances, and it is possible to prevent a decrease in the boron concentration in the vicinity of the oxide film interface without using an expensive high-pressure oxidation furnace, and an excessive boron implantation amount. An object of the present invention is to provide a manufacturing method capable of manufacturing a highly reliable semiconductor device which can obtain a sufficient punch-through breakdown voltage and a field inversion voltage without increasing the voltage extremely.

[0012]

In order to achieve the above object, according to the present invention, (1) a step of forming a silicon oxide film and a silicon nitride film on a silicon substrate in this order; ) First coating over the area where the active area is to be formed
Forming the photoresist film of (3) the first
Etching the silicon nitride film by using the photoresist film as a mask, and (4) forming boron for a channel stop inside the substrate using the first photoresist film or the silicon nitride film as a mask. Ion implantation as described above, (5) thermal oxidation in an atmosphere containing oxygen to form an element isolation oxide film having a desired thickness, (6) a diffusion layer on the active region, In the method of manufacturing a semiconductor device, which includes an element forming step of forming an electrode and providing necessary wiring, in the step (6), in the final heat treatment of high temperature heat treatment exceeding 800 ° C. There is provided a method for manufacturing a semiconductor device, characterized in that the heat treatment is performed at the highest temperature or higher in the heat treatment in the step (6).

[0013]

In the element forming process of the semiconductor device, various heat treatments such as a thermal oxidation process, a diffusion process, an implantation ion activation process, a silicidation process, and an interlayer insulating film reflow process are performed. These heat treatments are usually limited to a heat treatment temperature that does not destroy the profile of the diffusion layer formed up to that point.

In the present invention, the last high temperature heat treatment among the various high temperature heat treatments (in this specification, the heat treatment at 800 ° C. or higher which affects the boron profile is called high temperature heat treatment). A heat treatment (hereinafter referred to as a second heat treatment) at a high temperature equal to or higher than the maximum temperature of heat treatments (hereinafter, a high temperature heat treatment excluding the last heat treatment is collectively referred to as a first heat treatment) performed in the element forming process up to that point (hereinafter referred to as a first heat treatment). For example, 1000 ° C.). This heat treatment uses RTP (Ra
This can be advantageously performed by the pid thermal process) method.

By carrying out the second heat treatment at a temperature higher than that of the first heat treatment, the following actions and effects are produced. (1) In the element isolation oxide film forming step, the boron concentration in the vicinity of the interface which is lowered by being taken into the oxide film side and further lowered in the subsequent element forming step can be recovered by the second heat treatment. (2) Since the high temperature heat treatment is not performed after the second heat treatment, the boron concentration recovered by the second heat treatment is not lowered again.

As a result, the punch-through breakdown voltage and the field inversion voltage can be improved as compared with the case of forming by the conventional example. Alternatively, the implantation ion dose can be reduced in order to secure the same element isolation capability. Thereby, the occurrence of defects can be suppressed, and the leak current can be suppressed to a low level. Therefore, the charge retention characteristic can be improved in, for example, a DRAM.

The phenomenon that the boron concentration in the vicinity of the interface with the oxide film changes depending on the heat treatment temperature, and the higher the heat treatment temperature, the higher the boron concentration on the silicon side is fair (R.
B. Fair of the Journal of Electrochemical Society (1978, 125th).
Vol., Pp. 2050-2058).

[0018]

Embodiments of the present invention will now be described with reference to the drawings. 1 to 6 are process cross-sectional views sequentially showing the manufacturing process of one embodiment of the present invention. First, as shown in FIG. 1, a p-well 102 is formed in an n-type silicon substrate 101 by a known method, and after cleaning the surface, a 100Å-thick silicon oxide film 103 to be a pad oxide film is formed by a thermal oxidation method. Then, a 1500 Å thick silicon nitride film 104 is formed thereon by the CVD method.

A photoresist film 105 is formed by photolithography to cover the active region, and the silicon nitride film 104 and the silicon oxide film 103 are removed by dry etching using the photoresist film 105 as a mask to remove the silicon in the element isolation region. Expose the substrate surface.

Next, as shown in FIG. 2, the photolithography method is applied again to form a photoresist film 106 covering the region where the p well 102 is not formed. Using this as a mask, boron is used as a mask. , Acceleration energy: 5
0 keV to 120 keV, implantation dose: 8 × 10 ¹² c
Ions are implanted under the condition of m ⁻² to form a boron implanted region 107 for channel stop.

Next, as shown in FIG. 3, after removing the photoresist films 105 and 106 by peeling and removing, the regions where the silicon nitride film has been removed are subjected to wet thermal oxidation in an oxidizing furnace at 980 ° C. under normal pressure. An oxide film 108 for element isolation having a film thickness of about 3500Å is formed. According to the present invention, it is possible to obtain a boron-diffused region having a sufficient concentration as will be described later even by thermal oxidation under normal pressure. However, the pressure thermal oxidation method is not excluded. Next, as shown in FIG. 4, the silicon nitride film 104 and the pad oxide film (103) are removed.

Then, as shown in FIG. 5, the element region is subjected to a first heat treatment at 850 ° C. for a total of 1 hour by a known method to form a transistor 109 and a capacitor 110.

Next, as shown in FIG. 6, a contact hole 111 for the peripheral circuit is opened, and boron is ion-implanted through the contact hole to contact-reinforcing implant region 1.
12 is formed. Then, as the second heat treatment, RTA
Using a (Rapid Thermal Annealing) device, heat treatment is performed at a high temperature for a short time, for example, at 1000 ° C. for 10 seconds to 90 seconds. After that, a DRAM is completed by a known method through steps such as contact filling and wiring formation.

In FIG. 7, boron is ion-implanted at an acceleration energy of 50 keV and a dose of 8 × 10 ¹² cm ⁻² , and 980
Immediately after forming a thermal oxide film of about 3500 Å in humidified oxygen at ℃, heat treatment at 850 ℃ for 1 hour as the first heat treatment, and heat treatment at 1000 ℃ for 10 seconds and 90 seconds as the second heat treatment. It is a simulation result of the boron distribution when it is exposed.

From this figure, after heat treatment at 850 ° C., 5 × 1
The boron concentration on the silicon side at the interface, which was 0 ¹⁶ cm ⁻³ ,
1.2 × 10 ¹⁷ c by heat treatment at 1000 ° C. for 10 seconds
It is 2.4 times higher than m ^-3 . The concentration increase near this interface reaches 1 × 10 ¹¹ cm ^-2 in total. This change in the amount of boron changes when the element isolation oxide film is 3500 Å
This corresponds to an improvement in the field inversion voltage of 1.4V.

Further, even if the heat treatment time is 90 seconds, there is almost no change in the distribution of boron concentration except in the vicinity of the interface. Therefore, this degree of heat treatment does not change the impurity profile of the source / drain regions of the already formed transistor (the heat treatment that does not change the distribution of boron because the diffusion coefficient of boron is larger than that of phosphorus or arsenic). Does not change the impurity distribution in the n-type source / drain region).

FIG. 8 shows acceleration energy: 120 keV,
Dose: Boron ion implantation at 8 × 10 ¹² cm ^-2 , 98
Simulation result of boron distribution after forming an oxide film of about 3500Å at 0 ° C in humidified oxygen, heat-treating at 850 ° C for 1 hour as the first heat treatment, and heat-treating at 1000 ° C for 10 seconds as the second heat treatment Is.

From this figure, the heat treatment at 1000 ° C. for 10 seconds resulted in a boron concentration on the silicon side of the interface of 1.7 ×.
From 10 ¹⁶ cm ^-3 to 4.2 × 10 ¹⁶ cm ^-3 , about 2.6
It can be seen that the number has doubled. These concentrations correspond to 0.28 μm and 0.17 μm in the depletion layer, respectively. Therefore, by adding heat treatment at 1000 ° C. for 10 seconds, the length of the element isolation region required to prevent punch through can be shortened by about 0.1 μm. Conversely, 1
In order to obtain the same boron concentration at the interface as when the heat treatment is not performed at 000 ° C. for 10 seconds, the boron implantation amount can be reduced by 0.4 times, and the charge retention characteristic of the cell can be improved accordingly.

In the above embodiment, the first heat treatment is 85
The case of 0 ° C. for 1 hour is shown, but if the temperature and time affect the boron concentration distribution in the vicinity of the interface with the element isolation oxide film, they coincide with the above temperature and time. Obviously there is no need. Other conditions for the first heat treatment include, for example, the case of 800 ° C. to 950 ° C. for 30 minutes to 4 hours.

In the above embodiment, the second heat treatment is 1
Although the case of 10 seconds to 90 seconds at 000 ° C. is shown, this temperature and time are higher than the first heat treatment temperature, and by performing the second heat treatment, the operation of the element formed up to that time is inconvenient. Obviously, it is not necessary to match the above temperature and time as long as the temperature and time do not cause Although such conditions vary depending on the structure of the element to be manufactured, other conditions of the second heat treatment include, for example, the case of 1050 ° C. to 1200 ° C. for 1 second to 2 minutes.

The above embodiment is based on p-type in an n-type silicon substrate.
Although given for a single well structure of wells only, the invention is not limited to specific well structures, for example forming shallow p-wells and n-wells in a deep p-well or n-well. It is also applicable to the case of so-called triple well.

[0032]

According to the element isolation forming method of the present invention, the boron concentration at the oxide film interface reduced by the first heat treatment used in the step of forming elements such as thermal oxidation and the subsequent transistor, capacitor, etc. Can be recovered by the second heat treatment performed at a temperature higher than the heat treatment temperature. As a result, when the boron implantation amount is the same, the length of the element isolation region required to prevent punch through can be shortened, which can contribute to higher density of the semiconductor device.

Further, as compared with the case where this heat treatment is not performed, the same punch-through breakdown voltage and field inversion voltage can be obtained with a smaller amount of boron implantation, and the amount of defects introduced by boron implantation can be suppressed to a low level. Therefore, the leak current of the device can be reduced, and for example, when the present invention is applied to the manufacture of DRAM, the charge retention time of the memory cell can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in one manufacturing process of an embodiment of the present invention.

FIG. 2 is a sectional view of the embodiment of the present invention during the manufacturing process following the process of FIG. 1;

FIG. 3 is a sectional view of the embodiment of the present invention during the manufacturing process following the process of FIG. 2;

FIG. 4 is a sectional view of the embodiment of the present invention during the manufacturing process following the process of FIG. 3;

FIG. 5 is a sectional view of the embodiment of the present invention during the manufacturing process following the process of FIG. 4;

FIG. 6 is a sectional view of the embodiment of the present invention during the manufacturing process following the process of FIG. 5;

FIG. 7 is a graph showing changes in boron concentration distribution in an element isolation region due to heat treatment according to an example of the present invention.

FIG. 8 is a graph showing changes in boron concentration distribution in an element isolation region due to heat treatment according to an example of the present invention.

FIG. 9 is a cross-sectional view in one manufacturing process in the conventional manufacturing method.

FIG. 10 is a cross-sectional view showing a manufacturing step of the conventional manufacturing method that is subsequent to the step of FIG. 9;

FIG. 11 is a cross-sectional view showing one manufacturing step in the conventional manufacturing method, following the step of FIG. 10;

FIG. 12 is a graph showing changes in the boron concentration distribution in the element isolation region due to heat treatment in the conventional example.

[Explanation of symbols]

 101 n-type silicon substrate 201 p-type silicon substrate 102 p-well 103, 203 silicon oxide film (pad oxide film) 104, 204 silicon nitride film 105, 106, 205 photoresist film 107, 207 boron implantation region 108, 208 for element isolation Oxide film 109 Transistor 110 Capacitor 111 Contact hole 112 Contact reinforcement injection region

Claims (4)

[Claims] 1. A step of (1) depositing a silicon oxide film and a silicon nitride film on a silicon substrate in this order, and (2) a first photoresist film covering an area where an active area is to be formed. And (3) a step of etching away the silicon nitride film using the first photoresist film as a mask, and (4) a channel stop using the first photoresist film or the silicon nitride film as a mask. Boron for
Ion implantation so that a peak concentration is formed inside the substrate; (5) thermal oxidation in an atmosphere containing oxygen to form an element isolation oxide film having a desired thickness; In the method of manufacturing a semiconductor device, which comprises a step of forming a diffusion layer and electrodes on an active region and providing necessary wiring, in the method (6), the final heat treatment of high temperature heat treatment exceeding 800 ° C. In the method of manufacturing a semiconductor device, the heat treatment is performed at the maximum temperature of the heat treatment in the (6) th step up to that point or higher. 2. The final heat treatment in the step (6) is performed by an RTP method.
The manufacturing method of the semiconductor device described in the above. 3. The final heat treatment in the (6) th step is an activation treatment of impurities introduced into the surface of the semiconductor substrate through the contact holes.
The manufacturing method of the semiconductor device described in the above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the final heat treatment in the step (6) is performed at a temperature of 1000 ° C. or higher.