JPH0338858A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a shallow junction and a high integration by a method wherein, after ions have been implanted into the side of a semiconductor substrate, a high-temperature and short-time annealing operation is executed to form a channel stopper layer and an isolation oxide film is formed. CONSTITUTION:When an oxide-film isolation region is formed, ions are implanted into the side of a semiconductor substrate 1 and, after that, a high- temperature and short-time annealing operation is executed to form a channel stopper layer 8; after that, an isolation oxide film 8 is formed. Consequently, crystal damage which is caused by an ion implantation operation and an I-OSF which is caused by this ion-implantation damage and which is produced by oxidation can be restored and suppressed by the high-temperature and short-time annealing operation; since the high-temperature and short-time annealing operation is executed before forming the isolation oxide film 9, the ion implantation damage as a generation source of the I-OSF can be almost restored. Thereby, it is possible to restrain the ion implantation oxidation-causing stacking fault(I-OSF) from being produced; a quality is enhanced by an action that the high- temperature and short-time annealing operation can realize a shallow junction and a high integration.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a method of manufacturing a semiconductor device. The present invention relates to a technique effective for use in a method of manufacturing a semiconductor device having an oxide film isolation region.

[Prior Art] In a semiconductor device including a bipolar transistor or the like, a channel stopper layer is formed by ion-implanting impurities of a conductivity type opposite to that of a buried diffusion layer under an isolation oxide film, and from this isolation oxide film and channel stopper layer. The oxide film isolation region prevents channel leakage current from flowing between elements.

An example of the process for forming this oxide film isolation region is as follows.

First, an epitaxial layer is grown on a semiconductor substrate, and the epitaxial layer on a region where a channel stopper layer is to be formed is recessed by selective etching. Then,
After implanting ions into the recesses of this epitaxial layer,
In a batch type electric furnace, furnace annealing is performed in an inert gas atmosphere such as N2 or Ar to diffuse implanted impurities from the epitaxial layer to the substrate (reach down).

Thereafter, an isolation oxide film is formed on the recessed portion of the epitaxial layer by selective oxidation or CVD to form an oxide film isolation region.

[Problems to be Solved by the Invention] Here, it is known that crystal damage occurs on the silicon substrate side where ion implantation has been performed.

In particular, when directly thermally oxidizing the damaged area to form an oxide film, interstitial silicon is implanted from the silicon oxide surface into the damaged area. (hereinafter referred to as ■-○SF) is likely to occur, and since this 1-○SF absorbs interstitial silicon during oxidation and grows into the device active region, leakage current increases and breakdown voltage deteriorates. This gives rise to the problem of

Furthermore, when forming a CVD film such as an HLD film on this damaged area, thermal stress caused by heat treatment at approximately 700°C during CVD and intrinsic stress generated at the interface between silicon and the deposited film may cause damage. In highly integrated devices, where secondary defects such as dislocations occur due to ion implantation damage, the distance between active elements becomes narrower.
There is a problem that secondary defects deteriorate device characteristics.

Therefore, in a semiconductor device equipped with an isoplanar oxide film isolation region that adopts the so-called reach-down method described above, when the isolation oxide film is formed of a thermal oxide film, the leakage current increases due to this I-〇SF. However, if the isolation oxide film is formed of a CVD film, there will be a problem that the device characteristics will deteriorate due to ion implantation damage.
It has been found that F or ion implantation damage can be suppressed or recovered by high-temperature heat treatment.

Therefore, in the past, heat treatment (furnace annealing in a batch type electric furnace; 1000°C,
At the same time (approximately 15 minutes), this ■-〇SF was suppressed and the ion implantation damage was recovered, but in order to perform annealing in a batch-type electric furnace, the temperature was raised,
The problem is that it takes time for the temperature to cool down.

As described above, when annealing takes a long time, the following problems occur.

In other words, the spread of the diffusion layer is simply calculated by texp -E kT (D is a constant, E is activation energy, k is Boltzmann's constant, and T is temperature), and the diffusion coefficient increases at high temperatures. Therefore, if the annealing temperature is increased to recover from damage as described above, the diffusion layer will expand unless the annealing time is shortened, resulting in problems such as shallow junctions and high integration. It will come to life.

As described above, in the above punch type furnace annealing, it takes time to raise and lower the temperature, making it difficult to achieve shallow bonding and high integration.

In order to suppress and recover from such problems, i.e. SF and ion implantation damage, high-temperature annealing using batch furnace annealing takes time and makes it difficult to achieve shallow bonding and high integration. The problem is as follows: 1) The device is equipped with an isoplanar oxide film isolation region using the reach-down method. i! The l-0
Although the generation of 8F can be suppressed to some extent, it also poses a problem in semiconductor devices equipped with isoplanar oxide film separation regions that adopt the so-called reach assembling method, where the diffusion width of the channel stopper layer becomes a problem. .

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device with improved quality.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in forming an oxide film isolation region consisting of an isolation oxide film and a channel stopper layer under the isolation oxide film, ions are implanted into the semiconductor substrate side, and then annealing is performed at high temperature for a short time to form channels 1 to brim layers. , and then an isolation oxide film is formed.

[Operation] According to the method described in 1, in forming the oxide film isolation region, after ion implantation into the semiconductor substrate side, high temperature and short time annealing is performed to form a channel stopper layer, and then the isolation oxide film is formed. As a result, the crystal damage caused by ion implantation and the knee SF generated by oxidation due to this ion implantation damage can be recovered and suppressed by annealing at high temperature and for a short time. Annealing is performed before forming the isolation oxide film, and ■○SF
Since the ion implantation damage, which is the source of SF, can be almost completely recovered, the generation of ■-〇SF can be almost suppressed.Furthermore, high-temperature, short-time annealing enables shallow bonding and high integration, which improves quality. Objective 1 of ``Improvement'' will be achieved.

[Embodiment 1] Hereinafter, embodiments of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

The first drawing shows a semiconductor device obtained by applying an embodiment of the method for manufacturing a semiconductor device according to the present invention.

The semiconductor device of this embodiment is a semiconductor device in which a bipolar transistor is formed, and in the semiconductor device of this embodiment, elements are isolated by an isoplanar type oxide film isolation region using a so-called reach-down method. There is.

The manufacturing process of the semiconductor device configured as described above will be explained as follows.

First, an n-type buried layer 2 is formed on the entire surface of a P-type semiconductor substrate 1, and then an epitaxial layer 3 is grown on the entire surface.
Thereafter, a 5in2 film 4 and a Si3N4 film 5 are sequentially laminated.

Next, the region of the n-type epitaxial layer 3 where the channel stopper layer is to be formed is covered with a thickness of 172 cm.
A thermal oxide film 7 having a thickness of 500 mm is selectively formed in this etched groove. Next, using the photoresist 6 as a mask, B4 ions are implanted in an amount of 5.times.10@13 an@-2 at an acceleration voltage of 50 KeV through the 500 .ANG. thick thermal oxide film 7, resulting in the state shown in FIG.

Next, the photoresist 6 is removed, and the wafer is subjected to lamp heating at 050°C for 15 seconds in an N2 atmosphere to diffuse the implanted impurities from the epitaxial layer 3 to the substrate 1 and to eliminate crystal damage caused by the ion implantation. l-08F generated by oxidation due to ion implantation damage
recovery and suppression.

The lamp annealing equipment used here is equipped with 15 halogen lamps on the top and bottom surfaces of a quartz chamber with a small heat capacity. Each wafer is placed between the halogen lamps, and the lamps are turned on. By doing this, the temperature is raised from 200°C to the holding temperature (1000°C to 1250°C) in about 15 seconds, and the holding temperature (in this example, the ion implantation amount is 5 x 1013 cm-2, so the temperature is 1050" C1) will be described later) for several tens of seconds (5 seconds in this example), and then heated to 500°C for about 20 seconds.
Annealing is performed by lowering the temperature in seconds.

Here, the present inventor confirmed the following through experiments.

That is, as shown in FIG. 4, the higher the annealing temperature, the better the recovery state of ion implantation damage caused by lamp heating.

Here, Fig. 4 shows B1 ions at an acceleration voltage of 50 KeV.
This is a diagram when X 10 '4an-2 is inserted,
The ion implantation damage was determined by measuring modulated light reflectance.

In the same figure, the vertical axis is the relative value of the thickness of the ion implantation damage, and the time when the damage value reaches 70 is τ, and the temperature dependence of the rate constant of damage recovery (戊−) is 2.8 eV. It was discovered that This value is close to the activation energy of 2.7 eV for solid phase epitaxial growth (SPE) of an ion-implanted amorphous layer. This is considered to be an amorphous cluster with discontinuous damage, and its recovery depends on the SPE of the cluster.
This shows that high temperature is advantageous.

In addition, the present inventors applied 100%
After performing DryO oxidation at 0°C for 60 minutes and Wet○2 oxidation at 1000°C for 46 minutes (atmospheric pressure 5 kg/cJ), the surface of 81 was etched by 5ecco and etched with an optics '41 mirror.
-08F was observed and its density was measured.

Figure 5 shows the results.

As shown in Fig. 5, the reduction effect of lamp heating on >O8F density is almost negligible when the lamp heating temperature is below 1050°C, but becomes obvious when the lamp heating temperature is above ]-100″C, and it is possible to reduce the density to 1200°C. It can be seen that the generation suppression temperature of l-08F increases as the amount of ion implantation increases;
In the case of X], O" mark -", and I X 10" (1) -2, the temperatures are 1.050°C and 1100°C, respectively.

As described above, in this example, since the heat treatment is a high temperature, short time annealing, crystal damage caused by ion implantation and oxidation due to this ion implantation damage (in this case, oxidation occurs during the formation of the isolation oxide film). The 1-03F generated by the 1-03F (1-0%) is well recovered and suppressed.

Furthermore, high temperature, short time annealing has the effect of making it possible to achieve shallow junctions and high integration of the semiconductor substrate.

Thereafter, an isolation oxide film 9 is formed on the groove portion of the epitaxial layer 3 by thermal oxidation to obtain the state shown in FIG. 3.

As described above, in this example, since high temperature, short-time annealing is performed before forming the isolation oxide film 9, the ion implantation damage that is the source of the 5 ■-〇SF can be generally recovered, and the ■-〇SF The occurrence of this can be largely suppressed.

After that, by implanting epitaxial M3 ions 1, a p-type base diffusion layer 12, an n-type emitter diffusion layer 11, and an n-type collector diffusion layer 3 are formed, respectively.
When base electrode B, emitter electrode E, and collector electrode C are formed in base diffusion layer 12, emitter diffusion layer 11, and collector diffusion layer 13, respectively, the semiconductor device shown in FIG. 1 is obtained.

Incidentally, in the upper penetration embodiment, a process is described in which the isolation oxide film 9 is formed by thermal oxidation, but this embodiment also applies when the isolation oxide film 9 is formed by a CVD film such as an HLD film. can be applied, and in that case, deterioration of device characteristics due to ion implantation damage as described above (described in the prior art) will be avoided.

Further, in this embodiment, in the above process, the selective etching step is omitted and an isolation oxide film is formed.
The present invention can be similarly applied to a semiconductor device having an OCO8 type oxide film separation region, a semiconductor device having an isoplanar type oxide film separation region employing a reach-up method, and the like. When applied to this reach 2-up type semiconductor device, its manufacture is performed in the following order: B+ ion implantation into the substrate 1 - lamp annealing under an NJJ atmosphere - formation selection of the epitaxial layer 3 and etholy selective oxidation. It turns out.

Thus, according to the method of manufacturing a semiconductor device of the above embodiment, the following effects can be obtained.

That is, when forming the oxide film isolation region consisting of the isolation oxide film 9 and the channel stopper N8 under the isolation oxide film 9, the semiconductor substrate side (reach-down method, LOCO 8
After ion implantation into the epitaxial layer 3 in the mold and into the semiconductor substrate 1 in the reach-up method,
Channel stopper N8 is formed by high-temperature, short-time annealing.
is formed, and then the isolation oxide film 9 is formed, so that the crystal damage caused by ion implantation and the 108F generated by oxidation due to this ion implantation damage can be recovered and suppressed by high-temperature, short-time annealing. This high temperature
Short-time annealing is performed before forming the isolation oxide film, and ■
-〇Since the ion implantation damage that is the source of SF generation can be largely recovered, the generation of l-08F can be almost suppressed,
Furthermore, high-temperature, short-time annealing makes it possible to achieve shallow junctions and high integration, making it possible to improve the quality of semiconductor devices.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the first embodiment, the high-temperature, short-time heat treatment is performed by lamp annealing, but heat treatment such as resistance heating, radio frequency heating (RF), etc. may be used instead.

Furthermore, in the above embodiments, high-temperature, short-time annealing in which the temperature is linearly increased to a high-temperature holding temperature is employed, but for example, after low-temperature annealing of 400'C to 800'C, the high-temperature annealing is performed. It is also possible to replace it with a heat treatment method in which the temperature is raised to a holding temperature.

Furthermore, in the above embodiment, an example of application to a semiconductor device using a p-type semiconductor substrate l is described;
It goes without saying that the present invention can be similarly applied to semiconductor devices using n-type semiconductor substrates.

Further, the present invention can also be applied to a manufacturing process of a semiconductor device including a MOS transistor or the like.

[Effects of the Invention j Effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in forming an oxide film isolation region consisting of an isolation oxide film and a channel stopper layer under the isolation oxide film, ions are implanted into the semiconductor substrate side and then annealing is performed at high temperature for a short time to form the channel stopper layer. ,
Since a separate oxide film is then formed, crystal damage caused by ion implantation and ■-〇SF generated by oxidation due to this ion implantation damage can be recovered and suppressed by high-temperature, short-time annealing. This high-temperature, short-time annealing is performed before forming the isolation oxide film, and the ion implantation damage that is the source of 51-○ SF can be largely recovered, so the generation of l-08F can be almost suppressed, and the high-temperature, short-time annealing is Time annealing makes it possible to achieve shallow junctions and high integration.

As a result, it becomes possible to improve quality.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of a semiconductor device obtained by applying an embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG.
The figure is a process diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention. Figure 4 is a relationship between the annealing time and the magnitude of ion implantation damage with the annealing temperature as a parameter. Figure 5 is a diagram with the annealing temperature as a parameter. FIG. 2 is a diagram showing the relationship between annealing time and 1-0 SF density. 1... Semiconductor substrate, 3... Epitaxial layer,
8...Channel stopper layer, 9...Isolation oxide film. 6 0 0q 390-

Claims (1)

[Claims] 1. In forming an oxide film isolation region consisting of an isolation oxide film and a channel stopper layer under the isolation oxide film, after ion implantation into the semiconductor substrate side, high temperature, short-time annealing is performed. 1. A method of manufacturing a semiconductor device, comprising forming a channel stopper layer and then forming an isolation oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the high-temperature, short-time annealing is lamp annealing. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the isolation oxide film is formed by a CVD method.