JPH087546B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to non-interlaced scanning by inputting image data of interlaced scanning and storing it in storage means, and then performing scan conversion. The present invention relates to a display method in an image processing device for displaying on a display.

2. Description of the Related Art Scan conversion is performed by inputting image data of interlaced scanning in a television, VTR, etc. and storing it in a storage means, and then reading out two signals vertically for each scanning line as shown in FIG. 4 (a). When outputting to a non-interlaced scanning display, the conventional display method is as shown in FIGS. 4 (b) and 4 (c).
The display started from the same position.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the display method as described above, as shown in FIG. 3A, a diagonal edge portion in interlaced scanning is scanned and converted by double reading, and then non-scanned. When output by interlaced scanning, Fig. 3 (b)
As shown in Figure 2, the double reading emphasizes the stepwise distortion in the diagonal direction, which significantly deteriorates the vertical resolution. In addition, both fields start displaying at the same position, and flicker occurs at the edge. Was conspicuous.

In view of such a point, the present invention provides an image processing apparatus that realizes a display in which deterioration of vertical resolution and flicker at an edge portion are not noticeable without using complicated processing such as interpolation at the time of interlace-non-interlace scan conversion. The purpose is to provide.

Means for Solving the Problems The present invention provides a first register for setting a vertical display start position in an odd field, a second register for setting a vertical display start position in an even field, and the above-mentioned first register. The selection circuit for selecting the first register and the second register based on the even / odd determination signal, and the counter circuit which is reset by the display vertical synchronizing signal and uses the display horizontal synchronizing signal as a clock, the input clock number is The image processing apparatus includes a first counter circuit that outputs a reset pulse signal when the value output from the selection circuit is reached.

Operation According to the present invention, by changing the values set in the first register and the second register by 1 according to the above-described configuration, the display start position in the vertical direction is shifted by one line for each field. As shown in FIG. 3 (c), the diagonal edge portion in the interlaced scanning as shown in a) is displayed as shown in FIG. 3 (c). Therefore, as compared with the conventional display method, the stepwise distortion is less noticeable and the vertical resolution is significantly increased. Flicker is also reduced.

Practical Example FIG. 1 is a block diagram of an image processing apparatus according to a first example of the present invention. In FIG. 1, 1
Is a first register for setting a vertical display start position in an odd field, 2 is a second register for setting a vertical display start position in an even field, and 3 is a first register 1 and a second register 2. Selection circuit 4 which selects the output of 1 based on the even-odd determination signal, 4 is a first counter circuit which outputs a pulse signal which becomes a low level when the count number reaches the value output from the selection circuit, 5
Is a third register for vertically setting the display period, 6
Is a second counter circuit that outputs a pulse signal that is at a low level for a period until the count number reaches the value set by the third register.

The operation of the image processing apparatus of this embodiment configured as described above will be described below.

Here, the preset value a is set in the first register 1, the preset value a + 1 is set in the second register 2,
The case where the preset value b is set in the third register 5 will be described as an example.

The selection circuit 3 receives the first register set value a and the second register set value a according to the even / odd determination signal S (FIG. 2A).
Since +1 is switched and output, the first counter circuit 4 is reset by the vertical synchronization signal V (FIG. 2B) and then the second counter circuit 4 is reset.
In the odd field, a low pulse is output when the count reaches a, and in an even field, a low pulse is output when the count reaches a + 1. The second counter circuit 6
After being reset by the output signal of the first counter circuit 4 (FIG. 2 (c)), a low pulse is output during the vertical display period b as shown in FIG. 2 (d).

As described above, according to the present embodiment, the display start is shifted by one line for each field. Therefore, when the display is performed as shown in FIG. 3C and the display position is not changed (FIG. 3). Compared to (b), since the stepwise distortion due to the double reading becomes inconspicuous, the vertical resolution is greatly improved and the flicker of the edge portion is also reduced.

As described above, according to the present invention, at the time of interlace-non-interlace scan conversion, the display start position can be shifted by one line for each field without using complicated processing such as interpolation. , The deterioration of the vertical resolution becomes inconspicuous, and the flicker of the edge part also decreases.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart of the same embodiment, FIG. 3 is an explanatory view of a display method of the same embodiment, and FIG. 4 is a conventional example. FIG. 3 is an explanatory diagram relating to a display method of the image processing apparatus of FIG. 1,2,5 …… Register, 3 …… Selection circuit, 4,6 …… Counter circuit.

Claims (1)

[Claims] 1. A first register for setting a vertical display start position in an odd field, a second register for setting a vertical display start position in an even field, the first register and the second register. A selection circuit for selecting the output signal of the register of 1 based on the even-odd determination signal;
A counter circuit that is reset by a display vertical synchronizing signal and uses the display horizontal synchronizing signal as a clock; and a first counter circuit that outputs a reset pulse signal when the number of clocks reaches a value output from the selection circuit. , A third register for setting a display period in the vertical direction, and a counter circuit reset by an output signal of the first counter circuit and having a horizontal synchronizing signal for display as a clock, and the number of clocks is set by the third register. And a second counter circuit that outputs a pulse signal for a period until reaching a certain value.