JPH0870017A - Double-sided substrate and electrode connection using both-sided substrate - Google Patents

Double-sided substrate and electrode connection using both-sided substrate

Info

Publication number
JPH0870017A
JPH0870017A JP6204838A JP20483894A JPH0870017A JP H0870017 A JPH0870017 A JP H0870017A JP 6204838 A JP6204838 A JP 6204838A JP 20483894 A JP20483894 A JP 20483894A JP H0870017 A JPH0870017 A JP H0870017A
Authority
JP
Japan
Prior art keywords
double
semiconductor device
sided
circuit pattern
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6204838A
Other languages
Japanese (ja)
Inventor
Hiroshi Saito
宏 齋藤
Tomohiro Inoue
智広 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP6204838A priority Critical patent/JPH0870017A/en
Publication of JPH0870017A publication Critical patent/JPH0870017A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To stabilize electrode connection quality of a both-sided substrate so as to improve its yield. CONSTITUTION: This both-sided substrate is provided with a metal plate which is a good heat-conducting body and a pre-preg 11 to be laminated on both surfaces of the metal plate 10 for forming a circuit pattern 12 on its surface while being,constituted that a projection part 10a of the metal plate 10 projects from an end face of the pre-preg 11. Thereby, heat for electrode connection can be efficiently supplied to an electrode pad of a semiconductor device 16, which is an electrode connection spot, and a circuit pattern 12 through the projection part 10a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置または電子
部品を搭載した両面基板の構造及びその両面基板を用い
た電極接続方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a double-sided board on which a semiconductor device or electronic parts are mounted and an electrode connecting method using the double-sided board.

【0002】[0002]

【従来の技術】両面基板の両面にベアチップ状の半導体
装置を実装した例を図7に基づいて説明する。図7は両
面基板を台座上に固定してワイヤボンディングによる電
極接続を行った状態を示す断面図である。図で、1は両
面基板、2は両面基板1の第1面(台座の上面に接して
いる側の面)に実装されたベアチップ状の半導体装置、
3は回路パターン、4はボンディングワイヤ、5は半導
体装置2を封止する封止コート、6は両面基板1の第2
面(第1面に対して反対側の面)に実装されたベアチッ
プ状の半導体装置、7はワイヤボンディング時に両面基
板1を支持するための台座、7aは台座7の上面に形成
された凹状の座ぐり部、8は両面基板1の表面に当接し
て両面基板1を台座7上に固定及び位置決めするための
押さえ治具である。
2. Description of the Related Art An example in which bare chip semiconductor devices are mounted on both sides of a double-sided substrate will be described with reference to FIG. FIG. 7 is a cross-sectional view showing a state in which the double-sided substrate is fixed on a pedestal and electrodes are connected by wire bonding. In the figure, 1 is a double-sided substrate, 2 is a bare chip-shaped semiconductor device mounted on the first surface of the double-sided substrate 1 (the surface on the side in contact with the upper surface of the pedestal),
3 is a circuit pattern, 4 is a bonding wire, 5 is a sealing coat for sealing the semiconductor device 2, 6 is a second side of the double-sided substrate 1.
A bare chip semiconductor device mounted on the surface (the surface opposite to the first surface), 7 is a pedestal for supporting the double-sided substrate 1 at the time of wire bonding, and 7a is a concave shape formed on the upper surface of the pedestal 7. The counterbore portion 8 is a holding jig for contacting the surface of the double-sided substrate 1 and fixing and positioning the double-sided substrate 1 on the pedestal 7.

【0003】従来、両面基板1の両面にベアチップ実装
(チップ・オン・ボード、COB)を行う場合におい
て、先ず、両面基板1の第1面に半導体装置2をダイボ
ンドし、ボンディングワイヤ4により、半導体装置2の
電極パッド(図示省略)と第1面の回路パターン3とを
電極接続した後、この半導体装置2の上にエポキシ等の
液状樹脂を注ぎ硬化させるポッティング法を用いて封止
する。次に、両面基板1の第1面を裏側に向け、第2面
に半導体装置6をダイボンドして電極接続を行ってい
た。ここで、ボンディングワイヤ4で電極接続する場
合、一般に金ワイヤを用い、超音波と熱圧着併用方式で
行っていた。ワイヤボンドを行う場合、接続箇所の温度
を予め高めておくが、温度を高めるのに必要な熱は、両
面基板1を支持する台座7から両面基板1に供給してい
た。台座7には熱源であるヒータブロック(図示省略)
が設けられている。
Conventionally, in the case where bare chip mounting (chip on board, COB) is performed on both surfaces of the double-sided substrate 1, first, the semiconductor device 2 is die-bonded to the first surface of the double-sided substrate 1, and the semiconductor is bonded by the bonding wire 4. After electrode connection between the electrode pad (not shown) of the device 2 and the circuit pattern 3 on the first surface, the semiconductor device 2 is sealed by a potting method in which a liquid resin such as epoxy is poured and cured. Next, the first surface of the double-sided substrate 1 was faced to the back side, and the semiconductor device 6 was die-bonded to the second surface for electrode connection. Here, when the electrodes are connected by the bonding wires 4, a gold wire is generally used, and the ultrasonic wave and thermocompression bonding are used together. When wire bonding is performed, the temperature of the connection point is raised in advance, but the heat necessary for raising the temperature is supplied to the double-sided substrate 1 from the pedestal 7 that supports the double-sided substrate 1. The pedestal 7 has a heater block (not shown) as a heat source.
Is provided.

【0004】両面基板1の第2面側でワイヤボンディン
グを行うために両面基板1の第1面側を下側にして両面
基板1を台座7上に配置した場合、半導体装置2の封止
コート5がグローブトップ状に盛り上がっているため、
台座7と封止コート5が接触しないよう凹状の座ぐり部
7aが形成されている。両面基板1の基材の材質として
は主にエポキシ、ポリイミド系の樹脂が用いられてい
た。
In order to perform wire bonding on the second surface side of the double-sided substrate 1, when the double-sided substrate 1 is placed on the pedestal 7 with the first surface side of the double-sided substrate 1 facing downward, the sealing coat of the semiconductor device 2 is formed. Since 5 is raised like a glove top,
A recessed spot facing portion 7a is formed so that the pedestal 7 and the sealing coat 5 do not come into contact with each other. As the material of the base material of the double-sided substrate 1, epoxy and polyimide resins have been mainly used.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
両面基板の両面への半導体装置のベアチップ実装は、以
上に説明したように行われていたため、第2面の半導体
装置の電極接続を行うための熱供給が困難であった。こ
れは、座グリ部7a内の空気層(隙間)により、熱の伝
導効率が悪く、台座7の座グリ部7a周辺の両面基板と
の接触面から両面基板1に熱が伝わり、その熱が半導体
装置6または半導体装置6と電極接続する回路パターン
3に伝わるというように、かなり遠回りの経路で熱が伝
わっていた。従って、半導体装置6または半導体装置6
と電極接続する回路パターン3の温度を所望の温度にま
で上昇させるために、熱源であるヒータブロックの設定
温度を高くして台座7に過剰な熱を加える必要があっ
た。しかし、台座7に過剰な熱を加えると、回路パター
ン3の剥離、または、両面基板1の反り等が発生すると
いう問題点があった。また、両面基板1の裏側の第1面
には半導体装置2の他に、電子部品(チップコンデン
サ、抵抗等)が半田により搭載されることがあるため、
半田に対して熱的ストレスが加わり、半田にクラック、
剥離等が発生する原因にもなっていた。さらに、当然な
がら、半田の融点は台座7の設定温度よりも数10度以上
高いものを選定しなければならなかったため、融点は低
いが接合強度が強く、かつ、ヒートサイクル性がよい共
晶半田(例えば、Pb37%Sw 等)が使えないという課題も
あった。
However, since the bare chip mounting of the semiconductor device on both sides of the conventional double-sided substrate has been performed as described above, it is necessary to connect the electrodes of the semiconductor device on the second side. Heat supply was difficult. This is because the heat conduction efficiency is poor due to the air layer (gap) in the spot facing portion 7a, and the heat is transferred to the double-sided substrate 1 from the contact surface of the pedestal 7 around the spot facing portion 7a with the double-sided substrate, and the heat is transferred. The heat was conducted in a considerably detoured route such as being conducted to the semiconductor device 6 or the circuit pattern 3 that is electrode-connected to the semiconductor device 6. Therefore, the semiconductor device 6 or the semiconductor device 6
In order to raise the temperature of the circuit pattern 3 connected to the electrode to a desired temperature, it is necessary to raise the set temperature of the heater block which is the heat source to apply excessive heat to the pedestal 7. However, if excessive heat is applied to the pedestal 7, there is a problem that the circuit pattern 3 is peeled off or the double-sided board 1 is warped. In addition to the semiconductor device 2, electronic components (chip capacitors, resistors, etc.) may be mounted by soldering on the first surface on the back side of the double-sided substrate 1,
Thermal stress is applied to the solder, cracking the solder,
It was also a cause of peeling and the like. Furthermore, as a matter of course, the melting point of the solder had to be selected to be higher than the set temperature of the pedestal by several tens of degrees, so that the eutectic solder has a low melting point but strong bonding strength and good heat cycle property. There was also a problem that (for example, Pb37% Sw) could not be used.

【0006】さらに、台座7の座グリ部7aでは、両面
基板1は台座7によって直接支持されていないため、ワ
イヤボンドにより半導体装置6の電極パッドと両面基板
1上の回路パターン3を超音波と熱圧着併用で接続しよ
うとすると、その超音波エネルギーが両面基板1のたわ
みまたは振動(バウンド等)により接合部に伝わらず、
電極接合品質が極めて悪いという問題点があった。
Further, in the spot facing portion 7a of the pedestal 7, since the double-sided substrate 1 is not directly supported by the pedestal 7, the electrode pad of the semiconductor device 6 and the circuit pattern 3 on the double-sided substrate 1 are ultrasonically bonded by wire bonding. When attempting to connect by thermocompression bonding, the ultrasonic energy is not transmitted to the joint portion due to the bending or vibration (boundary) of the double-sided substrate 1,
There is a problem that the electrode bonding quality is extremely poor.

【0007】本発明は上記問題点に鑑みなされたもの
で、その目的とするところは、第1面に半導体装置また
は電子部品を実装しその裏側の第2面に実装する半導体
装置の電極接続品質を安定化し、その歩留りの向上を図
ることにより、基板両面への低コストなベアチップ実装
を可能とし、これに伴って機器の小型化が図れる両面基
板の構造及びその両面基板を用いた電極接続方法を提供
することにある。
The present invention has been made in view of the above problems. An object of the present invention is to mount the semiconductor device or the electronic component on the first surface and the electrode connection quality of the semiconductor device mounted on the second surface on the back side thereof. Stable and improved yield, enabling low-cost bare-chip mounting on both sides of the substrate, which leads to downsizing of equipment and structure of double-sided board and electrode connection method using the double-sided board. To provide.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するた
め、請求項1記載の両面基板は、板状の良熱伝導体と、
その良熱伝導体の両面に積層され、その表面に回路パタ
ーンが形成される絶縁層とを備え、前記良熱伝導体の一
部が少なくとも一方の前記絶縁層の端面から突出してい
ることを特徴とするものである。
In order to achieve the above object, the double-sided board according to claim 1 is a plate-shaped good heat conductor,
An insulating layer laminated on both sides of the good thermal conductor and having a circuit pattern formed on the surface thereof, wherein a part of the good thermal conductor projects from an end face of at least one of the insulating layers. It is what

【0009】請求項2記載の両面基板は、板状の良熱伝
導体と、その良熱伝導体の両面に積層され、その表面に
回路パターンが形成される絶縁層とを備え、前記絶縁層
の少なくとも一方に、前記絶縁層の表面から裏面に達す
る貫通孔が形成されており、その貫通孔を介して前記良
熱伝導体が露出していることを特徴とするものである。
A double-sided board according to a second aspect comprises a plate-shaped good heat conductor and an insulating layer laminated on both surfaces of the good heat conductor and having a circuit pattern formed on the surface thereof. At least one of them has a through hole reaching from the front surface to the back surface of the insulating layer, and the good thermal conductor is exposed through the through hole.

【0010】請求項3記載の両面基板は、銅張積層板
と、その銅張積層板の両面に積層され、その表面に回路
パターンが形成される絶縁層とを備え、前記絶縁層の少
なくとも一方に、前記絶縁層の表面から裏面に達する貫
通孔が形成されており、その貫通孔を介して前記銅張積
層板の回路パターンが露出していることを特徴とするも
のである。
A double-sided board according to a third aspect of the present invention comprises a copper-clad laminate and an insulating layer laminated on both sides of the copper-clad laminate and having a circuit pattern formed on the surface thereof, and at least one of the insulating layers. Further, a through hole reaching from the front surface to the back surface of the insulating layer is formed, and the circuit pattern of the copper clad laminate is exposed through the through hole.

【0011】請求項4記載の両面基板は、請求項1また
は請求項2記載の両面基板で、前記絶縁層の少なくとも
一方に、前記絶縁層の表面から裏面に達する半導体装置
実装用貫通孔が形成されており、その半導体装置実装用
貫通孔の内部にてベアチップ状の半導体装置が前記良熱
伝導体に接合されていることを特徴とするものである。
A double-sided substrate according to a fourth aspect is the double-sided substrate according to the first or second aspect, in which at least one of the insulating layers has a through hole for mounting a semiconductor device that extends from the front surface to the back surface of the insulating layer. The bare chip semiconductor device is bonded to the good thermal conductor inside the through hole for mounting the semiconductor device.

【0012】請求項5記載の両面基板は、請求項3記載
の両面基板で、前記絶縁層の少なくとも一方に、前記絶
縁層の表面から裏面に達する半導体装置実装用貫通孔が
形成されており、その半導体装置実装用貫通孔の内部に
てベアチップ状の半導体装置が前記銅張積層板上に形成
された回路パターン上に接合されていることを特徴とす
るものである。
A double-sided board according to a fifth aspect is the double-sided board according to the third aspect, in which at least one of the insulating layers has a through hole for mounting a semiconductor device which extends from a front surface to a back surface of the insulating layer, In the semiconductor device mounting through hole, a bare chip-shaped semiconductor device is bonded onto a circuit pattern formed on the copper clad laminate.

【0013】請求項6記載の両面基板は、請求項1また
は請求項2または請求項4記載の両面基板で、前記良熱
伝導体の露出した部分を加熱して前記両面基板上に搭載
された半導体装置、その他電子部品の電極接続のための
熱供給を行うことを特徴とするものである。
The double-sided board according to claim 6 is the double-sided board according to claim 1, 2 or 4, wherein the exposed portion of the good thermal conductor is heated and mounted on the double-sided board. It is characterized in that heat is supplied for connecting electrodes of semiconductor devices and other electronic components.

【0014】請求項7記載の両面基板は、請求項3また
は請求項5記載の両面基板で、前記銅張積層板の露出し
た回路パターンを加熱して前記両面基板上に搭載された
半導体装置、その他電子部品の電極接続のための熱供給
を行うことを特徴とするものである。
The double-sided board according to claim 7 is the double-sided board according to claim 3 or 5, wherein the exposed circuit pattern of the copper-clad laminate is heated to be mounted on the double-sided board. Another feature is that heat is supplied to connect electrodes of other electronic components.

【0015】[0015]

【作用】本発明の両面基板は、両面基板の内層として金
属板等の良熱伝導体または銅張積層板を両面基板の内側
に挟み込んだことを特徴とするものである。これによ
り、第1面に既に半導体装置、電子部品等が実装された
両面基板の第2面に半導体装置を実装してワイヤボンド
等の電極接続を行う場合、そのワイヤボンドに必要な熱
供給は、内層の良熱伝導体または銅張積層板上に形成さ
れた回路パターンを外部熱源から加熱することにより行
うことができるようになるため、両面基板への過剰な加
熱が不要で、半導体装置、電子部品、両面基板等に与え
る熱的ストレスを著しく低減することができる。また、
内層として挟み込む(または埋め込む)良熱伝導体また
は銅張積層板の性質により機械的強度が格段に向上し曲
げに強くなるため、半導体装置の電極接続時の、両面基
板のたわみ、振動、反り等が極めて少なくなるので、安
定したワイヤボンディング等(加熱のみの熱圧着または
超音波印加のみの接合方法も含む)による電極接続が可
能となる。
The double-sided board of the present invention is characterized in that a good heat conductor such as a metal plate or a copper clad laminate is sandwiched inside the double-sided board as an inner layer of the double-sided board. Accordingly, when the semiconductor device is mounted on the second surface of the double-sided substrate on which the semiconductor device, the electronic component, etc. are already mounted on the first surface and electrode connection such as wire bonding is performed, the heat supply necessary for the wire bond is not generated. Since the circuit pattern formed on the good heat conductor of the inner layer or the copper clad laminate can be heated by the external heat source, excessive heating of the double-sided substrate is not required, and the semiconductor device, It is possible to significantly reduce the thermal stress applied to electronic components, double-sided boards and the like. Also,
Due to the properties of a good thermal conductor or copper clad laminate sandwiched (or embedded) as the inner layer, the mechanical strength is significantly improved and it becomes resistant to bending, so that the deflection, vibration, warpage, etc. of the double-sided board at the time of connecting the electrodes of the semiconductor device. Therefore, stable wire bonding or the like (including thermocompression bonding only by heating or a bonding method only by applying ultrasonic waves) is possible.

【0016】[0016]

【実施例】図1に基づいて本発明の両面基板の一実施例
について説明する。図1は両面基板を台座上に固定して
ワイヤボンディングを施した状態を示す断面図である。
図で、9は両面基板である。両面基板9は、板状の良熱
伝導体である金属板10と、その金属板10の両面に積
層された絶縁層であるプリプレグ11と、プリプレグ1
1の表面に形成された回路パターン12とで構成されて
いる。13は両面基板9の第1面に実装されたベアチッ
プ状の半導体装置、14はボンディングワイヤ、15は
半導体装置13及びボンディングワイヤ14を封止する
封止コート、16は両面基板9の第2面に実装されたベ
アチップ状の半導体装置、17はワイヤボンディング時
に両面基板9を支持するための台座、18は両面基板9
の表面に当接させて両面基板9を台座17上に固定及び
位置決めするための押さえ治具である。
EXAMPLE An example of the double-sided board of the present invention will be described with reference to FIG. FIG. 1 is a sectional view showing a state in which a double-sided substrate is fixed on a pedestal and wire bonding is performed.
In the figure, 9 is a double-sided substrate. The double-sided substrate 9 includes a metal plate 10 that is a plate-shaped good heat conductor, a prepreg 11 that is an insulating layer laminated on both surfaces of the metal plate 10, and a prepreg 1.
1 and the circuit pattern 12 formed on the surface thereof. Reference numeral 13 is a bare chip semiconductor device mounted on the first surface of the double-sided substrate 9, 14 is a bonding wire, 15 is a sealing coat for sealing the semiconductor device 13 and the bonding wire 14, and 16 is a second surface of the double-sided substrate 9. A bare chip semiconductor device mounted on the base 17; a pedestal 17 for supporting the double-sided substrate 9 during wire bonding;
Is a holding jig for fixing and positioning the double-sided substrate 9 on the pedestal 17 by abutting on the surface of the.

【0017】図1に示す両面基板9で、金属板10の一
部がプリプレグ11の端面から突出して突出部10aを
形成している。台座17には両面基板9の第1面を支持
するための凹状の基板支持部17aが形成されていると
共に、台座17と封止コート15との接触を防止するた
めの座ぐり部17bが基板支持部17aの底面に形成さ
れている。基板支持部17aは、両面基板9が台座17
上に配置された際に、基板支持部17aの底面に両面基
板9の第1面が接触すると共に台座17の表面が金属板
10に接触するようにその深さが設定されている。
In the double-sided board 9 shown in FIG. 1, a part of the metal plate 10 projects from the end face of the prepreg 11 to form a projecting portion 10a. The pedestal 17 is formed with a concave substrate supporting portion 17a for supporting the first surface of the double-sided substrate 9, and a counterbore portion 17b for preventing contact between the pedestal 17 and the sealing coat 15 is formed on the substrate. It is formed on the bottom surface of the support portion 17a. In the board supporting portion 17a, the double-sided board 9 is the pedestal 17
The depth is set so that the first surface of the double-sided substrate 9 comes into contact with the bottom surface of the substrate supporting portion 17a and the surface of the pedestal 17 comes into contact with the metal plate 10 when the upper surface is placed above.

【0018】金属板10は、一般的には、絶縁層となる
プリプレグ11との密着性を増すために、表面を粗面化
処理した、銅、Al、Fe,コバール等、または、黒色の酸
化第2銅の層を表面に形成した銅板等が用いられる。
The metal plate 10 is generally made of copper, Al, Fe, kovar, or black oxide whose surface is roughened in order to increase the adhesion with the prepreg 11 serving as an insulating layer. A copper plate or the like having a second copper layer formed on its surface is used.

【0019】両面基板9は、例えば、金属板10をプリ
プレグ11で挟んで加熱プレスをし成形される。ここ
で、両面基板9は、内層の金属板10の一部がプリプレ
グ11の端面から突出して突出部10aを形成するよう
に構成されている。図1に示す実施例では突出部10a
の箇所では金属板10の表裏両面が露出するように構成
されている。また、ここで、両面基板9の第1面に形成
された回路パターンと第2面に形成された回路パターン
とを接続するために、スルーホール(図示省略)を設け
る場合は、金属板10に予め、スルーホールを形成する
位置に切りかけ部または穴を開けておけばよく、金属板
10にプリプレグ11を積層した後、一般的なスルーホ
ール形成法である、穴埋め法(イングで穴を埋める方
法)またはテンチング法(ドライフィルムを用いる方
法)等で容易に形成できる。
The double-sided substrate 9 is formed, for example, by sandwiching a metal plate 10 between prepregs 11 and heating and pressing. Here, the double-sided board 9 is configured such that a part of the inner layer metal plate 10 projects from the end surface of the prepreg 11 to form a projecting portion 10 a. In the embodiment shown in FIG. 1, the protrusion 10a
At this location, both the front and back surfaces of the metal plate 10 are exposed. When a through hole (not shown) is provided to connect the circuit pattern formed on the first surface of the double-sided board 9 and the circuit pattern formed on the second surface, the metal plate 10 is provided. It suffices to make a cut portion or a hole at a position where a through hole is to be formed in advance. After laminating the prepreg 11 on the metal plate 10, a general through hole forming method (a method of filling a hole with ing). ) Or a tenting method (method using a dry film) or the like.

【0020】以上に示したように構成して、金属板10
の露出した突出部10aに、半導体装置またはその他の
電子部品の電極接続(ワイヤボンド、半田付け等)のた
めの熱供給を行うことによって、電極接続の接合部分に
効率よく熱を伝えることができるので、両面基板9また
は半田に熱ストレスを与えることなく、安定した電極接
続を行うことができる。また、融点は低いが接合強度が
強く、かつ、ヒートサイクル性がよい共晶半田(例え
ば、Pb37%Sw 等)を使用することができる。
The metal plate 10 is constructed as described above.
By supplying heat to the exposed protruding portion 10a for electrode connection (wire bond, soldering, etc.) of the semiconductor device or other electronic component, heat can be efficiently transmitted to the joint portion of the electrode connection. Therefore, stable electrode connection can be performed without applying thermal stress to the double-sided board 9 or the solder. Further, eutectic solder (for example, Pb37% Sw) having a low melting point but a high bonding strength and good heat cycle property can be used.

【0021】図2に基づいて本発明の両面基板の異なる
実施例について説明する。但し、図1に示した構成と同
等構成については同符号を付すこととする。図2に示す
実施例が、図1に示す実施例と異なる点は、金属板10
はプリプレグ19の端面から突出しておらず金属板10
の第1面側の面はプリプレグ19に覆われており、金属
板10はプリプレグ20の端面から突出して金属板10
の一部が第2面側にのみ露出しており、その露出した金
属板10の第2面側の面に、金属製の押さえ治具18が
接触している点と、台座21には凹状の基板支持部17
aが設けられておらず両面基板9の第1面は台座21の
表面に接触している点である。21aは座ぐり部であ
る。このように構成して押さえ治具18を介して金属板
10に熱を伝えることによって図1に示した実施例と同
様の効果を得ることができる。
A different embodiment of the double-sided board of the present invention will be described with reference to FIG. However, the same components as those shown in FIG. 1 are designated by the same reference numerals. The difference between the embodiment shown in FIG. 2 and the embodiment shown in FIG.
Does not project from the end surface of the prepreg 19 and is a metal plate 10.
The surface of the metal plate 10 on the first surface side is covered with the prepreg 19, and the metal plate 10 projects from the end surface of the prepreg 20.
Is partially exposed to the second surface side, and the exposed surface of the metal plate 10 on the second surface side is in contact with the metal holding jig 18, and the pedestal 21 has a concave shape. Substrate support 17
The point a is not provided, and the first surface of the double-sided substrate 9 is in contact with the surface of the pedestal 21. 21a is a spot facing portion. By thus configured and transmitting heat to the metal plate 10 via the pressing jig 18, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

【0022】図3に示す本発明の両面基板のさらに異な
る実施例は、図2に示した実施例とは逆に、両面基板9
の第1面側に金属板10の突出部10aの面が露出する
ように構成された両面基板9に電極接続を行う場合の構
成を示したものである。つまり、図3に示す実施例が、
図1に示す実施例と異なる点は、金属板10の第2面側
の面はプリプレグ22に覆われており、金属板10の突
出部10aの第1面側の面のみが露出して台座17の表
面に接触している点と、押さえ治具18が両面基板9の
第2面側の面に接触している点である。この場合、図1
に示した実施例と同様に台座17を介して金属板10に
熱を伝える。
A further different embodiment of the double-sided board of the present invention shown in FIG. 3 is the reverse of the embodiment shown in FIG.
2 shows a configuration in which an electrode is connected to the double-sided substrate 9 configured such that the surface of the protruding portion 10a of the metal plate 10 is exposed on the first surface side. That is, the embodiment shown in FIG.
The difference from the embodiment shown in FIG. 1 is that the surface on the second surface side of the metal plate 10 is covered with the prepreg 22, and only the surface on the first surface side of the protruding portion 10a of the metal plate 10 is exposed. 17 is in contact with the surface of the double-sided board 9, and the holding jig 18 is in contact with the surface of the double-sided board 9 on the second surface side. In this case,
Heat is transferred to the metal plate 10 via the pedestal 17 as in the embodiment shown in FIG.

【0023】図4に基づいて本発明の両面基板のさらに
異なる実施例について説明する。図4に示す実施例が、
図1に示す実施例と異なる点は、金属板10に突出部が
形成されていない点と、金属板10の第2面側に積層さ
れた、絶縁層であるプリクレグ23にそのプリクレグ2
3の表面から裏面に貫通する貫通孔23aが形成されて
いる点である。但し、貫通孔23aは実施例に限定され
ず第1面側のプリクレグにも形成されていてもよい。図
4に示すように構成することにより、金属板10の一部
が貫通孔23aの箇所で両面基板9の第2面側に露出す
るので、この貫通孔23a内部の露出した金属板10に
熱を加えることによって金属板10に熱を伝えることが
できる。金属板10から温めることにより両面基板9の
表面に形成された回路パターン12または半導体装置1
6に伝わる熱分布が均一になる。すなわち、両面基板9
の表面の温度差が小さくなり、安定した電極接続が可能
となる。
A different embodiment of the double-sided board of the present invention will be described with reference to FIG. The embodiment shown in FIG.
The difference from the embodiment shown in FIG. 1 is that the metal plate 10 is not provided with a protrusion, and that the prepreg 2 which is an insulating layer laminated on the second surface side of the metal plate 10 has the prepreg 2.
The point is that a through hole 23a is formed so as to penetrate from the front surface to the back surface of No. 3. However, the through hole 23a is not limited to the embodiment and may be formed in the prepreg on the first surface side. By configuring as shown in FIG. 4, a part of the metal plate 10 is exposed to the second surface side of the double-sided substrate 9 at the through hole 23a, so that the exposed metal plate 10 inside the through hole 23a is heated. The heat can be transferred to the metal plate 10 by adding. The circuit pattern 12 or the semiconductor device 1 formed on the surface of the double-sided substrate 9 by heating from the metal plate 10.
The heat distribution transferred to 6 becomes uniform. That is, the double-sided board 9
The temperature difference on the surface of the electrode becomes small, and stable electrode connection becomes possible.

【0024】図5に基づいて本発明の両面基板のさらに
異なる実施例を説明する。図5に示す実施例が、図4に
示した実施例と異なる点は、両面基板9の第2面側に絶
縁層として接着剤または樹脂等で貼り合わせた絶縁基板
24(ガラエポ、ポリイミド等の樹脂基板)に、半導体
装置16を収納するための貫通孔(半導体装置実装用貫
通孔24a)を形成すると共に、その半導体装置実装用
貫通孔24aの内部で、半導体装置16を金属板10に
ダイボンドしている点である。このように構成して貫通
孔24bを介して金属板10を加熱することによって半
導体装置16または回路パターン12に効率良く熱を伝
えることができるようになる。電極接続後に、加熱のた
めに用いた貫通孔24bを樹脂等で穴埋めした方が耐湿
性が良くなるが穴埋めしなくてもよい。図5に示したよ
うに半導体装置16を実装することによって、実装高さ
を低くできる。また、電極接続箇所である、半導体装置
16の電極パッド(図示省略)と回路パターン12との
高さの差が小さくなり、ボンディングワイヤ14のワイ
ヤループに無理な応力がかからなくなり、ワイヤボンド
の歩留りが良くなるという利点もある。
A different embodiment of the double-sided board of the present invention will be described with reference to FIG. The embodiment shown in FIG. 5 is different from the embodiment shown in FIG. 4 in that the insulating substrate 24 (glass epoxy, polyimide, etc.) bonded to the second surface side of the double-sided substrate 9 with an adhesive or a resin as an insulating layer. A through hole (semiconductor device mounting through hole 24a) for housing the semiconductor device 16 is formed in the resin substrate), and the semiconductor device 16 is die-bonded to the metal plate 10 inside the semiconductor device mounting through hole 24a. That is the point. By thus configuring and heating the metal plate 10 through the through hole 24b, heat can be efficiently transmitted to the semiconductor device 16 or the circuit pattern 12. After the electrodes are connected, it is better to fill the through holes 24b used for heating with a resin or the like to improve the moisture resistance, but it is not necessary to fill the holes. By mounting the semiconductor device 16 as shown in FIG. 5, the mounting height can be reduced. Further, the difference in height between the electrode pad (not shown) of the semiconductor device 16 and the circuit pattern 12, which is the electrode connection point, becomes small, and the wire loop of the bonding wire 14 is not subjected to excessive stress, so that wire bonding There is also an advantage that the yield is improved.

【0025】図6に基づいて本発明の両面基板のさらに
異なる実施例を説明する。図6に示す実施例は、両面基
板の内層として金属板10の替わりに銅張積層板25を
用い、加熱のための貫通孔26aを形成した絶縁基板2
6を銅張積層板25の第1面側に貼り合わせ、貫通孔2
7aを形成した絶縁基板27を銅張積層板25の第2面
側に貼り合わせ、貫通孔27aを介して内側の銅張積層
板25の第2面側に形成された回路パターン28を加熱
して絶縁基板27に熱を伝えるように構成された実施例
である。また、図示は省略するが、銅張積層板25上に
形成された回路パターン28と、貼り合わせた絶縁基板
26,27上に形成された回路パターン12とを接続す
る場合は、スルーホールまたはビアホール等で電気的に
接続すればよい。
A different embodiment of the double-sided board of the present invention will be described with reference to FIG. In the embodiment shown in FIG. 6, an insulating substrate 2 in which a copper clad laminate 25 is used as an inner layer of a double-sided substrate instead of the metal plate 10 and a through hole 26a for heating is formed
6 is attached to the first surface side of the copper clad laminate 25, and the through hole 2
The insulating substrate 27 having 7a formed thereon is attached to the second surface side of the copper clad laminate 25, and the circuit pattern 28 formed on the second surface side of the inner copper clad laminate 25 is heated through the through holes 27a. In this embodiment, the heat is transferred to the insulating substrate 27. Although illustration is omitted, in the case of connecting the circuit pattern 28 formed on the copper clad laminate 25 and the circuit pattern 12 formed on the insulating substrates 26 and 27 bonded together, through holes or via holes are used. It suffices to connect them electrically.

【0026】図6に示す実施例の場合、両面基板9の第
1面に実装した半導体装置13の電極接続を行う場合に
は、貫通孔26aに露出した銅張積層板25上の第1面
側に形成した回路パターン29を加熱して絶縁基板26
に熱を伝え、両面基板9の第2面側に実装した半導体装
置16の電極接続を行う場合には、貫通孔27aに露出
した銅張積層板25の第2面側に形成した回路パターン
28を加熱して絶縁基板27に熱を伝えるが、両面基板
9の内層として金属板を用いる場合よりも、両面基板9
の一方の面に加えた熱が他方の面に伝わりにくくなるの
で、他方の面への熱的な影響を小さくできるという利点
がある。
In the case of the embodiment shown in FIG. 6, when connecting the electrodes of the semiconductor device 13 mounted on the first surface of the double-sided board 9, the first surface of the copper clad laminate 25 exposed in the through hole 26a is exposed. Insulating substrate 26 by heating circuit pattern 29 formed on the side
When heat is transmitted to the semiconductor device 16 to connect the electrodes of the semiconductor device 16 mounted on the second surface side of the double-sided board 9, the circuit pattern 28 formed on the second surface side of the copper clad laminate 25 exposed in the through hole 27a. To transfer heat to the insulating substrate 27.
Since heat applied to one surface is less likely to be transferred to the other surface, there is an advantage that the thermal influence on the other surface can be reduced.

【0027】なお、良熱伝導体である金属板、または、
銅張積層板を加熱する方法は、金属板または銅張積層板
に、直接、伝熱部材を接触させて熱を伝える方法に限定
されず、光を用いた非接触の方法であるYAG レーザ、光
ビーム、赤外線加熱等の方法を用いてもよい、または、
接触方法のパルスヒート、ホットラム、パラレルギャッ
プ方法を用いてもよい。また、両面基板の形状、また
は、材質は実施例に限定されるものではない。さらに、
実施例では両面基板の第1面側に実装される半導体装置
には封止コートが施されていたが、赤外線検出素子また
は焦電素子等のセンサー素子のベアチップを基板に実装
する場合等、封止コートを施さない場合もあり実施例に
限定されるものではない。
A metal plate which is a good heat conductor, or
The method of heating the copper clad laminate is not limited to the method of transmitting heat by directly contacting the heat transfer member with the metal plate or the copper clad laminate, and is a non-contact method using light YAG laser, A method such as light beam or infrared heating may be used, or
The contact method such as pulse heating, hot ram, or parallel gap method may be used. Further, the shape or material of the double-sided substrate is not limited to the embodiment. further,
In the embodiment, the semiconductor device mounted on the first surface side of the double-sided board is provided with the sealing coat. However, when the bare chip of the sensor element such as the infrared detection element or the pyroelectric element is mounted on the board, it is sealed. In some cases, a stop coat may not be applied, which is not limited to the examples.

【0028】[0028]

【発明の効果】請求項1乃至請求項5記載の両面基板、
または、請求項6または請求項7記載の電極接続方法に
よれば、両面基板の所望の位置にベアチップ状の半導体
装置または電子部品を実装でき、半導体装置等の電極接
続品質が安定化し歩留りが向上する。また、電極接続を
しようとする半導体装置または電子部品が搭載されてい
る面の反対側の面に搭載されている半導体装置、その
他、半田付けで搭載されている電子部品等の接続部に与
える熱的ストレスを極めて低減することができ、封止コ
ートの封止樹脂または半田材料等の劣化によるクラック
または剥離、ワイヤボンド接合部の金属(主にAu)拡散
( 150℃以上で顕著になる)による強度劣化等の不良発
生を防止できる効果がある。従って、基板両面への低コ
ストのベアチップ実装が可能となり、これに伴って機器
の高密度化、小型化も図れるという効果が期待できる。
The double-sided substrate according to any one of claims 1 to 5,
Alternatively, according to the electrode connecting method of claim 6 or 7, a bare chip-shaped semiconductor device or electronic component can be mounted at a desired position on the double-sided substrate, the electrode connection quality of the semiconductor device or the like is stabilized, and the yield is improved. To do. In addition, heat applied to the connection part of the semiconductor device or the semiconductor device mounted on the surface opposite to the surface on which the electronic component is mounted, or the other electronic component mounted by soldering. Stress can be extremely reduced, due to cracking or peeling due to deterioration of the sealing resin or solder material of the sealing coat, and diffusion of metal (mainly Au) in the wire bond joint (prominent at 150 ° C or higher) This has the effect of preventing the occurrence of defects such as strength deterioration. Therefore, it is possible to mount a low-cost bare chip on both surfaces of the substrate, and it is expected that the density and size of the device can be increased accordingly.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の両面基板の一実施例を示す断面図であ
る。
FIG. 1 is a sectional view showing an embodiment of a double-sided board of the present invention.

【図2】本発明の両面基板の異なる実施例を示す断面図
である。
FIG. 2 is a cross-sectional view showing another embodiment of the double-sided board of the present invention.

【図3】本発明の両面基板のさらに異なる実施例を示す
断面図である。
FIG. 3 is a sectional view showing still another embodiment of the double-sided board of the present invention.

【図4】本発明の両面基板のさらに異なる実施例を示す
断面図である。
FIG. 4 is a sectional view showing still another embodiment of the double-sided board of the present invention.

【図5】本発明の両面基板のさらに異なる実施例を示す
断面図である。
FIG. 5 is a sectional view showing still another embodiment of the double-sided board of the present invention.

【図6】本発明の両面基板のさらに異なる実施例を示す
断面図である。
FIG. 6 is a sectional view showing still another embodiment of the double-sided board of the present invention.

【図7】従来の両面基板の一例を示す断面図である。FIG. 7 is a cross-sectional view showing an example of a conventional double-sided board.

【符号の説明】[Explanation of symbols]

9 両面基板 10 金属板(良熱伝
導体) 11,19,20,22,23,24 プリプレグ(絶
縁層) 12 回路パターン 13,16 半導体装置 23a,24b,26a,27a 貫通孔 24a 半導体装置実装
用貫通孔 25 銅張積層板 26,27 絶縁基板(絶縁
層) 28,29 回路パターン
9 Double-sided substrate 10 Metal plate (good thermal conductor) 11, 19, 20, 22, 23, 24 Prepreg (insulating layer) 12 Circuit pattern 13, 16 Semiconductor device 23a, 24b, 26a, 27a Through hole 24a For mounting semiconductor device Through hole 25 Copper clad laminate 26,27 Insulating substrate (insulating layer) 28,29 Circuit pattern

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 板状の良熱伝導体と、その良熱伝導体の
両面に積層され、その表面に回路パターンが形成される
絶縁層とを備え、前記良熱伝導体の一部が少なくとも一
方の前記絶縁層の端面から突出していることを特徴とす
る両面基板。
1. A plate-shaped good heat conductor, and an insulating layer laminated on both surfaces of the good heat conductor and having a circuit pattern formed on the surface thereof. At least a part of the good heat conductor is provided. A double-sided board, characterized in that it projects from an end face of one of the insulating layers.
【請求項2】 板状の良熱伝導体と、その良熱伝導体の
両面に積層され、その表面に回路パターンが形成される
絶縁層とを備え、前記絶縁層の少なくとも一方に、前記
絶縁層の表面から裏面に達する貫通孔が形成されてお
り、その貫通孔を介して前記良熱伝導体が露出している
ことを特徴とする両面基板。
2. A plate-shaped good heat conductor, and an insulating layer laminated on both surfaces of the good heat conductor and having a circuit pattern formed on the surface thereof, wherein at least one of the insulating layers has the insulating layer. A double-sided board, wherein a through hole reaching from the front surface to the back surface of the layer is formed, and the good thermal conductor is exposed through the through hole.
【請求項3】 銅張積層板と、その銅張積層板の両面に
積層され、その表面に回路パターンが形成される絶縁層
とを備え、前記絶縁層の少なくとも一方に、前記絶縁層
の表面から裏面に達する貫通孔が形成されており、その
貫通孔を介して前記銅張積層板の回路パターンが露出し
ていることを特徴とする両面基板。
3. A copper-clad laminate, and an insulating layer laminated on both surfaces of the copper-clad laminate and having a circuit pattern formed on the surface thereof. At least one of the insulating layers has a surface of the insulating layer. A double-sided board characterized in that a through hole reaching the back surface is formed, and the circuit pattern of the copper clad laminate is exposed through the through hole.
【請求項4】 前記絶縁層の少なくとも一方に、前記絶
縁層の表面から裏面に達する半導体装置実装用貫通孔が
形成されており、その半導体装置実装用貫通孔の内部に
てベアチップ状の半導体装置が前記良熱伝導体に接合さ
れていることを特徴とする請求項1または請求項2記載
の両面基板。
4. A through-hole for mounting a semiconductor device, which reaches from a front surface to a back surface of the insulating layer, is formed in at least one of the insulating layers, and a semiconductor device having a bare chip shape inside the through-hole for mounting the semiconductor device. The double-sided board according to claim 1 or 2, wherein is bonded to the good thermal conductor.
【請求項5】 前記絶縁層の少なくとも一方に、前記絶
縁層の表面から裏面に達する半導体装置実装用貫通孔が
形成されており、その半導体装置実装用貫通孔の内部に
てベアチップ状の半導体装置が前記銅張積層板上に形成
された回路パターン上に接合されていることを特徴とす
る請求項3記載の両面基板。
5. A semiconductor device mounting through-hole that extends from the front surface to the back surface of the insulating layer is formed in at least one of the insulating layers, and a bare chip-shaped semiconductor device is provided inside the semiconductor device mounting through-hole. The double-sided board according to claim 3, wherein is bonded on a circuit pattern formed on the copper-clad laminate.
【請求項6】 前記良熱伝導体の露出した部分を加熱し
て前記両面基板上に搭載された半導体装置、その他電子
部品の電極接続のための熱供給を行うことを特徴とす
る、請求項1または請求項2または請求項4記載の両面
基板を用いた電極接続方法。
6. The heat supply for heating an exposed portion of the good thermal conductor to connect electrodes of a semiconductor device mounted on the double-sided substrate and other electronic components. An electrode connecting method using the double-sided substrate according to claim 1 or claim 2 or claim 4.
【請求項7】 前記銅張積層板の露出した回路パターン
を加熱して前記両面基板上に搭載された半導体装置、そ
の他電子部品の電極接続のための熱供給を行うことを特
徴とする、請求項3または請求項5記載の両面基板を用
いた電極接続方法。
7. The exposed circuit pattern of the copper clad laminate is heated to supply heat for connecting electrodes of a semiconductor device mounted on the double-sided substrate and other electronic components. An electrode connecting method using the double-sided substrate according to claim 3 or 5.
JP6204838A 1994-08-30 1994-08-30 Double-sided substrate and electrode connection using both-sided substrate Withdrawn JPH0870017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6204838A JPH0870017A (en) 1994-08-30 1994-08-30 Double-sided substrate and electrode connection using both-sided substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6204838A JPH0870017A (en) 1994-08-30 1994-08-30 Double-sided substrate and electrode connection using both-sided substrate

Publications (1)

Publication Number Publication Date
JPH0870017A true JPH0870017A (en) 1996-03-12

Family

ID=16497232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6204838A Withdrawn JPH0870017A (en) 1994-08-30 1994-08-30 Double-sided substrate and electrode connection using both-sided substrate

Country Status (1)

Country Link
JP (1) JPH0870017A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020017561A (en) * 2018-07-23 2020-01-30 キヤノン株式会社 Module and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020017561A (en) * 2018-07-23 2020-01-30 キヤノン株式会社 Module and manufacturing method thereof

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Effective date: 20011106