JPH0897355A - Hybrid integrated circuit device and manufacture - Google Patents

Hybrid integrated circuit device and manufacture

Info

Publication number
JPH0897355A
JPH0897355A JP23345794A JP23345794A JPH0897355A JP H0897355 A JPH0897355 A JP H0897355A JP 23345794 A JP23345794 A JP 23345794A JP 23345794 A JP23345794 A JP 23345794A JP H0897355 A JPH0897355 A JP H0897355A
Authority
JP
Japan
Prior art keywords
substrate
insulating substrate
conductive
semiconductor element
metal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23345794A
Other languages
Japanese (ja)
Inventor
Susumu Ota
晋 太田
Yuusuke Igarashi
優助 五十嵐
Toshiaki Ikeda
年明 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP23345794A priority Critical patent/JPH0897355A/en
Publication of JPH0897355A publication Critical patent/JPH0897355A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE: To improve reliability of the fixing portion, on the occasion of obtaining a multilayer substrate by bonding an insulating substrate on a metal substrate, by controlling influence of semiconductor elements and parts of both substrates as much as possible without allowing re-fusion of hardended solder on the insulating substrate for soldering on the metal substrate. CONSTITUTION: A semiconductor element 35 for a high amplitude signal is mounted on a metal substrate 30 and an insulating substrate 38 is mounted in the region corresponding to a removed area 44. Moreover, a fixing part 45 is also provided at the superimposed area and this fixed area is also fused simultaneously with fusing of solder on the metal surface 30.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、混成集積回路装置およ
びその製造方法に関し、特に多層基板にして実装密度を
向上させるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device and a method of manufacturing the same, and more particularly to a multi-layer substrate to improve the packaging density.

【0002】[0002]

【従来の技術】第3図および第4図を参照しながら従来
の構造について説明する。一般に多層基板構造は、例え
ば特願平2−201219号(H05K 3/36)に
説明されており、下層の基板10の上に例えばプリント
基板11が実装され多層基板となるものである。第1の
基板10には、導電路12や導電ランド13が形成さ
れ、この上にはチップ抵抗14や半導体素子15が半田
を介して電気的に接続されている。またプリント基板1
1は、やはり導電路16や図では省略したが導電ランド
にチップ抵抗や半導体素子が半田を介して接続されてい
る。
2. Description of the Related Art A conventional structure will be described with reference to FIGS. Generally, a multilayer substrate structure is described in, for example, Japanese Patent Application No. 2-201219 (H05K 3/36), and a printed circuit board 11 is mounted on the lower substrate 10 to form a multilayer substrate. Conductive paths 12 and conductive lands 13 are formed on the first substrate 10, and chip resistors 14 and semiconductor elements 15 are electrically connected thereto via solder. Printed circuit board 1
1, a chip resistor or a semiconductor element is connected to a conductive land 16 or a conductive land through solder, which is also omitted in the drawing.

【0003】またプリント基板11は、下層の基板10
と接着されるため裏面に実装することは一般的ではな
い。
The printed circuit board 11 is a lower layer substrate 10.
Since it is adhered to, it is not common to mount it on the back surface.

【0004】[0004]

【発明が解決しようとする課題】一般に下層の基板10
もプリント基板11も半田を介して半導体素子や部品が
固着されているものがある。特にプリント基板11は、
半導体素子や部品が実装されて供給され、これを下層の
基板10に接着してから、下層の基板10に半導体素子
15等を半田で固着しようとすると、半田に加えられる
熱が下層の基板を介してプリント基板にも加えられるた
めに、プリント基板の半田固着部が再度溶融し劣化等の
問題を起こす原因となった。特に下層の基板が金属基板
であると、熱伝導が良いため、より深刻である。
Generally, the lower substrate 10 is used.
There are some printed circuit boards 11 to which semiconductor elements and parts are fixed via solder. In particular, the printed circuit board 11
When semiconductor elements and parts are mounted and supplied, and the semiconductor elements 15 and the like are soldered to the lower layer substrate 10 after being bonded to the lower layer substrate 10, the heat applied to the solder causes the lower layer substrate to move. Since it is added to the printed circuit board through the solder, the solder-bonded portion of the printed circuit board is melted again and causes a problem such as deterioration. In particular, when the lower substrate is a metal substrate, the heat conduction is good, which is more serious.

【0005】一方、プリント基板11と下層の基板10
は、接着剤を介して固着されるため、2枚の基板の熱膨
張係数の違いにより基板が反ったり、剥がれたりする問
題があった。
On the other hand, the printed circuit board 11 and the lower substrate 10
However, since they are fixed via an adhesive, there is a problem that the substrates warp or peel off due to the difference in thermal expansion coefficient between the two substrates.

【0006】[0006]

【課題を解決するための手段】本発明は前述した課題に
鑑みて成され、第1に、絶縁性基板下層の金属基板の少
なくとも一部がくり抜かれ、このくり抜き領域に対応す
る前記絶縁性基板の表面および/または裏面に前記第2
半導体素子および/または第2部品を実装する事で解決
するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. First, at least a part of a metal substrate under an insulating substrate is hollowed out, and the insulating substrate corresponding to the hollowed-out region is formed. On the front surface and / or the back surface of the second
This is solved by mounting a semiconductor element and / or a second component.

【0007】第2に、金属基板のくり抜き部に半導体素
子および/または部品が固着された絶縁性基板を実装し
た後、この金属基板の導電路および/または導電ランド
に半田を介して半導体素子を固着することで解決するも
のである。第3に、金属基板に絶縁性基板をのせ、この
金属基板の導電路および/または導電ランドに半田を介
して半導体素子を固着する工程と同時に、前記絶縁性基
板と前記金属基板が当接した領域の半田を介して固定す
ることで解決するものである。
Secondly, after mounting an insulating substrate having a semiconductor element and / or components fixed to the hollowed-out portion of the metal substrate, the semiconductor element is mounted on the conductive path and / or the conductive land of the metal substrate via solder. The solution is to fix it. Thirdly, at the same time as the step of placing the insulating substrate on the metal substrate and fixing the semiconductor element to the conductive path and / or the conductive land of the metal substrate via the solder, the insulating substrate and the metal substrate are brought into contact with each other. This is solved by fixing the solder in the area.

【0008】[0008]

【作用】第1に、絶縁性基板の実装予定領域に対応する
金属基板にくり抜き部を設けることで、、そこには空間
が設けられる。従って、絶縁性基板は直接熱源(例えば
ヒーター)に当接しないために、絶縁性基板の固着部に
設けられた半田は、融点に到達せず、溶融することがな
い。また大信号用の半導体素子を金属基板に、また絶縁
性基板上に発熱の少ない小信号用の素子を実装すれば、
くり抜き部があるため、絶縁性基板に大信号用の素子の
熱が伝わらず、同時にこの素子は金属基板に実装されて
いるために、金属基板を介して外部に放熱ができる。
In the first place, a hollow is provided in the metal substrate corresponding to the intended mounting area of the insulating substrate, whereby a space is provided therein. Therefore, since the insulating substrate does not directly contact the heat source (for example, the heater), the solder provided on the fixed portion of the insulating substrate does not reach the melting point and does not melt. Also, if a large signal semiconductor element is mounted on a metal substrate and an element for small signal with less heat generation is mounted on an insulating substrate,
Due to the hollow portion, the heat of the large signal element is not transmitted to the insulating substrate, and at the same time, since this element is mounted on the metal substrate, heat can be radiated to the outside through the metal substrate.

【0009】第2に、前記くり抜き部を設けることで、
金属基板に前記絶縁性基板を固着した後、金属基板の半
田を溶融することで、絶縁性基板の半田を再度溶かすこ
となく金属基板の素子を固着できる。第3に、金属基板
と当接した絶縁性基板の領域、つまりくり抜き部の周辺
は、熱源からの熱を絶縁性基板に良好に伝えることがで
きるため、金属基板の半田溶融工程と同時に2枚の基板
を固着できる。従って、接着剤による2枚の基板の固定
と併用すれば、接着強度が増す。また接着剤を併用しな
くとも、くり抜き部が有るために、2枚の基板の間に生
ずる歪みが従来よりも少ないために反りやはがれを防止
できる。
Secondly, by providing the hollow portion,
By fixing the insulating substrate to the metal substrate and then melting the solder of the metal substrate, the elements of the metal substrate can be fixed without melting the solder of the insulating substrate again. Thirdly, since the heat from the heat source can be satisfactorily transferred to the insulating substrate in the region of the insulating substrate that is in contact with the metal substrate, that is, in the periphery of the cut-out portion, two sheets are formed simultaneously with the solder melting process of the metal substrate. The substrate can be fixed. Therefore, when used in combination with the fixing of the two substrates with the adhesive, the adhesive strength is increased. Further, even if an adhesive is not used together, since there is a cutout portion, the distortion generated between the two substrates is smaller than in the conventional case, so that warpage and peeling can be prevented.

【0010】[0010]

【実施例】以下に本発明の実施例を図1および図2を参
照しながら説明する。図1は、実施例の平面図であり、
まず金属基板30があり、その上には導電路31や導電
ランド32が貼着されている。この金属基板30は、A
l基板から成りその表面には酸化膜33が形成されてい
る。この酸化膜は、陽極酸化により両表面がアルマイト
処理されて生成されているが、熱酸化でも良いし、デポ
ジッションで達成しても良い。また少なくとも一主面に
エポキシ樹脂あるいはポリイミド樹脂等の接着性を有す
る絶縁樹脂34が被覆され、前記導電路31がホットプ
レスにより貼着されている。導電路31は、Cuで成
り、全面に貼着した後、塩化第2鉄等の溶液でエッチン
グされてパターニングされている。導電ランド32は、
ベアチップ状の第1半導体素子35等を固着するエリア
で、ここでは大信号用の発熱素子が実装されるために、
チップ35の下層にはCu等のヒートシンク36が半田
等を介して固着されており、導電路と一体であったり、
アイランド状になっている。半導体素子35は、ICチ
ップやLSIチップでも良いが、図はパワートランジス
タであり、表面のベース電極やエミッタ電極は、金属細
線により、配線の一部と一体のパッドにワイヤーボンデ
ィングされている。更には、チップ抵抗やチップコンデ
ンサ等の第1部品37が導電路に半田を介して接続され
ている。
Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a plan view of the embodiment,
First, there is a metal substrate 30, on which conductive paths 31 and conductive lands 32 are attached. This metal substrate 30 is A
An oxide film 33 is formed on the surface of the substrate 1. Although this oxide film is formed by anodizing both surfaces by anodic oxidation, it may be formed by thermal oxidation or may be formed by deposition. Further, at least one main surface is covered with an insulating resin 34 having an adhesive property such as an epoxy resin or a polyimide resin, and the conductive path 31 is attached by hot pressing. The conductive path 31 is made of Cu, and is adhered to the entire surface and then etched and patterned with a solution of ferric chloride or the like. The conductive land 32 is
In the area where the bare chip-shaped first semiconductor element 35 and the like are fixed, since a large-signal heating element is mounted here,
A heat sink 36 of Cu or the like is fixed to the lower layer of the chip 35 via solder or the like, and is integrated with the conductive path,
It looks like an island. Although the semiconductor element 35 may be an IC chip or an LSI chip, it is a power transistor in the figure, and the base electrode and the emitter electrode on the surface are wire-bonded by metal thin wires to a pad integrated with a part of the wiring. Furthermore, a first component 37 such as a chip resistor or a chip capacitor is connected to the conductive path via solder.

【0011】一方、両面実装用の絶縁性基板38があ
り、ここでは例えばガラスエポキシ、紙エポキシ、紙フ
ェノールおよびポリイミド等の材料より成る、いわゆる
プリント基板がある。ただしシート状のフレキシブル基
板でも良い。この絶縁性基板38には、前述した金属基
板と同様に第2導電路39や第2導電ランド40が設け
られ、第2導電路には第2部品や第2半導体素子が、第
2導電ランド40には、トランジスタ等の第2半導体素
子が半田等を介して固着されている。当然両面実装であ
るために、上述の構成がスルーホールを介して絶縁性基
板38の裏面にも形成されている。
On the other hand, there is an insulating substrate 38 for double-sided mounting, and here, there is a so-called printed circuit board made of materials such as glass epoxy, paper epoxy, paper phenol and polyimide. However, a sheet-shaped flexible substrate may be used. The insulating substrate 38 is provided with the second conductive paths 39 and the second conductive lands 40 similarly to the above-described metal substrate, and the second component and the second semiconductor element are connected to the second conductive lands in the second conductive paths. A second semiconductor element such as a transistor is fixed to 40 via solder or the like. Since it is of course double-sided mounting, the above-mentioned structure is also formed on the back surface of the insulating substrate 38 via the through holes.

【0012】ここで金属基板30と絶縁性基板38の回
路の電気的コンタクトは、41,42,43に示す3例
等により実現されている。41は、両基板の境界にボン
ディングパッドが延在され、金属細線により実現されて
いる。またボンデイングは加圧されるため、くり抜き部
ではなく両基板の重畳部に一方の電極が設けられること
が好ましい。42は、両境界に電極が近接され、両者が
半田により電気的に接続されている。とくにこの接続さ
れる電極は重畳部である必要はないが、近接した方が半
田が2つの間にまたぎ易いので重畳部にあった方がよ
い。更には43は、金属基板30の配線が、絶縁性基板
38の重畳部下層にまで延在され、この上にある配線か
ら延在された電極とが、丸印で示したスルーホールを介
して半田により電気的に接続されている。従って金属基
板と絶縁性基板の回路が電気的に接続され所望のIC回
路が達成されている。
Here, the electrical contact between the circuit of the metal substrate 30 and the insulating substrate 38 is realized by the three examples shown by 41, 42 and 43. 41 has a bonding pad extending at the boundary between both substrates and is realized by a thin metal wire. Further, since the bonding is pressurized, it is preferable that one electrode is provided not on the cutout portion but on the overlapping portion of both substrates. The electrode of 42 is close to both boundaries, and both are electrically connected by soldering. In particular, the electrode to be connected does not need to be the overlapping portion, but it is better to be in the overlapping portion because the solder is more likely to straddle between the two when the electrodes are close to each other. Further, in 43, the wiring of the metal substrate 30 extends to a lower layer of the overlapping portion of the insulating substrate 38, and the electrode extending from the wiring thereabove through a through hole indicated by a circle. It is electrically connected by solder. Therefore, the circuit of the metal substrate and the circuit of the insulating substrate are electrically connected to achieve a desired IC circuit.

【0013】本発明の特徴は、絶縁性基板38に示した
点線のくり抜き部44で、これは絶縁性基板周辺が金属
基板30と重畳し、それ以外は金属基板と当接しないよ
うに、金属基板に設けられている。従って、絶縁性基板
38の裏面にも厚みのある部品や半導体素子が実装で
き、しかも点線領域の金属基板30と絶縁性基板38は
接着剤等で固着されていないために、熱膨張係数の違い
による基板間の歪みや素子や部品へ加わる応力を減少さ
せることができる。
A feature of the present invention is a hollowed-out portion 44 of the dotted line shown in the insulating substrate 38, which is formed so that the periphery of the insulating substrate overlaps with the metal substrate 30 and does not contact the other metal substrate. It is provided on the substrate. Therefore, a thick component or a semiconductor element can be mounted on the back surface of the insulating substrate 38, and the metal substrate 30 and the insulating substrate 38 in the dotted line region are not fixed to each other with an adhesive or the like. It is possible to reduce the strain between the substrates and the stress applied to the element or component due to the.

【0014】また金属基板30には、大信号用の発熱素
子が、絶縁性基板上には小信号用の発熱が少ない素子を
実装すれば、大信号用の素子からの熱は、くり抜き部が
あるため絶縁性基板に伝わりにくく、また金属基板30
上に実装されるために、大信号素子からの熱を放熱させ
ることができ、絶縁性基板、これに実装される素子や部
品への熱的影響を最小限にくい止めることができる。
If a large-signal heat generating element is mounted on the metal substrate 30 and a small-signal heat generating element is mounted on the insulating substrate, the heat from the large-signal element is cut out. Since it is present, it is difficult to reach the insulating substrate, and the metal substrate 30
Since it is mounted on top, heat from the large-signal element can be dissipated, and the thermal influence on the insulating substrate and the elements and components mounted on it can be minimized.

【0015】後述するが前もって絶縁性基板38の両面
に半田を介して第2部品と第2半導体素子が固着された
ものを用意し、これを金属基板30に固着してから金属
基板の第1部品や第1半導体素子を半田を介して固着す
る場合、例えば熱源として基板の下層に当てられるヒー
ターで半田を溶融すると、くり抜き部44が有るために
絶縁性基板38は、直接熱源から加熱されないため、温
度上昇にタイムラグを有する。従って金属基板上の半田
が溶けても絶縁性基板の半田は溶融することが無く、再
度固着部が溶け出すことがない。
As will be described later, an insulative substrate 38 having a second component and a second semiconductor element fixed to both sides by solder is prepared in advance, and this is fixed to the metal substrate 30 before the first metal substrate is bonded. When fixing a component or the first semiconductor element via solder, for example, when the solder is melted by a heater applied to the lower layer of the substrate as a heat source, the insulating substrate 38 is not directly heated by the heat source because of the hollow portion 44. , There is a time lag in temperature rise. Therefore, even if the solder on the metal substrate is melted, the solder on the insulating substrate is not melted, and the fixed portion is not melted again.

【0016】一方、金属基板30と絶縁性基板38の重
畳部は、例えば接着剤により固定されるが、固定部45
の様にしても良い。つまり絶縁性基板の周辺に設けられ
た半田ランド45(裏面にも設けていても良い)、スル
ーホールおよびこれと位置が一致した金属基板領域の半
田ランドが2点または3点設けられ、両者を半田を介し
て接続しても良い。また絶縁性基板の裏面と金属性基板
の表面の2点で固定しても良い。この場合、2枚の基板
の重畳部に接続点が存在するため、ヒーターからの熱は
絶縁性基板の重畳部には熱を伝えることが可能であるた
め、金属基板上の半田溶融と同時に実現することができ
る。従って、接着剤と併用して使えば、両基板の接着強
度を向上させることができ、また半田ランドを重畳部に
数多く点在させることで接着剤を省略することも可能で
ある。一般に接着剤は、加熱固化するものが多いため、
この加熱が省略でき、基板の劣化を防止できる。
On the other hand, the overlapping portion of the metal substrate 30 and the insulating substrate 38 is fixed by, for example, an adhesive.
You can also use That is, the solder lands 45 (which may be provided on the back surface) provided around the insulating substrate, the through holes and the solder lands in the metal substrate region whose position coincides with the through lands are provided at two or three points. You may connect through solder. Alternatively, the back surface of the insulating substrate and the front surface of the metallic substrate may be fixed at two points. In this case, since there is a connection point in the overlapping portion of the two substrates, the heat from the heater can be transferred to the overlapping portion of the insulating substrate. can do. Therefore, if it is used in combination with an adhesive, the adhesive strength of both substrates can be improved, and the adhesive can be omitted by interspersing a large number of solder lands in the overlapping portion. Generally, most adhesives heat and solidify,
This heating can be omitted, and the deterioration of the substrate can be prevented.

【0017】続いて製造方法について説明する。まず導
電路31や導電ランド32の貼着された金属基板30と
絶縁性基板38に第2部品や第2半導体素子が固着され
たものを用意する。ここで金属基板は前もって図示のよ
うなくり抜き部44が設けられている。続いて、絶縁性
基板38を金属基板30のくり抜き部44へ実装する。
この際、接着剤で固定しても良い。更に前もって設けら
れた半田を外部熱源、例えばヒーター等で溶融し、金属
基板の素子や部品、外部リードおよび固定部が半田によ
り固定される。ここで両基板の半田は、加熱前に半田ク
リームを載せておいても良いし、加熱の際に半田を載せ
ても良い。
Next, the manufacturing method will be described. First, a metal substrate 30 to which the conductive paths 31 and the conductive lands 32 are attached and an insulating substrate 38 to which the second component and the second semiconductor element are fixed are prepared. Here, the metal substrate is provided with a cutout portion 44 as shown in advance. Then, the insulating substrate 38 is mounted on the hollow portion 44 of the metal substrate 30.
At this time, it may be fixed with an adhesive. Further, the solder provided in advance is melted by an external heat source, for example, a heater or the like, and the elements and parts of the metal substrate, the external leads and the fixing portion are fixed by the solder. Here, as the solder of both substrates, solder cream may be placed before heating, or solder may be placed during heating.

【0018】従って、絶縁性基板38に固化されたくり
抜き部上の半田は、再溶融せず第2半導体素子や第2部
品の半田固定劣化を防止できる。また重畳部に設けられ
た接続部42や固定部45は、溶融するため、両基板間
の電気的接続や両基板の固定を実現できる。最後には、
図面では省略したが箱状の収納ケース等に収納され、中
に樹脂が必要により注入されて封止される。
Therefore, the solder on the cut-out portion solidified on the insulating substrate 38 is prevented from remelting and preventing the solder fixing deterioration of the second semiconductor element or the second component. Further, since the connecting portion 42 and the fixing portion 45 provided in the overlapping portion are melted, electrical connection between both substrates and fixing of both substrates can be realized. Finally,
Although not shown in the drawing, it is stored in a box-shaped storage case or the like, and a resin is injected therein as needed and sealed.

【0019】[0019]

【発明の効果】以上の説明からも明らかなように、第1
に、金属基板にくり抜き部を設け、この上に絶縁性基板
を実装するため、厚みのある半導体素子や部品を絶縁性
基板の両面に実装でき、しかもこのくり抜き部に実装さ
れる半導体素子や部品は、金属基板上の発熱素子からの
影響を受けずらいため、回路の誤動作、回路基板の劣化
等を防止できる。従ってパワー回路において、大信号用
半導体素子を金属基板に、絶縁性基板にそれ以外の小信
号用半導体素子を実装すれば、全体の回路の信頼性を維
持させることができる。また絶縁基板裏面の半導体素子
や部品は、くり抜き部があるために有る程度厚みのある
ものを実装でき、しかも2枚の基板間の固定のための接
着剤を省略できるために、接着剤固化の際による応力の
影響も無くすことができる。
As is apparent from the above description, the first
In addition, since the metal substrate is provided with a hollow portion and the insulating substrate is mounted thereon, a thick semiconductor element or component can be mounted on both sides of the insulating substrate, and the semiconductor element or component to be mounted in the hollow portion can be mounted. Since it is hard to be affected by the heating element on the metal substrate, malfunction of the circuit, deterioration of the circuit substrate, etc. can be prevented. Therefore, in the power circuit, if the large signal semiconductor element is mounted on the metal substrate and the other small signal semiconductor element is mounted on the insulating substrate, the reliability of the entire circuit can be maintained. Further, the semiconductor element or component on the back surface of the insulating substrate can be mounted with a certain thickness due to the hollow portion, and the adhesive for fixing between the two substrates can be omitted. It is also possible to eliminate the influence of stress due to time.

【0020】第2に、予め絶縁性基板に半導体素子や部
品を実装した状態で金属基板に載置し、このあと金属基
板上に半導体素子や部品を半田を介して固定しても、切
り抜き部には金属基板が無いため、この領域の絶縁性基
板は温度が上昇せず、前もって半田付けした固着部が再
溶融せず、信頼性の向上につながる。第3に、金属基板
との重畳部は、ヒーターからの熱を絶縁性基板に伝える
ことができ、両基板間の固定を行う半田、また両基板の
境界に設けた電気的接続のための半田を金属基板上の半
田溶融時に同時に行うことができる。従って工程の簡略
化が実現できる。
Secondly, even if the semiconductor element or component is mounted on the insulating substrate in advance and placed on the metal substrate and then the semiconductor element or component is fixed on the metal substrate via solder, the cutout portion Since there is no metal substrate, the temperature of the insulating substrate in this region does not rise, and the fixing portion soldered in advance does not remelt, which leads to improvement in reliability. Thirdly, the overlapping portion with the metal substrate can transfer the heat from the heater to the insulating substrate, and the solder for fixing the two substrates, and the solder for electrical connection provided at the boundary of both substrates. Can be performed simultaneously when the solder on the metal substrate is melted. Therefore, simplification of the process can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を説明する平面図である。FIG. 1 is a plan view illustrating an embodiment of the present invention.

【図2】図1の断面図である。FIG. 2 is a cross-sectional view of FIG.

【図3】従来の混成集積回路装置の平面図である。FIG. 3 is a plan view of a conventional hybrid integrated circuit device.

【図4】図3の断面図である。4 is a cross-sectional view of FIG.

【符号の説明】[Explanation of symbols]

30 金属基板 31,39 導電路 32,40 導電ランド 35 半導体素子 37 部品 38 絶縁性基板 44 くり抜き部 30 Metal Substrate 31,39 Conductive Path 32,40 Conductive Land 35 Semiconductor Element 37 Parts 38 Insulating Substrate 44 Cutout

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 表面を絶縁処理した金属基板と、この金
属基板に絶縁性接着剤を介して貼着された第1導電路お
よび第1導電ランドと、この第1導電路および第1導電
ランドに電気的に接続された第1半導体素子および第1
部品と、前記金属基板表面の少なくとも一部に実装され
た両面実装用の絶縁性基板と、この絶縁性基板の両面に
貼着され少なくとも一部で電気的に接続された第2導電
路および第2導電ランドと、この第2導電路および第2
導電ランドに電気的に接続された第2半導体素子および
第2部品と、前記第1導電路および第1導電パッドと前
記第2導電路および第2導電パッドとを電気的に接続す
る接続手段とを少なくとも備え、 前記金属基板には大信号用の第1半導体素子が実装さ
れ、前記絶縁性基板には小信号用の第2半導体素子が実
装され、 前記絶縁性基板下層の前記金属基板の少なくとも一部が
くり抜かれ、このくり抜き領域に対応する前記絶縁性基
板の裏面に前記第2半導体素子および/または第2部品
が実装されることを特徴とした混成集積回路装置。
1. A metal substrate whose surface is treated with insulation, a first conductive path and a first conductive land which are adhered to the metal substrate with an insulating adhesive, and the first conductive path and the first conductive land. A first semiconductor element and a first electrically connected to
A component, an insulating substrate for double-sided mounting mounted on at least a part of the surface of the metal substrate, a second conductive path and a second conductive path that are attached to both surfaces of the insulating substrate and are electrically connected at least in part. A second conductive land, and a second conductive path and a second conductive land.
A second semiconductor element and a second component electrically connected to the conductive land; and a connecting means for electrically connecting the first conductive path and the first conductive pad to the second conductive path and the second conductive pad. At least, a first semiconductor element for large signal is mounted on the metal substrate, a second semiconductor element for small signal is mounted on the insulating substrate, at least the metal substrate of the lower layer of the insulating substrate A hybrid integrated circuit device, wherein a part is hollowed out, and the second semiconductor element and / or the second component is mounted on the back surface of the insulating substrate corresponding to the hollowed out region.
【請求項2】 一部がくり抜かれ表面に導電路および導
電ランドが形成された金属基板およびこのくり抜かれた
領域に配置される絶縁性基板を用意する工程と、 前記絶縁性基板の導電路および/または導電ランドに半
田を介して半導体素子を固着する工程と、 前記金属基板に前記絶縁性基板を実装した後、この金属
基板の導電路および/または導電ランドに半田を介して
半導体素子を固着する工程とを少なくとも有することを
特徴とした混成集積回路装置の製造方法。
2. A step of preparing a metal substrate partly hollowed out to form conductive paths and conductive lands and an insulating substrate arranged in the hollowed-out region, and a conductive path of the insulating substrate and And / or fixing the semiconductor element to the conductive land via solder, and mounting the insulating substrate on the metal board, and then fixing the semiconductor element to the conductive path and / or conductive land of the metal board via solder A method of manufacturing a hybrid integrated circuit device, comprising:
【請求項3】 表面に導電路および/または導電ランド
が形成された金属基板およびこの金属基板のくり抜き部
に配置される絶縁性基板を用意する工程と、 前記絶縁性基板の導電路および/または導電ランドに半
田を介して半導体素子を固着する工程と、 前記金属基板のくり抜き部に前記絶縁性基板をのせ、こ
の金属基板の導電路および/または導電ランドに半田を
介して半導体素子を固着する工程と同時に、前記絶縁性
基板と前記金属基板が当接した領域の半田を介して固定
することを特徴とした混成集積回路装置の製造方法。
3. A step of preparing a metal substrate having a conductive path and / or a conductive land formed on a surface thereof and an insulating substrate arranged in a hollow portion of the metal substrate, and a conductive path and / or of the insulating substrate. A step of fixing a semiconductor element to a conductive land via solder; a step of mounting the insulating substrate on a hollow portion of the metal board, and fixing the semiconductor element to a conductive path and / or a conductive land of the metal board via solder At the same time as the step, a method for manufacturing a hybrid integrated circuit device is characterized in that the insulating substrate and the metal substrate are fixed to each other via solder in a region in contact with each other.
JP23345794A 1994-09-28 1994-09-28 Hybrid integrated circuit device and manufacture Pending JPH0897355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23345794A JPH0897355A (en) 1994-09-28 1994-09-28 Hybrid integrated circuit device and manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23345794A JPH0897355A (en) 1994-09-28 1994-09-28 Hybrid integrated circuit device and manufacture

Publications (1)

Publication Number Publication Date
JPH0897355A true JPH0897355A (en) 1996-04-12

Family

ID=16955339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23345794A Pending JPH0897355A (en) 1994-09-28 1994-09-28 Hybrid integrated circuit device and manufacture

Country Status (1)

Country Link
JP (1) JPH0897355A (en)

Similar Documents

Publication Publication Date Title
JP3165807B2 (en) Electronic semiconductor device, multi-chip module and row thereof
US5057461A (en) Method of mounting integrated circuit interconnect leads releasably on film
KR20080035974A (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
JPH0897355A (en) Hybrid integrated circuit device and manufacture
JP2636602B2 (en) Semiconductor device
JPH07115281A (en) Printed wiring board
JP2003046211A (en) Electronic component mounting structure
JP3203176B2 (en) Hybrid integrated circuit device and method of manufacturing the same
JP2735920B2 (en) Inverter device
JP3331146B2 (en) Manufacturing method of BGA type semiconductor device
JPH10284821A (en) Printed wiring board
JP2541494B2 (en) Semiconductor device
JP2669286B2 (en) Composite lead frame
JPH08264914A (en) Fpc with thermocompression bonded bump
JP2822987B2 (en) Electronic circuit package assembly and method of manufacturing the same
JP3199018B2 (en) Optical module
JPS5994897A (en) Method of producing hybrid integrated circuit
JPH06314707A (en) Hybrid integrated circuit
JPH0870017A (en) Double-sided substrate and electrode connection using both-sided substrate
JPH1022324A (en) Semiconductor device and its manufacture
JPH04340257A (en) Electronic-component mounting device and manufacture thereof
JPH08330361A (en) Method of mounting integrated circuit device
JPH05129743A (en) Hybrid integrated circuit device and manufacture thereof
JPS59950A (en) Connecting and mounting method for ic chip
JPH03192790A (en) Hybrid integrated circuit