JPH086874A - Method and device for multiplexing control - Google Patents

Abstract

PURPOSE:To improve the system operation rate of multiple-system constitution to which a bus coupling device is applied. CONSTITUTION:The output data of a CPU unit 3 are held in a memory 90, and the output data are transferred to the memory 93 of an input/output device 5 through a data transfer means 1 and also copied to the memory 94; and the data in the memory 94 are sent back to the memory 95 of the CPU unit 3 through the data transfer means 1 and the data in the memory 94 are sent back to the memory 96 of the CPU unit 3 through a data transfer means 2. The data of the memories 90 and 95, and the data of the memories 90 and 96 are compared with each other to judge whether the data transfer means 1 and 2 are normal or abnormal, thereby switching the data transfer means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple system control method and apparatus for controlling a plant in a multiprocessor system, and more particularly to a multiple system control method and apparatus suitable for improving the operating rate.

[0002]

2. Description of the Related Art In recent years, plant control systems have been made faster and larger in scale, and if a system goes down due to a failure, its effect will be extremely large. For this reason, it has become important to increase the system operating rate by adopting a configuration in which the entire system does not stop even if a failure occurs in a part of the system.

As a conventional high-speed and large-scale system, there is a multiprocessor system using bus connection. In this system, a plurality of CPU units and a plurality of input / output device units are connected by one bus coupling device unit to perform broadcast communication, and each CPU unit memory and all incoming / outgoing data are matched in parallel data transfer. Is planned by. In order to increase the system operating rate, CPU units are assigned to m input / output device units at a ratio of m, and each CPU constantly outputs to the corresponding input / output device unit, and some CPUs are abnormal. If there is, abnormal CP
CP which stopped U and another normal CPU stopped immediately
Output is performed on behalf of the input / output device unit that U was in charge of, and system control is continued. Furthermore, there is a conventional technique in which an m: n backup multiprocessor multiple system is provided by providing a backup system for an abnormal CPU by providing n spare CPUs.

However, in the above-mentioned conventional technique, since one bus coupling device unit exists as a common portion, there is a problem that the entire system must be stopped at the time of maintenance or failure of the bus coupling device.

Therefore, conventionally, as described in Japanese Patent Laid-Open No. 4-373240, two systems of CPUs and two systems of buses are provided, and two connection buffers for each CPU and bus are provided, and all system configurations are provided. By duplicating the elements, safety measures are taken against a single bus failure.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The conventional technique described in Japanese Patent No. 73240 is a standby duplex system in which two buses can use only one bus at a time. Therefore, there is a problem that it cannot be applied to an m: n backup multiprocessor system in which a plurality of CPUs control simultaneously. That is, conventionally, there is a problem that the operating rate of a multiprocessor system using a bus coupling device cannot be improved.

It is an object of the present invention to provide a multi-system control method and apparatus capable of improving the system operation rate without stopping the plant control even if one system of data transfer means fails in a multi-processor system for plant control. To provide.

[0008]

SUMMARY OF THE INVENTION The above object is to provide a data output from a CPU unit and the data output from the CPU unit in a multiplexing control device having a plurality of data transfer means between a CPU unit and an input / output device. The data transferred to the input / output device through one of the data transfer means is returned to the CPU unit through the data transfer means, and the CPU unit compares the returned data with the output data and outputs the data from the data transfer means. By judging normality / abnormality,
Achieved.

Further, the above-mentioned object is to return the data outputted from the CPU unit and the data obtained by transferring the data to the input / output device through the first data transfer means to the CPU unit through the second data transfer means. The unit compares the returned data with the output data described above to determine whether the data transfer means is normal or abnormal.
Achieved.

Further, the above object can be achieved by switching the data transfer means when it is determined that there is an abnormality.

[0011]

The failure of the data transfer means includes a failure of the input system and a failure of the output system. In the present invention, since the output data from the CPU unit is compared with each data returned to the CPU unit through at least two data transfer means, not only the presence or absence of the failure of the data transfer means, Since it is possible to discriminate whether the input system or the output system of the data transfer means has a failure, it is possible to perform appropriate processing for improving the system operating rate.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a multiplex system controller according to an embodiment of the present invention. The multiple system control device of FIG. 1 includes bus coupling device units (data transfer means) 1 and 2, CPU units 3 and 4, input / output device units 5 and 6, an output connection signal generator 7, and a plant 9. Composed.

The CPU unit 3 includes a CPU 30 and a CP.
The U internal first bus connection port 31, the CPU internal second bus connection port 32, and an internal bus 38 that connects them to each other. The CPU unit 4 has the same configuration.

The bus coupling device unit 1 includes a connection port 13 for the CPU unit 3, a connection port 14 for the CPU unit 4, a connection port 15 for the input / output device unit 5, and
It is composed of a connection port 16 of the input / output device unit 6, a bus coupling control mechanism 10, and an internal bus 18 which connects these to each other. The bus coupling device unit 2 has the same configuration.

The input / output device unit 5 includes input / output control mechanisms 51, 52, output devices 53, 55, an input device 54,
56, and an internal bus 58 connecting these to each other. The input / output device unit 6 has the same configuration.

The in-CPU first bus connection port 31 of the CPU unit 3 is connected to the connection port 13 of the bus coupler unit 1 by the data transfer line 813, and the in-CPU second bus connection port 32 is connected by the data transfer line 823. , The connection port 23 of the bus coupler unit 2. Further, the in-CPU first bus connection port 41 of the CPU unit 4 is connected by the data transfer line 814.
Connected to the connection port 14 of the bus coupler unit 1,
The second bus connection port 42 in the CPU is connected to the connection port 2 of the bus coupler unit 2 by the data transfer line 824.
4 is connected.

Connection port 15 of bus coupler unit 1
Is connected to the input / output control mechanism 51 of the input / output device unit 5 by the data transfer line 815, and the connection port 16
Are connected to the input / output control mechanism 61 of the input / output device unit 6 by the data transfer line 816. Further, the connection port 25 of the bus coupler device unit 2 is connected to the input / output control mechanism 52 of the input / output device unit 5 by the data transfer line 825, and the connection port 26 is connected by the data transfer line 826. Of the input / output control mechanism 62.

The CPU 30 of the CPU unit 3 and the output switching signal generator 7 are connected by the output switching request signal line 837, and the CPU 40 of the CPU unit 4 and the output connection signal generator 7 are connected to the output switching request signal line. 847
Connected by. The output connection signal generator 7 and the input / output control mechanism 51 of the input / output device unit 5 and the input / output control mechanism 61 of the input / output device unit 6 are connected by an output connection signal line 871. 7, the input / output control mechanism 52 of the input / output device unit 5 and the input / output control mechanism 62 of the input / output device unit 6,
Output connection signal line 87 which is the inverted signal of the line 871
Connected by two. The output device 53 and the input device 54 are connected to the plant 9 through an output signal line 853. The output devices 55, 63, 65 and the input devices 56, 64, 66 are similarly connected.

The bus connection port 31 of the CPU unit 3,
Reference numerals 32 each have a memory and store plant control data. The CPU 30 performs control calculation of the plant 9 based on this memory data, and when detecting an abnormality, outputs an output switching request signal on the output switching request signal line 837. The CPU unit 4 is also performing the same operation.

The bus coupling control mechanism 10 of the bus coupling device unit 1 determines the address of the data to be transferred by the internal bus 18.
Output to. This address is passed through the corresponding bus connection port, the bus connection port 31 of the CPU 3, the bus connection port 41 of the CPU 4, the input / output control mechanism 51 of the input / output device unit 5, the input / output control mechanism 61 of the input / output device unit 6.
To receive. The bus connection port and the input / output control mechanism are provided with area registration for distinguishing whether the own port is the information source or not by the address. As a result, one of the ports that received the address becomes the data transmission source and the other ports become the data reception destinations.

When the bus connection port 31 of the CPU unit 3 is the transmission source, the bus connection port 31 outputs the memory data, and the bus connection port 41 of the CPU unit 4 transmits this data via the bus coupling device unit 1. Received,
Store in internal memory. Further, the input / output control mechanisms 51, 61
Also receives this data via the bus combiner unit 1 and, via the internal bus 58, the output devices 53, 55, 63,
Send data to 65. Output devices 53, 55, 63, 65
Are output signal lines 853, 855 based on this data.
Output to the plant 9 via 863 and 865.

Input / output control mechanism 5 of input / output device unit 5
1 is the source, the input / output control mechanism 51 is the plant 9
Of the input device 54, 56
The data is taken in through, output as data, received by the bus connection ports 31 and 41 of the CPU units 3 and 4, and the data is stored in the respective memories. This operation is the same for the bus coupler unit 2.

Input / output control mechanism 51, 52, 61, 62
Transmits / receives data to / from the bus coupling device units 1 and 2, and outputs devices 53 55, 63, 65 and input devices 54, 56, 6
Input and output to and from the plant 9 via 4, 66, and here, input O of the output switching signal from the lines 871 and 872
The operation changes depending on N and OFF. When the output connection signal is ON, the input data from the input device is transmitted, and the reception data is written to the output device. When the output connection signal is OFF, the input data from the input device is transmitted, but the received data is received. Is not written to the output device, and dummy writing that does not cause an error to the bus coupling device is performed.

Each of the input / output device units 5 and 6 has two input / output control mechanisms, to which an output connection signal 871 and an inverted output connection signal 872 are connected. Since these signals are mutually exclusive, the data transmission of the input / output device can be performed by the two input / output control mechanisms, and the output right to write the received data to the output device has the output connection signal ON. There is only one input / output control mechanism on the operating side.

The output connection signal generator 7 outputs the output connection signal 871, and outputs the output switching request signals 837 and 847 output from the CPU units 3 and 4 to the NOR 71.
And output connection signal 871 is generated. Also, this signal is inverted by the inverter 72 to generate the inverted output connection signal 872. As a result, even if only one CPU detects a plant control abnormality and outputs an output switching request signal,
The output connection signal is turned off, and the output right of the input / output control mechanism is transferred to another.

Next, the overall operation of the multiplex system controller shown in FIG. 1 will be described. Now, if there is no abnormality in the system, the CPU units 3 and 4 output the output switching request signal 837,
847 is turned off. As a result, the output connection signal generator 7 turns on the output connection signal 871 and turns off the inverted output connection signal 872. As a result, in the input / output control mechanisms 51 and 61, since the output connection signal 871 is ON, the output connection mechanisms 512 and 612 are connected and are in the output permission state. Further, since the inverted output connection signal 872 is OFF in the input / output control mechanisms 52 and 62, the output connection mechanism 5
22 and 622 are opened, and the output is not permitted.

The CPU 30 calculates the plant control data stored in the internal memory of the connection ports 31 and 32, stores the result in the internal memory of the connection ports 31 and 32, and transfers the data to the output area registered in advance. I am updating. The CPU 40 also operates in the same manner. The bus coupling control mechanism 10 of the bus coupling device unit 1 sequentially outputs the addresses. However, when the address of the output area of the bus connection port 31 of the CPU unit 3 is output, the CPU 30 of the connection port 31 Output the updated internal memory data.

This data is output to the internal bus 18 via the connection port 13 of the bus coupler unit 1, and the CP
It is transmitted to the bus connection port 41 in the CPU unit 4 via the connection port 14 of the U unit 4 and stored in its internal memory. Further, the data on the internal bus 18 is transmitted to the input / output control mechanism 51 via the connection port 15, via the output connection mechanism 512, and further via the internal bus 58,
It is written in the output device 53. The output device 53 outputs 8
53 is output to the plant 9 to control the plant 9. The output 853 is also captured by the input device 54.

Next, when the bus control mechanism 10 outputs the address of the output area of the input / output control mechanism 51, the input / output control mechanism 10 reads the data of the input device 54 and outputs it to the internal bus 18 via the connection port 15. . This data is
It is transmitted to the bus connection port 41 of the CPU unit 4 via the connection port 14 and stored in the internal memory. Also,
The data on the internal bus 18 is transferred to C via the connection port 13.
It is transmitted to the bus connection port 31 of the PU unit 3 and stored in the internal memory.

The CPU 30 collates the data returned via the bus coupling device unit 1 with the data previously stored in its own internal memory, confirms whether they match, and if they match, the output switching request signal. Leave 837 OFF. On the other hand, the bus coupling device unit 2 side operates in the same manner, but the input / output control mechanism 52 opens the output connection mechanism 522 because the inverted output connection signal 872 being input is OFF. It does not output the data received from the combiner unit 2 to the internal bus 58. However, since input is possible, the data of the input device 54 is transmitted to the bus connection port 32 of the CPU 3 and the bus connection port 42 of the CPU 4 via the bus coupler unit 2.
The CPU 30 collates the data returned to the bus connection port 32 with the data stored in its own internal memory. As a result, the plant control data is output to the plant 9 by the bus coupling device unit 1 system and is not output by the bus coupling device unit 2 system. In addition, the output to the plant 9 is read out by two systems, and it is collated whether it matches the output source data.

Consider a case where the bus coupling control mechanism 10 fails, the bus connection ports 13 and 15 fail, or the data transfer lines 813 and 815 are disconnected. When such a failure occurs, the bus coupling unit 1
Since data cannot be transmitted or received from the CPU 30 to the plant 9 via the bus connection device unit 1
The contents of the data area that should be returned via the transmission source data stored in its own internal memory will not match. As a result, the CPU 30 detects the collation error and outputs the output switching request signal 837 to ON. Upon receiving this, the output connection signal generator 7 outputs the output connection signal 871 OFF because the output switching request signal of each CPU is ON, and
The inverted output connection signal 872 is output ON. This allows the input / output control mechanism 5 connected to the output connection signal 871.
The output connection mechanisms 512 and 612 of 1, 61 are opened, and the output right is lost. Also, the output connection mechanisms 522, 6 of the input / output control mechanisms 52, 62 connected to the inverted connection signal 872.
22 is connected and gets the output right. As a result, the output data for controlling the plant 9 is transmitted from the CPU to the output device via the bus coupling device unit 2.

Next, a system control method by data collation will be described.
This will be described with reference to FIGS. FIG. 2 shows a memory (denoted by a code in the 90s in the frame) in each device, and FIG. 3 shows a processing procedure of the input / output system control program.

The memories 91 and 95 in the connection port 31 are
It is a first-system memory, and the output data from the memory 90 in the CPU is stored in the memory 91, and the memory 95 is
Input data is stored. Further, the memories 92 and 96 in the connection port 32 are memories of the second system.
The output data from the memory 90 in the CPU is stored in
Input data is stored in the memory 96. Output device 53
Output data to the plant 9 is stored in the internal memory 93, and input data is stored in the memory 94 in the input device 54.

In the control program of FIG. 3, the first system is selected and controlled. The CPU 30 stores output data in the memory 90, and the memory 91, the memory 92
The data is transferred to each and the bus connection transfer wait is performed.

The bus coupling device 1 transfers the data in the memory 91 to the memory 93 in the output device 53 via the output connection mechanism 512.
Transfer to. Since the output device 53 outputs this output data to the plant 9 and also feeds it back to the input device 54, the input device 54 captures this data and stores it in the memory 94.

Next, the bus coupler 1 transfers the data in the memory 94 to the memory 95. On the other hand, the bus coupling device 2
Tries to store the data in the memory 92 in the memory 93, but cannot store it in the memory 93 because the output connection mechanism 522 is opened. However, the data in the memory 94 is transferred to the memory 96.

If the currently used bus coupling system is the first system, the CPU stores data in the memory 90 and memory 9.
The data in memory 5 are compared with each other, and if they match, then the data in memory 90 and the data in memory 96 are compared.
If the comparison results are in agreement, it is determined that both bus connection systems are normal, and the process proceeds to the next process. When the data in the memory 90 and the data in the memory 96 do not match, it is determined that there is an abnormality in the input route of the second system, and after reporting to the system monitoring device or the like, the process proceeds to the next process.

If the data in the memory 90 does not match the data in the memory 95, the data in the memory 90 and the memory 9
Compare with the data in 6. If the comparison results match, it is determined that the input route of the first system is abnormal, and after reporting, the read data is changed to use the data of the second system, and the process proceeds to the next process. If the memory 90 and the memory 96 do not match, it is determined that there is an abnormality in the output route of the first system, and after reporting, the output system is switched. This is done by turning on the output switching request signal 837.

After that, the bus connection transfer wait is performed, and the data return by the second route is waited. By this output switching, the bus coupling system currently in use becomes the second system, so the memory 90 and the memory 96 are compared, and if they match, the process proceeds to the next process. If they do not match, the memory 90 and the memory 95 are compared. If they match, it is determined that the input route of the second system is abnormal, the read data is changed to use the data of the first system, and the process proceeds to the next process. . If they do not match, it is determined that the output route of the second system is abnormal, and the output route abnormality of the first system has already been detected, so it is considered that control cannot be continued and error processing is performed.

From the above, even if the bus coupler unit currently in use fails, the output system shifts to the system of another bus coupler unit, so that plant control can be continued and the operating rate can be increased. it can.

FIG. 4 is an overall configuration diagram of a multiplexing controller according to another embodiment of the present invention. In this embodiment, n system bus coupling units are used. The multiplexing controller of the present embodiment includes a # 1 bus coupler unit 1, a # 2 bus coupler unit 2, a # 3 bus coupler unit 100, ...
#N bus coupler unit 200 has n bus coupler units. The CPU unit 3 has a bus connection port 3 in the CPU for connecting the # 1 bus coupler unit 1.
N corresponding to each bus coupler unit including 1
It has a bus connection port in the CPU. The same applies to the CPU unit 4.

The input / output device unit 5 has an input / output control mechanism 51 for connecting the # 1 bus coupling device unit 1, and n input / output control mechanisms corresponding to the respective bus coupling device units. Also, an n-system output connection signal generator 700 is provided, connected to the CPU unit 3 by the output switching request signal 83700, connected to the CPU unit 4 by the output switching request signal 84700, and connected to the input / output control mechanism 51 by #.
One output connection signal 8701 is connected, and the output connection signals # 1 to #n are connected to each of the n input / output control mechanisms.

FIG. 5 is a diagram showing an internal configuration of an example of the n-system output connection signal generator 700 shown in FIG. The output switching request signal 83700 from the CPU unit 3 is connected to the n-system output connection generator 700 by n signal lines # 1 to #n, and the CPU unit 3 uses the signal line of the bus coupling system number to be used. Is turned on and the other signal lines are turned off.
The same applies to the CPU unit 4. In the n-system output connection signal generator 700, the # 1 OR gate 730 and n
There are 5 OR gates, and the # 1 OR gate 730 has
The # 1 output switching request signals from the CPU unit 3 and the CPU unit 4 are connected. The outputs of the n OR gates are connected to the inputs # 1 to #n of the priority encoder 710. Priority weighting is prioritized on the #n side. Priority encoder 7
10 is connected to the decoder 720, and decoder outputs # 1 to # 1
#N is associated with inputs # 1 to #n of the priority encoder.

Here, for example, when the CPU unit 3 selects the # 1 bus connection system, the CPU unit 3 turns on the # 1 signal line of the output switching request signal 83700. Also,
When the CPU unit 4 selects the # 3 bus connection system, C
The PU unit 4 turns on the # 3 signal line of the output switching request signal 84700. This turns on the outputs of the # 1 OR gate and the # 3 OR gate. This turns on inputs # 1 and # 3 of the priority encoder 710,
Due to the priority, the priority encoder 710 and the decoder 720 turn ON only the output # 3 of the decoder 720,
Others are turned off.

In this way, the n-system output connection signal generator 700 selects the system number with the highest weighting from the output switching request signals output from each CPU. In addition, each CP
The bus connection system number selected by U is # 1 in the initial state.

Next, the operation of the multiplexing controller of FIG. 4 will be described. Now, the CPU units 3 and 4 have both selected the # 1 system, and only the # 1 input / output control mechanism 51 can output. The bus coupler units # 1 to #n always perform data matching. In this state, each CPU collates the output data with the input data captured by using each bus coupling system, and diagnoses whether there is an abnormality in each bus coupling system.

Here, the CPU unit 3 or 4 is
When the mismatch of the input data taken in from all the systems is detected, the output switching request signal is switched from # 1ON to # 2ON. As a result, the output connection signal generator 700 switches the system selection from # 1 to # 2. As a result, only the input / output control mechanism 52 shifts to the output enabled state. This way, #
If one system is abnormal, go to # 2, if # 2 is abnormal, go to # 3.
You can switch up to.

From the above, even if the bus coupler unit currently in use fails, the output system shifts to the system of another bus coupler unit, so that plant control can be continued and the operating rate can be increased. it can.

In this embodiment, two CPU units,
Although one input / output device unit is used, the same effect can be obtained even if one or a plurality of CPU units and input / output device units are installed.

[0050]

According to the present invention, even if the bus coupler of one system fails, the fault can be detected reliably and the plant control can be transferred to the bus coupler of the normal system to continue.
The system operation rate can be increased, and it is also possible to repair the fault of the abnormal system during plant control in the normal system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiplex system control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a built-in memory in each device shown in FIG.

3 is a flowchart showing a processing procedure of a multiplex system control method of the apparatus shown in FIG.

FIG. 4 is a configuration diagram of an n-system multiplex system controller according to another embodiment of the present invention.

5 is a configuration diagram of an n-system output connection signal generator shown in FIG.

[Explanation of symbols]

1, 2 ... Bus coupling device unit, 3, 4 ... CPU unit, 5, 6 ... Input / output device unit, 7 ... Output connection signal generator, 9 ... Plant, 10, 20 ... Bus coupling control mechanism,
30, 40 ... CPU, 51, 52, 67, 62 ... Input / output control mechanism, 31, 32, 41, 42 ... In-CPU bus connection port, 13, 14, 23, 24 ... CPU unit bus connection port, 15, 16 , 25, 26 ... Input / output device unit bus connection port.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiromasa Yamaoka 52-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika Plant, Ltd. (72) Inventor Ryuichi Watanabe 2-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1 Hiritsu Process Computer Engineering Co., Ltd.

Claims (18)

[Claims] 1. A method of controlling a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, wherein the data output from the CPU unit,
The data transferred to the input / output device through one of the data transfer means is C
The multiplexing control method, wherein the CPU unit returns to the PU unit, and the CPU unit compares the returned data with the output data to determine normality / abnormality of the data transfer means. 2. A data output from a CPU unit in a method of controlling a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device.
The data transferred to the input / output device through the first data transfer means is transferred to the C through the second data transfer means.
The multiplexing control method, wherein the CPU unit returns to the PU unit, and the CPU unit compares the returned data with the output data to determine whether the data transfer means is normal or abnormal. 3. A method of controlling a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, wherein the output data output from the CPU unit and the output data are first data. The first return data obtained by returning the data transferred to the input / output device through the transfer unit to the CPU unit through the first data transfer unit and the data transferred to the input / output device through the first data transfer unit are The second return data returned to the CPU unit through the second data transfer means are compared, and when the output data = the first return data and the output data = the second return data, the data transfer means is judged to be normal. Multiplexing control method. 4. A method for controlling a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, wherein the output data output from the CPU unit and the output data are first data. The first return data obtained by returning the data transferred to the input / output device through the transfer unit to the CPU unit through the first data transfer unit and the data transferred to the input / output device through the first data transfer unit are The second return data returned to the CPU unit through the second data transfer means is compared, and when the output data = the first return data and the output data ≠ the second return data, there is an abnormality in the input system of the second data transfer means. A multiplexing control method, characterized by: 5. A method of controlling a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, wherein the output data output from the CPU unit and the output data are first data. The first return data obtained by returning the data transferred to the input / output device through the transfer unit to the CPU unit through the first data transfer unit and the data transferred to the input / output device through the first data transfer unit are The second return data returned to the CPU unit through the second data transfer means is compared, and when output data ≠ first return data and output data = second return data, there is an abnormality in the input system of the first data transfer means. And the input system from the input / output device is switched to the second data transfer means. 6. A method of controlling a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, wherein the output data output from the CPU unit and the output data are first data. The first return data obtained by returning the data transferred to the input / output device through the transfer unit to the CPU unit through the first data transfer unit and the data transferred to the input / output device through the first data transfer unit are The second return data returned to the CPU unit through the second data transfer means is compared, and when the output data ≠ the first return data and the output data ≠ the second return data, there is an abnormality in the output system of the first data transfer means. And the output system is switched to the second data transfer means. 7. The method according to claim 6, wherein the first → second and second →
When the result of the data comparison according to claim 6 performed by the CPU unit after switching the first data transfer means is the same as in claim 6, it is determined that both the output systems of the first and second data transfer means are abnormal. A method for controlling a multiplex control device, comprising: 8. The method for controlling a multiplexing device according to claim 1, wherein at least two CPU units are provided, and each CPU unit makes the comparison and the determination separately. 9. The method of controlling a multiplexing control device according to claim 1, further comprising at least two input / output devices. 10. In a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, a first memory for holding data output from the CPU unit in the CPU unit, and the data. A second memory for storing the data transferred to the input / output device through one of the data transfer means by returning the data to the CPU unit through the data transfer means, and the CPU unit stores the data in the first memory and the second memory. A multiplexing control device, comprising means for comparing the data of the above-mentioned data and judging whether the data transfer means is normal or abnormal. 11. A multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, a first memory for holding data output from the CPU unit in the CPU unit, and the data. A second memory for returning the data transferred to the input / output device through the first data transfer means to the CPU unit through the second data transfer means and storing the data, and the CPU unit stores the data in the first memory and the second memory. A multiplexing control device comprising means for comparing data in a memory to determine whether the data transfer means is normal or abnormal. 12. In a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, a first memory for holding output data output from the CPU unit, and the output data A second memory for storing first return data obtained by returning the data transferred to the input / output device through the first data transfer means to the CPU unit through the first data transfer means; and the input memory through the first data transfer means. The second data transferred to the output device
Returned to the CPU unit through the second data transfer means
A third memory for storing return data, and C
The multiplexing control device, wherein the PU unit comprises means for judging the data transfer means to be normal when the output data = first return data and the output data = second return data. 13. In a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, a first memory for holding output data output from the CPU unit, and the output data A second memory for storing first return data obtained by returning the data transferred to the input / output device through the first data transfer means to the CPU unit through the first data transfer means; and the input memory through the first data transfer means. The second data transferred to the output device
Returned to the CPU unit through the second data transfer means
A third memory for storing return data, and C
The multiplexing control device, wherein the PU unit includes means for determining that there is an abnormality in the input system of the second data transfer means when output data = first return data and output data ≠ second return data. 14. In a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, a first memory for holding output data output from the CPU unit, and the output data A second memory for storing first return data obtained by returning the data transferred to the input / output device through the first data transfer means to the CPU unit through the first data transfer means; and the input memory through the first data transfer means. The second data transferred to the output device
Returned to the CPU unit through the second data transfer means
A third memory for storing return data, and C
The PU unit has output data ≠ first return data and output data =
When it is the second return data, it is determined that the input system of the first data transfer means is abnormal, and the input system from the input / output device is set to the second system.
6. A multiplexing control device comprising means for switching to said data transfer means. 15. In a multiplexing control device comprising a plurality of data transfer means between a CPU unit and an input / output device, a first memory for holding output data output from the CPU unit, and the output data A second memory for storing first return data obtained by returning the data transferred to the input / output device through the first data transfer means to the CPU unit through the first data transfer means; and the input memory through the first data transfer means. The second data transferred to the output device
Returned to the CPU unit through the second data transfer means
A third memory for storing return data, and C
The PU unit has output data ≠ first return data and output data ≠
A multiplexing control device comprising means for judging that there is an abnormality in the output system of the first data transfer means for the second return data and switching the output system to the second data transfer means. 16. The data comparison result according to claim 6, wherein the CPU unit performs comparison of the data according to claim 6 performed by the CPU unit after switching the first-> second and second-> first data transfer means. In the same case as above, the multiplexing control device is provided with means for judging that there is an abnormality in both the output systems of the first and second data transfer means. 17. The multiplexing control device according to claim 10, wherein at least two CPU units are provided, and each CPU unit separately performs the comparison and the determination. 18. The multiplexing control device according to claim 10, further comprising at least two input / output devices.