JPH086841A - Memory control unit - Google Patents

Abstract

PURPOSE:To obtain the high-speed memory system by reducing the wait state of a CPU even at DRAM refresh cycle as to a memory system which uses a DRAM. CONSTITUTION:When the DRAM area of a memory area is accessed, a data acknowledgement generating device 14 substantially stops the operation of the CPU and then refreshing operation is performed by using an RAS.CAS generating device 13; When write access is performed even when an area other than the DRAM area is accessed, the operation of the CPU is substantially stopped, refreshing operation is performed after a read/write signal controller 15 stops input operation for a write signal, but in other cases, the refreshing operation is performed without stopping the operation of the CPU and the input operation for the signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic random access memory (hereinafter referred to as "DRAM") and a pseudo S.
The present invention relates to a memory control device that controls a memory system including a dynamic memory such as a RAM.

[0002]

2. Description of the Related Art Generally, when a DRAM stores data, a high / low storage state is held depending on the presence / absence of charges stored in a capacitor, but the charge is gradually lost due to leakage current or the like with the lapse of the holding time. The operation of resetting the high / low potential again (hereinafter referred to as "refresh operation") is required. The refresh operation of the DRAM and the like is controlled by the memory control device.

A conventional memory control device will be described with reference to the drawings. FIG. 4 shows the configuration of a conventional memory control device. In FIG. 4, 101 is an entire memory control device, 102 is an address decoder that determines which memory an address value generated by a central processing unit (hereinafter referred to as "CPU") indicates, and 103 is an address valid generated by the CPU. A chip select generator that inputs a signal and a value generated by an address decoder and generates a chip select signal in an actual memory chip.
Is a refresh request generator that generates a refresh request signal at a predetermined timing, 105 is a data acknowledge generator (DK generator) that generates a data acknowledge signal indicating the end of access to the memory, 106
Is a RAS / CAS generator for generating a RAS (row address strobe) signal and a CAS (column address strobe) signal which are signals for controlling DRAM.
8 is address data generated by the CPU, 109 is a memory area signal generated by the address decoder 102, 110 is a signal indicating the DRAM area of the memory area signal bus, 1
11 is a chip select signal, 112 is an address valid signal, 113 is a refresh request signal, 114 is a RAS signal, 115 is a CAS signal, 107 is a bus use right request signal generator for requesting a bus right to the CPU, and 116 is C
Bus right request signal for requesting bus right from PU, 1
Reference numeral 17 is a bus release signal issued from the CPU, and 118 is a refresh cycle start instruction signal.

In the memory control device configured as described above, the RAS signal and the CAS signal are used to control the DRAM. By changing the input timing of these two signals, the refresh mode and the normal write / read mode are used. And are switched.

FIG. 5 shows a RAS currently generally used.
The input timing of a signal and a CAS signal is shown. FIG.
Shows a case where normal writing / reading is performed, and FIG. 7B shows a case where refreshing is performed. Like this
Since the mode is changed by changing the timing of the control signals (RAS, CAS) input to the RAM, the CPU cannot access the DRAM for writing or reading while refreshing the DRAM. . Therefore, it is necessary to stop the operation of the CPU when refreshing the DRAM.

The operation of refreshing the DRAM will be described. Based on the address data 108 issued when the CPU accesses the memory, the address decoder 102 determines which memory area is being accessed and outputs a memory area signal 109. An address valid signal 112 indicating the start of access is input to the chip select generator 103 together with the memory area signal 109. At this time, the value of the memory area signal 109 is DRA.
If the area other than the M area is shown, the chip select generation device 103 confirms that the address valid signal 112 is valid,
A chip select signal 111 is generated for the memory chips arranged in each memory area. Also, the memory area signal 1
If the value of 09 indicates the DRAM area, the DRAM area signal 110 allows the RAS / CAS generator 106 to confirm the validity by the address valid signal 112, and the RAS to the DRAM.
-Generate and access CAS.

On the other hand, the refresh request generator 104 generates a refresh request signal 113 at a constant timing. When the bus right request signal generator 107 receives the refresh request signal 113 as shown in the timing chart of FIG.
A bus release request signal 116 is generated for U. In response to this request, if the CPU is not currently accessing the bus, it outputs a signal (bus release signal 117) indicating that the CPU will stop immediately. If the CPU is currently accessing the bus, the CPU outputs the bus release signal 117 immediately after the completion of the access. In order to obtain the stopped state of the CPU, the data acknowledge signal output from the data acknowledge (DK) signal generator 105 is set to the low level and is not returned to the CPU instead of actually stopping the CPU. Recognize that access to has not ended. This substantially stops the CPU. Bus right request signal generator 1
When 07 receives the bus release signal 117, the refresh cycle start signal 118 is generated. When the refresh cycle start signal 118 becomes active, the refresh request generator 104 negates the refresh request signal 113, and the RAS / CAS generator 106 causes the RAS signal 11 at the refresh timing shown in FIG. 5B.
4. Output the CAS signal 115 to refresh the DRAM.

[0008]

However, in the above configuration, the CP is not refreshed during the DRAM refresh cycle.
After requesting bus right from U and stopping CPU, D
In order to perform the RAM refresh, the CPU does not operate during the dotted line portion of the timing chart shown in FIG.
There was a problem of degrading the performance of the entire system.

The present invention is intended to solve the above-mentioned problems.
It is an object of the present invention to provide a memory control device capable of high-speed operation by minimizing CPU stop even during an AM refresh cycle.

[0010]

In order to solve the above-mentioned problems, a memory control device of the present invention comprises a refresh control signal generating section for controlling a refresh operation of a dynamic memory, and a CPU control section for controlling an operation of a CPU. A signal control unit that controls a signal (for example, a write signal) commonly input to the dynamic memory area and other areas, and when accessing the dynamic memory area of the memory area,
When the CPU control unit substantially stops the operation of the CPU and the refresh control signal generation unit performs the refresh operation, and also when accessing an area other than the dynamic memory area, it is not the dynamic memory area and the dynamic memory area. When a common signal is input to the area of
The operation of the PU is substantially stopped, the input operation of the common signal is substantially stopped by the signal control unit, and the refresh operation is performed using the refresh control signal generation unit. In other cases, the operation of the CPU and The refresh operation is performed without stopping the signal input operation.

[0011]

According to the present invention, the above configuration prevents the CPU from entering the wait state unless the CPU requests the bus right and the CPU accesses the DRAM area or the write access to another memory area.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the overall configuration of a computer system using the memory control device of the present invention.
In the figure, reference numeral 1 denotes one semiconductor chip, on which a CPU 2, a memory control device 3, a read only memory (ROM) and a random access memory (RAM) 5 are mounted. These components are configured to exchange addresses and data via the address bus 8 and the data bus 9. Also, the CPU 2 sends an address valid signal (DS) 20 and a read / write signal 21 to the memory control device 3. A dynamic memory such as DRAM 6 and a static memory such as SRAM 7 are provided in each memory area outside the chip 1, and are controlled by the memory control device 3. In particular, the operation of the dynamic memory such as the DRAM 6 is controlled by the RAS signal and the CAS signal sent from the memory control device 3. The memory control device 3 is a DRAM
6, a read / write signal that is a write signal or a read signal of information is sent to the SRAM 6 and the SRAM 7. Of these, the write signal WR is sent to both the DRAM 6 and the SRAM 7 in common. From the memory control device 3, a data acknowledge signal (DK) 26 indicating the completion of access to the memory area is sent to the CPU 2.

FIG. 2 shows the configuration of an embodiment of the memory control device of the present invention. In the figure, 10 is an address decoder for determining which memory the address value generated by the CPU indicates, 11 is an address valid signal generated by the CPU and a value generated by the address decoder,
A chip select generator for generating a chip select signal to an actual memory chip, 12 is a refresh request generator for generating a refresh request signal at a predetermined timing, and 13 is a DRAM for generating a RAS signal or a CAS signal at a predetermined timing. To control refresh operation
The AS / CAS generator functions as a refresh control signal generator. Reference numeral 14 is a data acknowledge generator, which generates a data acknowledge signal indicating that the access to the memory that has accessed the CPU is completed. if,
Unless the data acknowledge signal is generated from the data acknowledge generator 14, the CPU cannot recognize the end of access, so the CPU waits for the end of access and is in a substantially stopped state. The data acknowledge generator 14 functions as a CPU controller.

Reference numeral 15 is an OR circuit, which is a read / write signal control device which determines whether the read / write signal output from the CPU can be output to the actual memory chip and outputs the read / write signal, which functions as a signal control unit. The read / write signal 21 input to the read / write signal controller 15 is C
It is a high / low digital signal sent from PU, and when it is high, it makes read access to the memory, and when it is low, it makes write access. Since the read / write signal control device 15 is composed of an OR circuit, the read / write signal 21
Refresh cycle signal 2 regardless of high or low
When 5 goes high (active), the output memory read / write signal 27 is always high. Therefore, the read / write signal control device 15 can be controlled to stop the write signal and always output only the read signal (high).

16 is address data generated by the CPU,
Reference numeral 17 is a memory area signal bus generated by the address decoder 10, 18 is a signal indicating a DRAM area in the memory area signal bus 17, 19 is a chip select signal, 20 is an address valid signal indicating the start of access, and 22 is a refresh request signal. , 23 is a RAS signal, 24 is a CAS signal, 2
Reference numeral 5 is a refresh cycle signal indicating execution of a refresh cycle, 26 is a data acknowledge signal, and 27 is a memory read / write signal output to a memory chip.

The operation of the device having the above-described structure will be described. Address data 1 output from the CPU by the address decoder 10
It is determined from 6 which memory area is being accessed and a memory area determination signal 17 is output. If the value indicates an area other than the DRAM, the chip select generator 11
Confirms that the address valid signal 20 is valid,
The chip select signal 19 is generated in each of the memory chips arranged in each memory area, and the data acknowledge generator 14 generates the data acknowledge signal 26 at a timing corresponding to each memory chip.

The address decoder 10 sets the access area to D
If it is determined to be the RAM area, the memory area determination signal 1
The DRAM area signal 18 of 7 becomes active.
When the DRAM area signal 18 becomes active, RAS.C
The AS generator 13 confirms the validity by the address valid signal 20, and sends to the DRAM the RAS signal 23 which is a control signal and the CAS signal.
Generate signal 24. The data acknowledge signal generator 14 also generates a data acknowledge signal at the timing for accessing the DRAM.

On the other hand, the refresh request generator 12 generates the refresh request signal 22 at a fixed timing, and when the RAS / CAS generator 13 receives the refresh request signal 22, the address valid signal 20 causes the current memory access. Is executed. From the judgment result, if the memory access is not executed,
Immediately, and if a memory access is being performed,
After receiving the data acknowledge signal 26 and confirming the end of access, the refresh cycle signal 25 is output,
The RAS signal 23 and the CAS signal 24 are generated at the refresh timing (that is, the timing shown in FIG. 5B) for the DRAM.

When the refresh cycle signal 25 is output, the refresh request generator 12 negates the refresh request signal 22. Then, even when the CPU accesses the memory during execution of the refresh cycle, the data acknowledge generator 14 outputs the data acknowledge signal without stopping the CPU depending on the condition.
That is, when the data acknowledge generator 14 determines from the memory area determination signal 17 that the access area is other than DRAM and the read / write signal 21 is not a write access, as shown in the read cycle of the timing chart of FIG. Then, the data acknowledge signal is output at the same timing as the normal access.

On the other hand, when the access area is the DRAM area or when write access is made to other areas other than the DRAM area, as shown in the write cycle of the timing chart of FIG. The data acknowledge signal 26 is output at the timing when the access is started. That is, in this case, since the data acknowledge signal 26 is not sent to the CPU until the refresh operation is completed, the CPU continues to wait for the access end signal (data acknowledge signal) and the CPU is substantially stopped. . Further, the read / write signal control device 15 outputs only the read signal to the memory chip and does not output the write signal during the refresh cycle.

The reason for performing the above control is that the DRAM
To access to refresh and normally D
Since the RAS signal and the CAS signal, which are control signals, have different timings when accessing the RAM area, both operations cannot be performed at the same time, and during the refresh operation of the DRAM, the CPU is substantially stopped and the DRAM area is accessed. This is because it is necessary to stop normal access to. Of the read / write signals, the write signal is commonly input to the DRAM area and the other memory areas, so that write access cannot be performed during the refresh operation even in areas other than the DRAM. You really need to stop. It is also necessary to stop the write signal.

On the other hand, if the above conditions are not met, that is, if the access area is other than the DRAM area and no write access is made to other areas, the DRA
Even during the refresh operation of M, the CPU is not stopped. Therefore, unlike the conventional case where the operation of the CPU is uniformly stopped during the refresh operation, this embodiment can provide a memory control device in which the CPU is hardly stopped.

In the present embodiment, the DRAM has been described as an example, but the present invention is not limited to this, and the present invention can be applied to all dynamic memories including pseudo SRAM and the like.

Although the write signal has been described as an example of the signal input to the DRAM area and the other areas, the signal is not limited to this.

[0026]

According to the present invention, it is possible to reduce the CPU wait state even during the DRAM refresh cycle, reduce the overhead of the memory system, and realize a high-speed memory system, and its practical effects are great.

[Brief description of drawings]

FIG. 1 is a system configuration diagram using a memory control device of the present invention.

FIG. 2 is a configuration diagram of a memory control device according to an embodiment of the present invention.

FIG. 3 is a DRAM in the memory control device of the present invention.
Refresh timing diagram

FIG. 4 is a block diagram of a conventional memory control device.

FIG. 5 is a timing diagram of a RAS signal and a CAS signal.

FIG. 6 is a DRAM refresh timing diagram in a conventional memory control device.

[Explanation of symbols]

 1 semiconductor chip 2 CPU 3 memory control device 5 ROM, RAM 6 DRAM 7 SRAM 8 data bus 9 address bus 10 address decoder 11 chip select generation device 12 refresh request generation device 13 RAS / CAS generation device 14 data acknowledge generation device 15 read / Write signal controller 16 Address data 17 Memory area judgment signal 18 DRAM area judgment signal 19 Chip select signal 20 Address valid signal 21 Read / write signal 22 Refresh request signal 23 RAS signal 24 CAS signal 25 Refresh cycle signal 26 Data acknowledge signal 27 Memory Read / write signal 107 Bus usage right request signal generator 116 Bus release request signal 117 Bus release signal 118 Refresh cycle Start request signal

Claims (3)

[Claims] 1. A refresh control signal generation unit for controlling a refresh operation of a dynamic memory, a central processing unit control unit for substantially controlling the operation of a central processing unit, a dynamic memory region and other regions. And a signal control unit for controlling a signal commonly input to, and when the dynamic memory area is accessed, the central processing unit control unit substantially stops the operation of the central processing unit. When performing a refresh operation using the refresh control signal generating section and inputting a common signal to the dynamic memory area and an area other than the dynamic memory area, the central processing unit control section performs central processing. By substantially stopping the operation of the arithmetic processing unit and substantially stopping the input operation of the common signal by the signal controller, the refresh control signal generator is used. A memory control device performing a refresh operation, and in other cases, the refresh operation is performed without stopping the operation of the central processing unit and the signal input operation. 2. A refresh control signal generator for controlling a refresh operation of a dynamic memory, and a data acknowledge generator for generating a data acknowledge signal indicating the end of access to the memory area to the central processing unit.
A write signal control unit for controlling a write signal commonly input to the dynamic memory region and the other regions, and when accessing the dynamic memory region, a data acknowledge from the data acknowledge generation unit By substantially stopping the operation of the central processing unit by stopping the signal,
When the refresh operation is performed by the refresh control signal generator and the write signal is input to an area other than the dynamic memory area, the operation of the central processing unit is substantially stopped by using the data acknowledge generator. At the same time, the write signal control unit substantially stops the input operation of the write signal and the refresh control signal generation unit performs the refresh operation. In other cases, the operation of the central processing unit and the signal A memory control device characterized by performing a refresh operation without stopping an input operation. 3. An address decoder for determining which area is accessed by the central processing unit based on an address sent from the central processing unit, an output value of the address decoder and the central processing unit. From the address valid signal indicating the start of access from, the chip select generator that outputs a chip select signal to the memory in the area to be accessed, a refresh request generator that outputs a refresh request signal at a fixed timing, The output value of the address decoder, the address valid signal, the refresh request signal, and a data acknowledge signal indicating the end of access are input, and when the refresh request signal is disabled, the output of the address decoder is a dynamic memory. Dynamic memory access when showing region When a memory control signal is generated at a timing and the refresh request signal is enabled, if there is a memory access that is currently being executed, the generation of a data acknowledge signal is awaited. If there is no memory access, the memory control is immediately performed at the dynamic memory refresh timing. A memory control signal generator that outputs a refresh cycle signal while generating a signal and further generating the memory control signal for dynamic memory refresh, an output value of the address decoder, the address valid signal, and the read / Write signal and the refresh cycle signal are input, a data acknowledge signal is generated according to the memory system of the access area when the refresh cycle period is not in progress, and a dynamic memory is generated when the refresh cycle period is in progress. Access the area At the same time, or when performing write access to another area, a data acknowledge signal is generated at the timing when access is started after the refresh is completed. In other cases, a data acknowledge signal is generated as in the case where the refresh cycle is not in progress. A memory having a data acknowledge generator and a write signal controller for inputting the read / write signal and the refresh cycle signal and for fixing the read / write signal to the memory system to the read signal and outputting the read signal during the refresh cycle. Control device.