JPH0865288A - Delay measuring system for pds transmission system - Google Patents

Abstract

PURPOSE: To suppress the increase of power consumption when measuring the delay time of a transmission line. CONSTITUTION: In the case of measuring the delay time of signal transmission to be performed between station inside equipment 1 and respective subscriber equipment 21-2m, a clock signal A outputted from a clock oscillator 5 for performing the signal transmission is subjected to 1/n frequenc division, the clocks of these clock signals B frequencydivided into the (n) stages are shifted one by one corresponding to the clock signal of the clock oscillator, (n) pieces of clock signals C1-Cn are generated, the respective count values of (n) pieces of clock signals are added and based on this added value, the delay time is measured. As a result, since respective counters 641-64n count the frequencydivided lowspeed clock signals, the power consumption at the respective counters is reduced so that the power consumption of the equipment 1 can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay measuring method in a PDS (passive double star) transmission system, and more particularly to a delay measuring method for reducing power consumption.

[0002]

2. Description of the Related Art Generally, in a PDS transmission system, one subscriber line terminating device and a plurality of subscriber devices are optically connected by a star coupler, and between the subscriber line terminating device and the plurality of subscriber devices. The main signal is transmitted and received.
Conventionally, in such a transmission system, when measuring the delay amount of a transmitted / received signal, a counter is directly operated using a clock of a transmission line, and a delay time is calculated based on the count value of this counter. ing. That is,
In the subscriber line terminating device (intra-station device), in order to receive the burst signal from each subscriber device in a time division manner, the delay time is measured by using the above-mentioned counter for each subscriber device and the delay time is measured. The transmission phase of the burst signal output from each subscriber device is adjusted using the measurement result.

[0003]

In such a delay measuring circuit of the intra-station device, since the counter is directly operated using the transmission line clock to calculate the delay time from the count value, the clock frequency of the transmission line is When the cost becomes higher, the counter has to perform the counting operation at a high speed, which causes a problem that the power consumption of the counter increases.

Therefore, it is an object of the present invention to measure the delay time without increasing the power consumption even if the frequency of the transmission line becomes high.

[0005]

In order to solve such a problem, the present invention provides a main signal terminal for transmitting a signal while optically connecting an intra-station device and a plurality of subscriber devices via a star coupler. A PD that includes a generation circuit and a clock oscillator that generates a clock signal for transmitting a signal in the station device, and that performs signal transmission between the station device and each subscriber device
In the S transmission system, a frequency dividing circuit for dividing the frequency of a clock signal output from the clock oscillator by n, and n clock signals by shifting the clock signal divided by n by 1 clock by the clock signal of the clock oscillator Is provided in an in-station device, a clock generation circuit for generating the clock signal, an n counter for inputting and counting each of these n clock signals, and an adder circuit for adding the count value of each of the n counters. is there. In addition, the main signal termination
A counter control circuit for controlling the start and stop of the n counters based on the measurement start instruction and the measurement end instruction from the generation circuit is provided.

[0006]

When measuring the delay time of the signal transmission performed between the in-station device and each subscriber device, the clock signal output from the clock oscillator for signal transmission is divided by n, and the divided clock signal is divided by n. Is shifted by one clock by the clock signal of the clock oscillator to generate n clock signals, each count value of these n clock signals is added, and the delay time is measured based on this added value. As a result, since each counter counts the divided low-speed clock signal, the power consumption of the device can be reduced. Further, the start and stop of the n counters are controlled based on the measurement start instruction and the measurement end instruction from the main signal terminating / generating circuit that transmits a signal to each subscriber device. As a result, the delay time can be accurately measured.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
The embodiment system shown in FIG. 1 is a PDS transmission system in which an intra-station device 1 which is a subscriber line terminating device and a plurality of subscriber devices 21 to 2m (m is an integer of 2 or more) are 1 to m star couplers. Optical connection is made by means of 3 and the intra-station device 1 and each subscriber device transmit a main signal via a star coupler 3.

The intra-station device 1 is composed of a main signal terminating / generating circuit 4, a transmission line clock oscillator 5, a delay measuring circuit 6, and a delay measurement value processing section 7. Delay measurement circuit 6
Is for measuring the delay time between the intra-station device 1 and the subscriber devices 21 to 2m. The frequency dividing circuit 61 and the shift register 6
2, counter control circuit 63, counters 641 to 64n,
And an adder circuit 65.

That is, the frequency dividing circuit 61 in the delay measuring circuit 6
Is the frequency f0 output from the transmission line clock oscillator 5.
Of the transmission clock signal A is input and frequency-divided by n, and the n-divided clock signal B is output to the shift register 62. At the same time, the shift register 62 outputs the n-divided clock signal B by 1 / f0 based on the transmission clock signal A. It outputs n clock signals C1 to Cn having a frequency f0 / n whose phases are shifted from each other. Therefore, this shift register 62 constitutes a clock generation circuit.

The n clock signals C1 to C
n is input to each of the n counters 641 to 64n, and is counted by each counter. Starting and stopping of the n counters are based on an instruction from the main signal termination / generation circuit 4. The control circuit 63 controls.
The adder circuit 65 uses these n counters 641-6.
Input each count value of 4n, add each count value,
The delay measurement value is output to the delay measurement value processing unit 7.

Next, the in-office device 1 and the subscriber devices 21 to 2m
The detailed operation of the delay measuring circuit 6 for measuring the delay time between and will be described. The main signal terminating / generating circuit 4 sends a delay measurement start instruction command to each subscriber unit and also issues a measurement start instruction to the counter control circuit 63. When the counter control circuit 63 receives the delay measurement start instruction from the main signal termination / generation circuit 9, it starts the counters 641 to 64n.
The counters 641 to 64n thus started receive the clock signals C1 to Cn, respectively, and start counting from "0".

Here, for example, the delay measurement response to the above-mentioned delay measurement start instruction is received by the main signal terminating / generating circuit 4 from a specific subscriber device 3j, and the main signal terminating / generating circuit 4 is received.
When the delay measurement end instruction is output from the counter control circuit 63, the counter control circuit 63 stops the counting operation of each of the counters 641 to 64n at the same time as receiving the delay measurement end instruction. The adder circuit 65 inputs the count values of the respective counters 641 to 64n at this time, adds them, and outputs them to the delay measurement value processing unit 7. That is, the output of the adder circuit 65 at this time indicates the number of clocks having a frequency corresponding to f0, and this value becomes the delay time to be obtained. That is, the delay time can be measured in units of the clock frequency f0 output from the transmission line clock oscillator 5.

As described above, the high-speed clock signal A of the frequency f0 output from the transmission path clock oscillator 5 is not directly counted, but the low-speed divided clocks C1 to Cn obtained by dividing the frequency of the clock signal A are counted. Since the delay time is measured by the counter, the power consumption in each of the counters 641 to 64n becomes small, and therefore the power consumption can be reduced as compared with the case where the delay measurement is directly performed with the clock of the transmission line frequency.

[0014]

As described above, according to the present invention, when measuring the delay time of the signal transmission performed between the in-station device and each subscriber device, the clock signal for performing the signal transmission in the in-station device is measured. Is divided by n, and this n-divided clock signal is shifted by one clock by the clock signal of the clock oscillator to generate n clock signals, and the count values of these n clock signals are added to obtain Since the delay time is measured based on the added value, each counter counts the divided low-speed clock signal, so that the power consumption of each counter is suppressed and therefore the power consumption of the device can be reduced. Further, since the start and stop of the n counters are controlled based on the measurement start instruction and the measurement end instruction from the main signal terminating / generating circuit that transmits signals to each subscriber device, the delay time can be accurately measured. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... In-station device, 21-2m ... Subscriber device, 3 ... Star coupler, 4 ... Main signal termination / generation circuit, 5 ... Transmission line clock oscillator, 6 ... Delay measuring circuit, 61 ... Dividing circuit, 62 ... Shift register , 63 ... Counter control circuit, 641 to 64
n ... Counter, 65 ... Adder circuit.

Claims (2)

[Claims] 1. A main signal terminating / generating circuit for transmitting a signal and a clock oscillator for generating a clock signal for transmitting a signal while optically connecting an in-station device and a plurality of subscriber devices via a star coupler. In a PDS transmission system in which the internal device is provided and the signal is transmitted between the internal device and each subscriber device, the frequency of the clock signal output from the clock oscillator is divided by n (n is an integer of 2 or more). A frequency dividing circuit, a clock generating circuit for generating n clock signals by shifting the clock signal divided by n by 1 clock by the clock signal of the clock oscillator, and inputting these n clock signals, respectively. Based on the output of the adder circuit, which is equipped with an n-counter for counting Delay measurement method in PDS transmission system, characterized by measuring the inner device and the transmission delay time between each subscriber device. 2. The delay measuring method in the PDS transmission system according to claim 1, wherein starting and stopping of the n counters are controlled based on a measurement start instruction and a measurement end instruction from the main signal termination / generation circuit. A delay measuring method in a PDS transmission system, characterized in that a counter control circuit is provided.