KR20050040289A - Input clock generating device of universal asynchronous receiver transmitter - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input clock generator of a general purpose asynchronous transceiver, and more particularly, to a technique for generating a desired baud rate by precisely controlling a clock frequency input to a universal asynchronous receiver transmitter (UART). Initiate. To this end, the present invention provides a constant obtained by setting two frequency division coefficients close to the input clock frequency of the UART corresponding to the available clock frequency, and combining two types of frequency division clocks calculated by the two frequency division coefficients at a constant ratio. By providing the UART with a clock whose average value of the period is an integer multiple of the UART input frequency, the error rate is minimized when transmitting and receiving data through the UART.

Description

Input clock generating device of Universal Asynchronous Receiver Transmitter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input clock generator of a universal asynchronous transceiver, and more particularly, to precisely control a clock frequency input to a universal asynchronous receiver transmitter (UART) to generate a desired baud rate. Technology.

In general, data transmission is achieved by configuring a modem between a transmitting end and a receiving end, respectively, to control each other's communication speed. At this time, the baud rate should be synchronized between both ends of the transmission and reception for smooth communication. Here, the baud rate is a unit of bps (bit per second) and represents a unit of how many bits per second to transmit data.

In particular, in order to generate an appropriate baud rate in a universal asynchronous receiver transmitter (UART), a clock having an integer multiple of 3.6864 MHz as an input frequency is required. Here, the UART is a device that performs communication between relatively low speed but mainly simple devices. In other words, UART transmits only one data at a time in ASCII code format without transmitting clock information.

However, a UART provided inside a System On Chip (SOC) such as a micro controller unit (MCU) cannot directly receive a clock having an integer multiple of 3.6864 MHz from the outside. Accordingly, when the frequency used in the system on a chip is not an integer multiple of the UART input frequency, an error occurs and thus there is a problem that an appropriate baud rate cannot be generated when transmitting and receiving data through the UART.

The present invention was created to solve the above problems, and in particular, sets two frequency division coefficients close to the input clock frequency of the UART corresponding to the available clock frequency, and calculates two types of frequency coefficients calculated by the two frequency division coefficients. Its purpose is to ensure that the average value of a given clock cycle, obtained by combining the divided clocks at a constant rate, is an integer multiple of the UART input frequency.

An input clock generator of a general-purpose asynchronous transceiver of the present invention for achieving the above object, the control counter for counting and outputting a specific clock; The first division coefficient, the second division coefficient, which is close to the input clock frequency of the general purpose asynchronous transceiver, is preset in response to an arbitrary clock frequency, and one of the first division coefficient and the second division coefficient is selected according to the counting value of the control counter. Output multiplexer; And calculating a sum of clock periods by combining clocks divided by the first division factor and the second division factor at a predetermined ratio, and outputting the calculated clock period to a general-purpose asynchronous transceiver when the average value of the calculated clock periods coincides with the input clock frequency. And a clock divider.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of an input clock generator of a general-purpose asynchronous transceiver according to the present invention.

The present invention includes a control counter 10, a multiplexer 20, and a clock divider 30.

First, the control counter 10 counts a clock applied from the clock divider 30 and outputs a selection control signal. A first division factor (eg, 13) and a second division which is close to the input clock frequency (eg, 3.6864 MHz) of the UART 40 corresponding to the clock frequency (eg, 48 MHz) available in the system. A coefficient (eg, 14) is preset to the input of the multiplexer 20. Therefore, the multiplexer 20 selects and outputs one of two frequency division coefficients close to the desired input clock frequency according to the counting value applied from the control counter 10.

The clock divider 30 combines two kinds of divided clocks calculated by the division coefficients applied from the multiplexer 20 at a predetermined ratio. In addition, the clock divider 30 outputs the average value of the combined clock cycles to the UART 40 when the averaged clock frequency becomes a desired input clock frequency. Here, the average value of the predetermined period calculated by the clock divider 30 is an integer multiple of the input clock frequency provided to the UART 40.

An operation process of the present invention having such a configuration will be described below with reference to the flowchart of FIG. 2.

For example, suppose that the frequency of the clock available in the clock generator is 48 MHz, and the frequency used as the input clock frequency of the UART 40 is 3.6864 MHz. Here, the clock frequency 48 MHz is about 13.0208 times that of 3.6864 MHz, which is the input clock frequency of the UART 40. Therefore, when the clock frequency 48 MHz is divided by 13, the clock frequency is 3.89231 MHz, which has a desired error rate of 3.6864 MHz.

Accordingly, the frequency division coefficient closest to the desired input clock frequency 3.6864 MHz is set to 13,14, and these two frequency division coefficients are used as the inputs of the multiplexer 20. Accordingly, the present invention generates an input clock frequency of the UART 40 by combining a clock divided by 14 with a clock frequency of 48 MHz for each of 47 clocks divided by 13, and the average of the 48 clock frequencies generated is 3.6864 MHz. .

The operation process of the present invention is expressed by the following equation.

① (1/48 × 13) ㎲: One cycle of a clock divided by 48 MHz for 13 minutes.

(1/48 × 14) ㎲: One cycle of the clock divided by 48 MHz for 14 minutes.

③ ① × 47 + ②: Sum of 48 clock cycles combining ① and ② clocks.

④ ③ ÷ 48: Average period of the 48 combined clocks.

That is, the division coefficients 13 and 14 which are closest to the input clock frequencies of the desired UART 40 are preset as the input coefficients of the multiplexer 20. The control counter 10 counts up to 48 clocks for selecting the division coefficients according to the clock applied from the clock divider 30 (step 100).

The multiplexer 20 determines whether the counting value of the control counter 10 is greater than or equal to an arbitrary value 48 (step 200), and selects the division factor 13 until the counting value of the control counter 10 becomes 47. To print. Subsequently, when the counting value of the control counter 10 reaches 48, the multiplexer 20 selects and outputs the division factor 14.

Accordingly, when the division factor applied from the multiplexer 20 is 13, the clock divider 30 multiplies the clock frequency 48 MHz by the 13 divided by 47 and outputs the result. (Step 300), and the clock divider 30 If the frequency division coefficient applied from the multiplexer 20 is 14, the clock frequency 48MHz is divided by 14 and outputs once. (Step 400) Finally, the clock divider 30 divides one clock frequency by dividing the clock frequency by 48MHz 13 times. Multiplied by 47, adds one cycle of the clock divided by 48 MHz of the clock frequency (step 500).

Therefore, dividing this value (3) by 48 and taking the inverse yields the average frequency of the combined 48 clocks. (Step 600) This average frequency is 3.6864 MHz, which corresponds to the input frequency of the UART 40.

That is, according to the present invention, the average period of the input clock input to the UART 40 is 48, and the error accumulated at each average period of the 48 clocks can be finally corrected.

As described above, the present invention provides an effect of reducing the number of clocks generated by using a clock divider capable of correcting an error at regular intervals and minimizing an error when transmitting and receiving data through the UART.

1 is a block diagram of a clock generator of a general-purpose asynchronous transceiver according to the present invention.

2 is a flow chart for explaining the operation of the present invention.

Claims (3)

A control counter counting and outputting a specific clock; The first division factor and the second division factor, which are close to the input clock frequencies of the general purpose asynchronous transceiver, are preset in correspondence to an arbitrary clock frequency, and any one of the first division factor and the second division factor is determined according to a counting value of the control counter. A multiplexer which selects and outputs one; And The sum of clock periods is calculated by combining clocks divided by the first division coefficient and the second division coefficient at a predetermined ratio, and when the average value of the calculated clock periods coincides with the input clock frequency, the general purpose asynchronous transceiver An input clock generator of a general-purpose asynchronous transceiver, characterized by comprising a clock divider for outputting to a. The apparatus of claim 1, wherein the average value of the clock periods calculated by the clock divider is an integer multiple of the input clock frequency. The clock divider of claim 1 or 2, wherein the clock divider outputs a predetermined number of clocks divided by the first division coefficient when the counting value of the control counter is less than or equal to a predetermined value, and the counting value of the control counter is increased. The input clock generator of the general-purpose asynchronous transceiver, characterized in that for outputting a clock divided by the second division coefficient when more than a predetermined value.