JPH0864745A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0864745A JPH0864745A JP21790094A JP21790094A JPH0864745A JP H0864745 A JPH0864745 A JP H0864745A JP 21790094 A JP21790094 A JP 21790094A JP 21790094 A JP21790094 A JP 21790094A JP H0864745 A JPH0864745 A JP H0864745A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- lead frame
- mounting surface
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止タイプの半導
体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed type semiconductor device.
【０００２】[0002]
【従来の技術】従来の樹脂封止タイプの半導体装置は、
例えば実公昭６１−２０７７０号公報に開示されたよう
なものがある。これは、半導体チップと、該半導体チッ
プを搭載しかつ該半導体チップに導通するリードフレー
ムと、前記半導体チップが搭載された面に設けられ該半
導体チップを被覆する樹脂部を有するものである。そし
て前記半導体チップが搭載された裏面側は、前記リード
フレームが露出した状態を成し、さらに該リードフレー
ム露出面において前記半導体チップが搭載された部分が
低く、その周辺部が高くなるように段差が形成されてい
る。そして該段差により、前記半導体チップの放熱性が
確保されたものである。2. Description of the Related Art Conventional resin-sealed semiconductor devices are
For example, there is one disclosed in Japanese Utility Model Publication No. 61-20770. This has a semiconductor chip, a lead frame on which the semiconductor chip is mounted and which is electrically connected to the semiconductor chip, and a resin portion which is provided on the surface on which the semiconductor chip is mounted and covers the semiconductor chip. The back surface side on which the semiconductor chip is mounted has a state in which the lead frame is exposed, and a step is formed such that a portion where the semiconductor chip is mounted on the exposed surface of the lead frame is low and a peripheral portion thereof is high. Are formed. The step ensures the heat dissipation of the semiconductor chip.
【０００３】ここで図４には、従来の半導体装置５０を
基板６０に実装する場合の接合部の拡大断面図を示す。
図例のように当該装置５０実装時は、基板６０に設けら
れた接続端子６１上にリードフレーム５２露出面が位置
するように当該装置５０を配置し、前記接続端子６１表
面と前記リードフレーム５２露出面を半田６２付けによ
り接合する。すなわちリードフレーム５２露出面と接続
端子６１表面との間及びその周囲に半田６２を溶融、流
入させて、当該装置５０と基板６０を接合する。FIG. 4 shows an enlarged cross-sectional view of a joint portion when the conventional semiconductor device 50 is mounted on the substrate 60.
As shown in the drawing, when the device 50 is mounted, the device 50 is arranged so that the exposed surface of the lead frame 52 is located on the connection terminal 61 provided on the substrate 60, and the surface of the connection terminal 61 and the lead frame 52 are arranged. The exposed surface is joined by soldering 62. That is, the solder 62 is melted and caused to flow between the exposed surface of the lead frame 52 and the surface of the connection terminal 61 and the periphery thereof to bond the device 50 and the substrate 60.
【０００４】また図５には、例えば半導体チップ５１を
リードフレーム５２に搭載するダイボンディング工程、
あるいは半導体チップ５１とリードフレーム５２との導
通を確保するワイヤボンディング工程等の組立工程にお
ける当該装置５０の構成を表す概略図を示す。図例のよ
うに当該装置５０のリードフレーム５２には、例えばハ
ーフエッチング若しくはコイニング加工により形成され
た段差が、半導体チップ５１が搭載される裏面側に設け
られている。そのため組立工程においては、該段差の形
状に合わせた治具６３を用いて、リードフレーム５２を
下方より支持した状態で作業を行う必要がある。また半
導体チップ５１を樹脂で被覆するモールド工程において
も、同様の治具を用いる必要がある。Further, FIG. 5 shows a die bonding process for mounting the semiconductor chip 51 on the lead frame 52, for example.
Alternatively, a schematic diagram showing the configuration of the device 50 in an assembly process such as a wire bonding process for ensuring electrical continuity between the semiconductor chip 51 and the lead frame 52 is shown. As shown in the figure, the lead frame 52 of the device 50 is provided with a step formed by, for example, half etching or coining on the back surface side on which the semiconductor chip 51 is mounted. Therefore, in the assembly process, it is necessary to perform the work with the lead frame 52 supported from below using a jig 63 that matches the shape of the step. Further, it is necessary to use the same jig also in the molding step of covering the semiconductor chip 51 with the resin.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら上述の装
置５０を基板６０へ実装する場合、リードフレーム５２
露出面と接続端子６１表面が面接触し、互いの面の間及
びその周囲に半田６２を溶融、流入させて接合する。そ
のため半田６２の充填量が少なく、実装した基板６０に
反りが発生した場合に、接合部にクラックが生じてしま
う可能性がある。故に基板実装時の信頼性の低下の一因
となっている。さらに上述の装置５０の組立工程におい
ては、リードフレーム５２の段差に対応する治具６３が
必要である。また該段差の形状が異なる場合、その都度
段取り替え等の作業が必要であり、生産性が高いとは言
えない。よって本発明においては、基板実装時の信頼性
を向上させ、かつ生産性の高い半導体装置の提供を目的
とする。However, when the above-described device 50 is mounted on the substrate 60, the lead frame 52 is used.
The exposed surface and the surface of the connection terminal 61 are in surface contact with each other, and the solder 62 is melted and flowed into and around the mutual surfaces to join them. Therefore, when the amount of the solder 62 filled is small and the mounted substrate 60 is warped, cracks may occur at the joint portion. Therefore, it is one of the causes of lowering the reliability at the time of board mounting. Further, the jig 63 corresponding to the step of the lead frame 52 is required in the assembly process of the device 50 described above. Further, when the shape of the step is different, work such as setup change is required each time, and the productivity cannot be said to be high. Therefore, it is an object of the present invention to provide a semiconductor device having improved reliability when mounted on a substrate and high productivity.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するために案出されたもので、半導体チップ１１と、こ
の半導体チップ１１を搭載しかつ該半導体チップ１１上
の電気端子と導通するためのリードフレーム１２と、こ
のリードフレーム１２の前記半導体チップ１１が搭載さ
れた面側のみに設けられかつ前記半導体チップ１１を被
覆するための封止樹脂部１３とを備えるとともに、前記
リードフレーム１２の前記半導体チップ１１が搭載され
た面の裏面側は、当該装置１０を基板２０に実装するた
めの装置実装面１２ａが形成された半導体装置１０にお
いて、以下のように構成されたものである。該装置実装
面１２ａは、前記基板２０側に向けて突出した突起部１
４が設けられる。そして当該装置１０を前記基板２０に
実装する際に、前記装置実装面１２ａは前記基板２０と
の間に前記突起部１４の突出量に応じた中空部２３を有
し、かつ前記装置実装面１２ａと前記基板２０に設けら
れた接続端子２１との間の中空部２３に半田２２が充填
される状態を成すものとする。The present invention has been devised in order to achieve the above-mentioned object, and it is electrically connected to a semiconductor chip 11, the semiconductor chip 11 mounted on the semiconductor chip 11, and an electric terminal on the semiconductor chip 11. And a sealing resin portion 13 provided only on the surface of the lead frame 12 on which the semiconductor chip 11 is mounted and for covering the semiconductor chip 11, and the lead frame 12 The rear surface side of the surface on which the semiconductor chip 11 is mounted is configured as follows in the semiconductor device 10 in which the device mounting surface 12a for mounting the device 10 on the substrate 20 is formed. The device mounting surface 12a has a protrusion 1 protruding toward the substrate 20 side.
4 are provided. When the device 10 is mounted on the substrate 20, the device mounting surface 12a has a hollow portion 23 corresponding to the protrusion amount of the protrusion 14 between the device mounting surface 12a and the substrate 20, and the device mounting surface 12a. It is assumed that the hollow portion 23 between the connection terminal 21 provided on the board 20 and the connection terminal 21 is filled with the solder 22.
【０００７】また前記突起部１４は、前記リードフレー
ム１２の外周端縁に設けられたものであってもよい。こ
のとき前記突起部１４先端の形状が鋭角を成す状態であ
るものとする。The protrusion 14 may be provided on the outer peripheral edge of the lead frame 12. At this time, it is assumed that the shape of the tip of the protrusion 14 forms an acute angle.
【０００８】[0008]
【作用】上記構成によれば、当該装置１０を基板２０に
実装する場合は、装置実装面１２ａと該基板２０との間
に突起部１４の突出量に応じた中空部２３が確保され
る。そして装置実装面１２ａと基板２０に設けられた接
続端子２１との間の中空部２３のみに半田２２が充填さ
れる。これにより該半田２２の充填量が豊富な状態で、
当該装置１０と基板２０が接合される。また装置実装面
１２ａの半導体チップ１１が搭載された裏面部分と基板
２０との間の中空部２３は、半田２２が充填されない。
従って中空部２３による空間が確保され、半導体チップ
１１の放熱性は良好となり、また半田２２付けによるフ
ラックス残渣を確実に除去することができる。また突起
部１４による中空部２３のため、リードフレーム１２の
装置実装面１２ａ側の段差が不要となるので、当該装置
１０の組立工程においては、該リードフレーム１２を平
面板状のもので下方から支えることにより作業が実施で
きる。According to the above structure, when the device 10 is mounted on the substrate 20, the hollow portion 23 is secured between the device mounting surface 12a and the substrate 20 according to the amount of protrusion of the protrusion 14. Then, the solder 22 is filled only in the hollow portion 23 between the device mounting surface 12a and the connection terminal 21 provided on the substrate 20. As a result, in a state where the filling amount of the solder 22 is abundant,
The device 10 and the substrate 20 are bonded. Further, the solder 22 is not filled in the hollow portion 23 between the substrate 20 and the back surface portion of the device mounting surface 12a on which the semiconductor chip 11 is mounted.
Therefore, the space by the hollow portion 23 is secured, the heat dissipation of the semiconductor chip 11 is improved, and the flux residue due to the solder 22 attachment can be reliably removed. Further, since the hollow portion 23 formed by the protruding portion 14 eliminates the need for a step on the device mounting surface 12a side of the lead frame 12, in the assembly process of the device 10, the lead frame 12 is a flat plate-shaped member from below. Work can be performed by supporting.
【０００９】一方突起部１４先端の形状が鋭角を成す場
合においては、該突起部１４先端が接続端子２１に点あ
るいは線接触の状態で当接するため、例えばに基板２０
に反りや凹凸が発生し接続端子２１の面精度が確保され
ていない場合であっても、確実な接続と接合が成され
る。On the other hand, when the tip of the protrusion 14 forms an acute angle, the tip of the protrusion 14 comes into contact with the connection terminal 21 in a point or line contact state.
Even if the surface accuracy of the connection terminal 21 is not ensured due to warpage or unevenness, reliable connection and bonding are achieved.
【００１０】[0010]
【実施例】以下、図面に基づき本発明に係わる半導体装
置について説明する。図１は、当該装置１０の構成の一
例を表す断面図を示す。図例の如く当該装置１０は、半
導体チップ１１と、この半導体チップ１１が搭載され、
かつ該半導体チップ１１上の電気端子と導通するための
リードフレーム１２と、このリードフレーム１２の前記
半導体チップ１１が搭載された面側のみに設けられ、か
つ前記半導体チップ１１を被覆するための封止樹脂部１
４より構成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an example of the configuration of the device 10. As shown in the figure, the device 10 has a semiconductor chip 11 and the semiconductor chip 11 mounted thereon.
Also, a lead frame 12 for conducting with an electric terminal on the semiconductor chip 11, and a seal provided only on the surface side of the lead frame 12 on which the semiconductor chip 11 is mounted and for covering the semiconductor chip 11. Stop resin part 1
It is composed of 4.
【００１１】リードフレーム１２は、半導体チップ１１
を搭載するダイパッド１２ｂと、半導体チップ１１上の
電気端子と接続ワイヤ１５を介して導通が確保されてい
る外部リード１２ｃより構成されている。またこのリー
ドフレーム１２は、半導体チップ１１が搭載された面の
裏面側、すなわち封止樹脂部１４が設けられた面と反対
側の面が、当該装置１０を基板２０に実装するための装
置実装面１２ａが形成されている。さら外部リード１２
ｃの外周端縁には、前期装置実装面１６より前期基板２
０側に突出した状態で、後述する加工バリにより形成さ
れた突起部１４が設けられている。The lead frame 12 is a semiconductor chip 11.
It is composed of a die pad 12b for mounting and an external lead 12c whose electrical continuity is ensured through an electric terminal on the semiconductor chip 11 and a connecting wire 15. Further, the lead frame 12 is mounted on the substrate 20 on the back surface side of the surface on which the semiconductor chip 11 is mounted, that is, on the surface opposite to the surface on which the sealing resin portion 14 is provided. The surface 12a is formed. External lead 12
At the outer peripheral edge of c, from the previous device mounting surface 16 to the previous substrate 2
A protruding portion 14 formed by a processing burr described later is provided in a state of protruding to the 0 side.
【００１２】当該装置１０を基板２０に実装する場合
は、該基板２０に設けられた接続端子２１上に外部リー
ド１２ｂが位置するように配置される。このとき突起部
１４先端が、接続端子２１と当接する状態を成す。よっ
て装置実装面１２ａと基板２０との間は、突起部１４の
突出量に応じた中空部２３が確保される。そして外部リ
ード１２ｂと接続端子２１の間の中空部２３には、当該
装置１０と基板２０を接合するための半田２２が溶融、
流入される。When the device 10 is mounted on the substrate 20, the external leads 12b are arranged so as to be positioned on the connection terminals 21 provided on the substrate 20. At this time, the tip of the protrusion 14 comes into contact with the connection terminal 21. Therefore, between the device mounting surface 12a and the substrate 20, the hollow portion 23 corresponding to the protrusion amount of the protrusion 14 is secured. Then, the solder 22 for joining the device 10 and the substrate 20 is melted in the hollow portion 23 between the external lead 12b and the connection terminal 21,
Be flowed in.
【００１３】このように当該装置１０と基板２０は、外
部リード１２ｂと接続端子２１の間の中空部２３に半田
２２が充填され接合される。よって接合部の半田２２充
填量が豊富であり、接合力が大きくかつ耐クラック性の
高い実装が成される。またダイパッド１２ｂと基板２０
との間は、中空部２３による空間が確保されているた
め、該ダイパッド１２ｂに搭載された半導体チップ１１
の放熱性が良好となる。さらに該中空部２３のため当該
装置１０実装時の洗浄が十分に行うことができ、半田２
２付けによるフラックス残渣を確実に除去することがで
きる。さらに突起部１４先端が接続端子２１に点あるい
は線接触の状態で当接するため、例えばに基板２０に反
りが発生し接続端子２１の面精度が確保されていない場
合であっても、確実な接続と接合が成される。In this way, the device 10 and the substrate 20 are joined by filling the hollow portion 23 between the external lead 12b and the connection terminal 21 with the solder 22. Therefore, the amount of the solder 22 filled in the joint portion is abundant, and the mounting force is large and the crack resistance is high. In addition, the die pad 12b and the substrate 20
Since a space is secured by the hollow portion 23 between the semiconductor chip 11 and the semiconductor chip 11 mounted on the die pad 12b.
The heat dissipation property of is improved. Furthermore, because of the hollow portion 23, sufficient cleaning can be performed when the device 10 is mounted.
It is possible to reliably remove the flux residue due to the attachment. Further, since the tip of the protrusion 14 abuts on the connection terminal 21 in a point or line contact state, even if the surface accuracy of the connection terminal 21 is not ensured even if the substrate 20 is warped, for example, a reliable connection is ensured. Is joined with.
【００１４】ここで上述した図１の半導体装置１０の組
立工程について説明する。図２は、当該装置１０のリー
ドフレーム１２の平面図を表すもので、該リードフレー
ム１２はダイパッド１２ｂと外部リード１２ｃとが枠１
２ｄと共に一枚の金属板より形成されている。そしてダ
イボンディング工程においてダイパッド１２ｂ上に半導
体チップ１１が搭載、固着され、ワイヤボンディング工
程において半導体チップ１１上の電気端子と外部リード
１２ｃとの導通が確保される。その後モールド工程にお
いて、図中破線部１３ａの部分に封止樹脂部１３が形成
される。The assembly process of the semiconductor device 10 shown in FIG. 1 will be described below. FIG. 2 shows a plan view of the lead frame 12 of the apparatus 10. The lead frame 12 includes a die pad 12b and external leads 12c in a frame 1.
It is formed of a single metal plate together with 2d. Then, in the die bonding step, the semiconductor chip 11 is mounted and fixed on the die pad 12b, and in the wire bonding step, electrical continuity between the electric terminals on the semiconductor chip 11 and the external leads 12c is secured. After that, in the molding step, the sealing resin portion 13 is formed in the portion of the broken line portion 13a in the figure.
【００１５】次にリードフレーム１２端縁の切断、すな
わちダイパッド１２ｂ及び外部リード１２ｃから枠１２
ｄを切断して分離を行う。このときの切断方向は、半導
体チップ１１搭載面側から、その反対面すなわち装置実
装面１２ａ側へ向かって行われるものとする。この切断
によりリードフレーム１２の切断面、すなわち外部リー
ド１２ｃの端縁に、前記装置実装面１２ａ側へ突出した
加工バリが形成される。つまりリードフレーム１２を切
断する方向とその切断力を制御することにより、所望す
る大きさの加工バリが形成され、すなわち当該装置１０
の突起部１４を形成することができる。従って、この突
起部１４は非常に容易に形成される。Next, the edge of the lead frame 12 is cut, that is, from the die pad 12b and the external lead 12c to the frame 12.
Cut d to separate. The cutting direction at this time is from the mounting surface side of the semiconductor chip 11 toward the opposite surface, that is, the device mounting surface 12a side. By this cutting, a processing burr protruding toward the device mounting surface 12a is formed on the cutting surface of the lead frame 12, that is, the edge of the external lead 12c. That is, by controlling the cutting direction of the lead frame 12 and the cutting force thereof, a processing burr having a desired size is formed, that is, the device 10 concerned.
The protrusions 14 can be formed. Therefore, the protrusion 14 is very easily formed.
【００１６】またダイパッド１２ｂと外部リード１２ｃ
は、同一平面上で一枚の金属板より形成されたものであ
る。よって当該装置１０の組立工程、例えばダイボンデ
ィング工程あるいはワイヤボンディング工程等において
は、平面板状のものによりダイパッド１２ｂ及び外部リ
ード１２ｃ、すなわちダイボンディングあるいはワイヤ
ボンディングを行う箇所を下方から支えることにより、
作業が可能となる。従って組立工程においては、特殊な
治具を必要としない。Further, the die pad 12b and the external lead 12c
Is formed of a single metal plate on the same plane. Therefore, in the assembly process of the device 10, for example, the die bonding process or the wire bonding process, by supporting the die pad 12b and the external lead 12c, that is, the place where the die bonding or the wire bonding is performed, from below from the flat plate shape,
Work becomes possible. Therefore, no special jig is required in the assembly process.
【００１７】図３には、他の実施例の構成を表す断面図
を示す。尚、図例は超小型の半導体装置に本発明を実施
した場合の例である。図例の半導体装置３０は、半導体
チップ３１と、リードフレーム３２と、封止樹脂部３３
より構成されるものである。半導体チップ３１は、断面
が凸形状のリードフレーム３２の片面側に接着テープ３
６を介して搭載されている。また半導体チップ３１上の
電気端子とリードフレーム３２は、接続ワイヤ３５を介
して導通が確保されている。さらにリードフレーム３２
の半導体チップ３１が搭載されている側の面は、封止樹
脂部３３により被覆され、この封止樹脂部３３が設けら
れた面の裏面側は、当該装置１０を基板４０に実装する
ための装置実装面３２ａが形成されている。またこの装
置実装面３２ａの外周端縁には、突起部３４が該装置実
装面３２ａ側に突出した状態で設けられている。このよ
うに構成したものであっても、上述の実施例と同様の効
果を奏することは、言うまでもない。FIG. 3 is a sectional view showing the structure of another embodiment. The example shown in the figure is an example in which the present invention is applied to an ultra-small semiconductor device. The semiconductor device 30 of the illustrated example includes a semiconductor chip 31, a lead frame 32, and a sealing resin portion 33.
It is composed of The semiconductor chip 31 has an adhesive tape 3 on one side of a lead frame 32 having a convex cross section.
It is mounted via 6. The electrical connection between the electrical terminals on the semiconductor chip 31 and the lead frame 32 is ensured via the connection wires 35. Further lead frame 32
The surface on which the semiconductor chip 31 is mounted is covered with the sealing resin portion 33, and the rear surface side of the surface on which the sealing resin portion 33 is provided is for mounting the device 10 on the substrate 40. The device mounting surface 32a is formed. A protrusion 34 is provided on the outer peripheral edge of the device mounting surface 32a in a state of protruding toward the device mounting surface 32a. It is needless to say that even with such a configuration, the same effect as that of the above-described embodiment can be obtained.
【００１８】[0018]
【発明の効果】本発明は以上のように構成されているの
で、当該装置を基板に実装する際の接合部の半田充填量
が豊富である。従って接合力が大きくかつ耐クラック性
の高い実装が成される。またリードフレームと基板との
間の中空部により、半導体チップの良好な放熱性の確保
と、確実なフラックス残渣の除去が可能となる。すなわ
ち当該装置実装時の実装不良を低減し、実装の信頼性の
向上を図った。また当該装置の組立工程においては、特
殊な治具を必要としない。すなわち高い生産性を確保す
ることができた。さらに突起部先端の形状が鋭角を成す
場合においては、基板との当接が点あるいは線接触によ
り成されるため、該基板の面精度が確保されていなくと
も、確実で信頼性の高い接続と接合が成される。確実な
接続と接合が成される。つまり本発明においては、半導
体装置の基板実装時の信頼性の向上と、生産性の高い該
半導体装置の提供を実現した。Since the present invention is configured as described above, the solder filling amount at the joint portion when mounting the device on a substrate is abundant. Therefore, mounting with high bonding strength and high crack resistance is achieved. Further, the hollow portion between the lead frame and the substrate makes it possible to secure good heat dissipation of the semiconductor chip and reliably remove the flux residue. That is, the mounting failure at the time of mounting the device was reduced, and the reliability of mounting was improved. Further, no special jig is required in the assembly process of the device. That is, high productivity could be secured. Furthermore, when the shape of the tip of the protrusion forms an acute angle, the contact with the substrate is made by point or line contact, so that a reliable and highly reliable connection can be achieved even if the surface accuracy of the substrate is not ensured. A bond is made. A secure connection and bond is made. That is, according to the present invention, it is possible to improve reliability when mounting a semiconductor device on a substrate and provide the semiconductor device with high productivity.
【図１】本発明に係わる半導体装置の構成の一例を表す
断面図である。FIG. 1 is a cross-sectional view showing an example of a configuration of a semiconductor device according to the present invention.
【図２】図１の半導体装置のリードフレームを表す平面
図である。FIG. 2 is a plan view showing a lead frame of the semiconductor device of FIG.
【図３】他の実施例の構成を表す断面図である。FIG. 3 is a sectional view showing a configuration of another embodiment.
【図４】従来の半導体装置の基板実装時の接合部の拡大
断面図である。FIG. 4 is an enlarged cross-sectional view of a joint portion of a conventional semiconductor device when mounted on a substrate.
【図５】従来の半導体装置の組立工程における構成概略
図である。FIG. 5 is a schematic configuration diagram in a conventional semiconductor device assembling process.
１０ 半導体装置 １１ 半導体チップ １２ リードフレーム １２ａ 装置実装面 １３ 封止樹脂部 １４ 突起部 ２０ 基板 ２１ 接続端子 ２２ 半田 ２３ 中空部 DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor chip 12 Lead frame 12a Device mounting surface 13 Sealing resin part 14 Projection part 20 Substrate 21 Connection terminal 22 Solder 23 Hollow part
Claims (2)
端子と導通するためのリードフレームと、 該リードフレームの前記半導体チップが搭載された面側
に設けられ、かつ前記半導体チップを被覆するための封
止樹脂部とを備えるとともに、 前記リードフレームの前記半導体チップが搭載された面
の裏面側は、当該装置を基板に実装するための装置実装
面が形成された半導体装置において、 該装置実装面は、前記基板側に向けて突出した突起部が
設けられ、 当該装置を前記基板に実装する際に、前記装置実装面は
前記基板との間に前記突起部の突出量に応じた中空部を
有し、 かつ前記装置実装面と前記基板に設けられた接続端子と
の間の前期中空部に半田が充填されたことを特徴とする
半導体装置。1. A semiconductor chip, a lead frame on which the semiconductor chip is mounted and which is electrically connected to an electrical terminal on the semiconductor chip, and a surface of the lead frame on which the semiconductor chip is mounted are provided. Further, the semiconductor chip is provided with a sealing resin portion for covering the semiconductor chip, and a device mounting surface for mounting the device on a substrate is formed on the back surface side of the surface of the lead frame on which the semiconductor chip is mounted. In the semiconductor device, the device mounting surface is provided with a protrusion projecting toward the substrate side, and when the device is mounted on the substrate, the device mounting surface is disposed between the substrate and the protrusion. A semiconductor device having a hollow portion corresponding to the protruding amount of the above, and having a hollow portion previously filled between the device mounting surface and the connection terminal provided on the substrate with solder.
周端縁の前記実装面側に設けられ、かつ前記突起部先端
の形状が鋭角を成す状態であることを特徴とする請求項
１記載の半導体装置。2. The protrusion is provided on the mounting surface side of the outer peripheral edge of the lead frame, and the shape of the tip of the protrusion is an acute angle. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21790094A JP3270883B2 (en) | 1994-08-19 | 1994-08-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21790094A JP3270883B2 (en) | 1994-08-19 | 1994-08-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0864745A true JPH0864745A (en) | 1996-03-08 |
| JP3270883B2 JP3270883B2 (en) | 2002-04-02 |
Family
ID=16711522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21790094A Expired - Fee Related JP3270883B2 (en) | 1994-08-19 | 1994-08-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3270883B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194778B1 (en) * | 1996-08-16 | 2001-02-27 | Sony Corporation | Semiconductor package with improved cross talk and grounding, and method of manufacturing same |
| CN104170109A (en) * | 2012-12-14 | 2014-11-26 | 旭化成微电子株式会社 | Magnetic sensor, magnetic sensor device, and magnetic senor manufacturing method |
| JP2017117825A (en) * | 2015-12-21 | 2017-06-29 | 日立オートモティブシステムズ株式会社 | Semiconductor package and semiconductor assembly |
-
1994
- 1994-08-19 JP JP21790094A patent/JP3270883B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194778B1 (en) * | 1996-08-16 | 2001-02-27 | Sony Corporation | Semiconductor package with improved cross talk and grounding, and method of manufacturing same |
| CN104170109A (en) * | 2012-12-14 | 2014-11-26 | 旭化成微电子株式会社 | Magnetic sensor, magnetic sensor device, and magnetic senor manufacturing method |
| JP2017117825A (en) * | 2015-12-21 | 2017-06-29 | 日立オートモティブシステムズ株式会社 | Semiconductor package and semiconductor assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3270883B2 (en) | 2002-04-02 |
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