JP2017117825A - Semiconductor package and semiconductor assembly - Google Patents

Semiconductor package and semiconductor assembly Download PDF

Info

Publication number
JP2017117825A
JP2017117825A JP2015248392A JP2015248392A JP2017117825A JP 2017117825 A JP2017117825 A JP 2017117825A JP 2015248392 A JP2015248392 A JP 2015248392A JP 2015248392 A JP2015248392 A JP 2015248392A JP 2017117825 A JP2017117825 A JP 2017117825A
Authority
JP
Japan
Prior art keywords
semiconductor
package
terminal
substrate
heat spreader
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015248392A
Other languages
Japanese (ja)
Other versions
JP6621321B2 (en
Inventor
壮志 五十嵐
Soji Igarashi
壮志 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Astemo Ltd
Original Assignee
Hitachi Automotive Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Automotive Systems Ltd filed Critical Hitachi Automotive Systems Ltd
Priority to JP2015248392A priority Critical patent/JP6621321B2/en
Publication of JP2017117825A publication Critical patent/JP2017117825A/en
Application granted granted Critical
Publication of JP6621321B2 publication Critical patent/JP6621321B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package or the like capable of improving reliability in solder connection life in a leadless package.SOLUTION: A package 100 includes a semiconductor chip 130; a mold resin 110 for sealing the semiconductor chip 130; and a terminal (a metal terminal 120, a terminal extension part 190) electrically connected to the semiconductor chip 130. The terminal includes: the metal terminal 120 arranged on the same plane as plane (an undersurface 101) of the mold resin 110 opposite to a printed board 170; and the terminal extension part 190 which extends from plane (the undersurface 121) of the metal terminal 120 opposite to the printed board 170 toward the printed board 170 and has elasticity.SELECTED DRAWING: Figure 1

Description

本発明は、半導体パッケージ及び半導体アセンブリに関する。   The present invention relates to a semiconductor package and a semiconductor assembly.

近年、電子機器の小型化に対応するために、電子機器に搭載される半導体装置を基板に高密度に実装することが要求され、それに伴って半導体装置の高機能化、小型化が進んでいる。上述の要求を満たすべく提案されている半導体装置パッケージの一つが、リードレスパッケージと呼ばれているものである（例えば、特許文献１参照）。特許文献１のパッケージは、パッケージ本体の周辺部に沿ってパッケージの下部に位置する金属端子を備えている。同時にこれらの金属端子はパッケージ本体の表面の下部と同一面上である。   In recent years, in order to cope with the downsizing of electronic devices, it has been required that semiconductor devices mounted on electronic devices be mounted on a substrate at high density, and accordingly, higher performance and downsizing of semiconductor devices are progressing. . One of the semiconductor device packages proposed to satisfy the above-described requirements is a so-called leadless package (see, for example, Patent Document 1). The package of Patent Document 1 includes metal terminals located at the bottom of the package along the periphery of the package body. At the same time, these metal terminals are flush with the lower part of the surface of the package body.

特許第4872683号公報Japanese Patent No.4872683

一方で、特許文献１に開示されるようなリードレスパッケージを基板に実装して使用する際に、パッケージと基板とのはんだ接続部に加わる熱的、機械的な変形応力が、はんだ接続寿命信頼性を低下させるという問題がある。   On the other hand, when a leadless package as disclosed in Patent Document 1 is mounted on a substrate and used, the thermal and mechanical deformation stress applied to the solder connection portion between the package and the substrate is a reliable solder connection life. There is a problem of reducing the sex.

ここで、パッケージ外周部から外側へガルウィング形状に延びている金属端子を有するＱＦＰ等の従来パッケージにおいては、金属端子が変形することではんだ接続部に加わる変形応力が緩和されるため、はんだ接続寿命信頼性への影響を小さくすることが出来た。しかし、リードレスパッケージでは、金属端子はパッケージ表面と同一平面に、端子表面を露出しているのみであり、変形応力を緩和することは出来ない。   Here, in a conventional package such as a QFP having a metal terminal extending in a gull wing shape from the outer periphery of the package to the outside, the deformation stress applied to the solder connection portion due to the deformation of the metal terminal is alleviated. The impact on reliability could be reduced. However, in the leadless package, the metal terminal only exposes the terminal surface in the same plane as the package surface, and the deformation stress cannot be reduced.

そこで本発明は、リードレスパッケージにおける、はんだ接続寿命信頼性を向上することができる半導体パッケージ及び半導体アセンブリを提供することを目的としている。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor package and a semiconductor assembly that can improve solder connection life reliability in a leadless package.

上記目的を達成するために、本発明は、半導体と、前記半導体を封止する封止部と、前記半導体に電気的に接続される端子と、を備え、前記端子は、基板に対向する前記封止部の面と同一面上に配置される第１部材と、前記基板に対向する前記第１部材の面から前記基板に向かって伸び、弾性を有する第２部材と、を有する。   In order to achieve the above object, the present invention includes a semiconductor, a sealing portion that seals the semiconductor, and a terminal that is electrically connected to the semiconductor, and the terminal faces the substrate. A first member disposed on the same plane as the surface of the sealing portion; and a second member that extends from the surface of the first member facing the substrate toward the substrate and has elasticity.

本発明によれば、リードレスパッケージにおける、はんだ接続寿命信頼性を向上することができる。上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。   ADVANTAGE OF THE INVENTION According to this invention, the solder connection lifetime reliability in a leadless package can be improved. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

本発明の第１の実施形態のパッケージの断面を示した図である。It is the figure which showed the cross section of the package of the 1st Embodiment of this invention. 本発明の第１の実施形態のパッケージを下面側から示した図である。It is the figure which showed the package of the 1st Embodiment of this invention from the lower surface side. 本発明の第２の実施形態のパッケージの断面を示した図である。It is the figure which showed the cross section of the package of the 2nd Embodiment of this invention. 本発明の第３の実施形態のパッケージの断面を示した図である。It is the figure which showed the cross section of the package of the 3rd Embodiment of this invention. 本発明の第４の実施形態のパッケージの断面を示した図である。It is the figure which showed the cross section of the package of the 4th Embodiment of this invention. 本発明の第５の実施形態のパッケージの断面を示した図である。It is the figure which showed the cross section of the package of the 5th Embodiment of this invention. 本発明の第６の実施形態のパッケージの断面を示した図である。It is the figure which showed the cross section of the package of the 6th Embodiment of this invention.

以下、図面を用いて、本発明の第１〜第６の実施形態による半導体パッケージ（以後パッケージと呼ぶ）の構成及び作用効果について説明する。なお、各図において、同一符号は同一部分を示す。   Hereinafter, the configuration and operational effects of semiconductor packages (hereinafter referred to as packages) according to first to sixth embodiments of the present invention will be described with reference to the drawings. In each figure, the same numerals indicate the same parts.

（第１の実施形態）
図1および図２に本発明の第１の実施形態によるパッケージ１００を示す。なお、図１は図２におけるＡ−Ａ断面図である。図２は本発明を適用したパッケージ１００の下面図である。 (First embodiment)
1 and 2 show a package 100 according to a first embodiment of the present invention. 1 is a cross-sectional view taken along line AA in FIG. FIG. 2 is a bottom view of the package 100 to which the present invention is applied.

パッケージ１００は、半導体チップ１３０を腐食から保護することを目的として設定（成形）したモールド樹脂１１０と、半導体チップ１３０の電気信号をパッケージ１００の外部と接続する金属端子１２０と、半導体チップ１３０と金属端子１２０の間を電気的に接続するワイヤ１５０と、半導体チップ１３０で生じる熱をパッケージ１００の外部に放熱するヒートスプレッダ１４０から成る。   The package 100 includes a mold resin 110 that is set (molded) for the purpose of protecting the semiconductor chip 130 from corrosion, a metal terminal 120 that connects an electrical signal of the semiconductor chip 130 to the outside of the package 100, and the semiconductor chip 130 and the metal. A wire 150 that electrically connects the terminals 120 and a heat spreader 140 that radiates heat generated in the semiconductor chip 130 to the outside of the package 100 are included.

金属端子１２０の下面１２１およびヒートスプレッダ１４０の下面１４１はパッケージ１００の下面１０１と同一平面に位置しており、リードレス構造のパッケージとなっている。金属端子１２０の側面１２２はパッケージ１００の側面１０２と同一平面に位置している。   The lower surface 121 of the metal terminal 120 and the lower surface 141 of the heat spreader 140 are located on the same plane as the lower surface 101 of the package 100, and form a leadless package. The side surface 122 of the metal terminal 120 is located on the same plane as the side surface 102 of the package 100.

また、金属端子１２０は下面１２１からパッケージ１００に対し垂直方向（図１の上下方向）に延びる端子延長部１９０と、結節部１９１で接続している。半導体チップ１３０はヒートスプレッダ１４０上に装着されている。パッケージ１００は端子延長部１９０およびヒートスプレッダ１４０において導電性接合部材１６０および１６１を介してプリント基板１７０上に設けられたランド１８０および１８１において電気的および機械的に接合されている。   In addition, the metal terminal 120 is connected to a terminal extension 190 extending from the lower surface 121 to the package 100 in the vertical direction (vertical direction in FIG. 1) by a knot 191. The semiconductor chip 130 is mounted on the heat spreader 140. The package 100 is electrically and mechanically joined to lands 180 and 181 provided on the printed circuit board 170 via conductive joining members 160 and 161 in the terminal extension 190 and the heat spreader 140.

換言すれば、パッケージ１００（半導体パッケージ）は、図１に示すように、半導体チップ１３０（半導体）と、半導体チップ１３０を封止するモールド樹脂１１０（封止部）と、半導体チップ１３０に電気的に接続される端子（金属端子１２０、端子延長部１９０）と、を備える。   In other words, the package 100 (semiconductor package) is electrically connected to the semiconductor chip 130 (semiconductor), the mold resin 110 (sealing part) that seals the semiconductor chip 130, and the semiconductor chip 130, as shown in FIG. Terminals (metal terminal 120, terminal extension 190) connected to the terminal.

詳細には、端子は、プリント基板１７０（基板）に対向するモールド樹脂１１０の面（下面１０１）と同一面上に配置される金属端子１２０（第１部材）と、プリント基板１７０に対向する金属端子１２０の面（下面１２１）からプリント基板１７０に向かって伸び、弾性を有する端子延長部１９０（第２部材）と、を有する。端子延長部１９０は、プリント基板１７０に対向する金属端子１２０の面（下面１２１）に垂直である。   Specifically, the terminals include a metal terminal 120 (first member) disposed on the same surface as the surface (lower surface 101) of the mold resin 110 facing the printed circuit board 170 (substrate), and a metal facing the printed circuit board 170. A terminal extension 190 (second member) extending from the surface (lower surface 121) of the terminal 120 toward the printed circuit board 170 and having elasticity. The terminal extension 190 is perpendicular to the surface (lower surface 121) of the metal terminal 120 that faces the printed circuit board 170.

本実施形態によれば、パッケージ１００の線膨張係数とプリント基板１７０の線膨張係数の差分に起因する変形応力が導電性接合部材１６０に印可された場合、端子延長部１９０は結節部１９１を基点として、端子下面１２１に対し水平方向に弾性変形が可能であるため、導電性接合部材１６０への変形応力を緩和することが可能である。前記効果により、はんだ接続寿命信頼性に優れたパッケージを実現することができる。   According to the present embodiment, when the deformation stress resulting from the difference between the linear expansion coefficient of the package 100 and the linear expansion coefficient of the printed circuit board 170 is applied to the conductive bonding member 160, the terminal extension 190 is based on the knot 191. As described above, since the elastic deformation in the horizontal direction with respect to the terminal lower surface 121 is possible, the deformation stress on the conductive bonding member 160 can be reduced. By the effect, a package having excellent solder connection life reliability can be realized.

なお、図１および図２で示した、４つの辺に端子を具備する半導体パッケージ（集積回路パッケージ）は例示的なものであり、且つ本発明の方法は半導体パッケージの任意の数の辺（即ち、１つ、２つ、３つまたは４つ）に対して適用することが可能である。また、図1および図２において金属端子一列で例示しているが、本発明の方法は任意の金属端子列に対しても拡張可能である。本拡張の考え方は、以下図３〜７にも適用できる。   The semiconductor package (integrated circuit package) having terminals on the four sides shown in FIGS. 1 and 2 is an example, and the method of the present invention can be applied to any number of sides of the semiconductor package (ie, 1, 2, 3, or 4). 1 and 2 exemplify a single metal terminal row, the method of the present invention can be extended to any metal terminal row. The concept of this extension can also be applied to FIGS.

（第２の実施形態）
図３は本発明の第２の実施形態によるパッケージ１００Ａを示している。本実施形態では、導電性接合部材１６０Ａが金属端子１２０の下面１２１まで形成されている点が第１の実施形態と異なる。 (Second Embodiment)
FIG. 3 shows a package 100A according to the second embodiment of the present invention. This embodiment is different from the first embodiment in that the conductive bonding member 160A is formed up to the lower surface 121 of the metal terminal 120.

本実施形態では、パッケージ１００Ａは金属端子１２０の下面１２１、端子延長部１９０およびヒートスプレッダ１４０において導電性接合部材１６０Ａおよび１６１を介してプリント基板１７０上に設けられたランド１８０および１８１において電気的および機械的に接合される。   In the present embodiment, the package 100A is electrically and mechanically connected to lands 180 and 181 provided on the printed circuit board 170 via the conductive bonding members 160A and 161 in the lower surface 121 of the metal terminal 120, the terminal extension 190 and the heat spreader 140. Are joined together.

ここで、パッケージ１００Ａ（半導体パッケージ）及びプリント基板１７０（基板）は半導体アセンブリ１０を構成する。ランド１８０は、端子（金属端子１２０、端子延長部１９０）に対向する。端子延長部１９０（第２部材）とランド１８０は導電性接合部材１６０Ａで接続される。詳細には、導電性接合部材１６０Ａは、図３に示すように、端子延長部１９０に対向するランド１８０から金属端子１２０（第１部材）まで形成される。   Here, the package 100 </ b> A (semiconductor package) and the printed circuit board 170 (substrate) constitute the semiconductor assembly 10. The land 180 is opposed to the terminal (metal terminal 120, terminal extension 190). The terminal extension 190 (second member) and the land 180 are connected by a conductive bonding member 160A. Specifically, as shown in FIG. 3, the conductive bonding member 160 </ b> A is formed from the land 180 facing the terminal extension 190 to the metal terminal 120 (first member).

本実施形態によれば、金属端子１２０と導電性接合部材１６０Ａとの接続長が第１の実施形態の場合よりも長くすることができるため、はんだ接続寿命を更に長寿命化することが可能である。   According to this embodiment, since the connection length between the metal terminal 120 and the conductive bonding member 160A can be made longer than that in the first embodiment, the solder connection life can be further extended. is there.

（第３の実施形態）
図４は本発明の第３の実施形態によるパッケージ１００Ｂを示している。本実施形態では、導電性接合部材１６０Ｂが端子延長部１９０の下面１９２まで形成されている点が第１の実施形態と異なる。 (Third embodiment)
FIG. 4 shows a package 100B according to a third embodiment of the present invention. This embodiment is different from the first embodiment in that the conductive bonding member 160B is formed up to the lower surface 192 of the terminal extension 190.

本実施形態では、パッケージ１００Ｂは端子延長部１９０の下面１９２およびヒートスプレッダ１４０において導電性接合部材１６０Ｂおよび１６１を介してプリント基板１７０上に設けられたランド１８０および１８１において電気的および機械的に接合される。   In the present embodiment, the package 100B is electrically and mechanically bonded to the lower surface 192 of the terminal extension 190 and the lands 180 and 181 provided on the printed circuit board 170 via the conductive bonding members 160B and 161 on the heat spreader 140. The

換言すれば、導電性接合部材１６０Ｂは、図４に示すように、端子延長部１９０（第２部材）に対向するランド１８０から端子延長部１９０の先端まで形成される。端子延長部１９０の根元から先端までの部分が、導電性接合部材１６０Ｂで覆われていないため、弾性変形しやすい。   In other words, the conductive bonding member 160B is formed from the land 180 facing the terminal extension 190 (second member) to the tip of the terminal extension 190 as shown in FIG. Since the portion from the base to the tip of the terminal extension 190 is not covered with the conductive bonding member 160B, it is easily elastically deformed.

本実施形態によれば、導電性接合部材１６０Ｂにパッケージ１００Ｂの線膨張係数とプリント基板１７０の線膨張係数の差分に起因する変形応力が印可された場合、端子延長部１９０は金属端子１２０と端子延長部１９０との結節部１９１を基点として、端子下面１２１に対し水平方向に弾性変形が可能であるため、導電性接合部材１６０Ｂへの応力集中を緩和することが可能である。   According to the present embodiment, when the deformation stress resulting from the difference between the linear expansion coefficient of the package 100B and the linear expansion coefficient of the printed circuit board 170 is applied to the conductive bonding member 160B, the terminal extension 190 is connected to the metal terminal 120 and the terminal. Since it is possible to elastically deform the terminal lower surface 121 in the horizontal direction starting from the node portion 191 with the extension portion 190, stress concentration on the conductive bonding member 160B can be reduced.

（第４の実施形態）
図５は本発明の第４の実施形態によるパッケージ１００Ｃを示している。本実施形態では、端子延長部１９０Ｃの位置が第１の実施形態と異なる。 (Fourth embodiment)
FIG. 5 shows a package 100C according to a fourth embodiment of the present invention. In the present embodiment, the position of the terminal extension 190C is different from that of the first embodiment.

本実施形態では、金属端子１２０は金属端子の側面１２２と同一の平面に一辺を接し、かつ下面１２１からパッケージ１００Ｃに対し垂直方向に延びる端子延長部１９０Ｃと、結節部１９１で接続している。   In the present embodiment, the metal terminal 120 is connected to a terminal extension 190 </ b> C that extends in a direction perpendicular to the package 100 </ b> C from the lower surface 121 with one side being in contact with the same plane as the side surface 122 of the metal terminal.

換言すれば、端子延長部１９０Ｃ（第２部材）は、図５に示すように、半導体チップ１３０（半導体）と反対側の金属端子１２０（第１部材）の端に配置される。これにより、端子延長部１９０Ｃの成形が容易となる。   In other words, the terminal extension 190C (second member) is arranged at the end of the metal terminal 120 (first member) opposite to the semiconductor chip 130 (semiconductor), as shown in FIG. This facilitates the molding of the terminal extension 190C.

パッケージ１００Ｃは端子延長部１９０Ｃおよびヒートスプレッダ１４０において導電性接合部材１６０および１６１を介してプリント基板１７０上に設けられたランド１８０および１８１において電気的および機械的に接合される。   The package 100C is electrically and mechanically joined to lands 180 and 181 provided on the printed circuit board 170 via the conductive joint members 160 and 161 in the terminal extension 190C and the heat spreader 140.

本実施形態によれば、パッケージ１００Ｃの線膨張係数とプリント基板１７０の線膨張係数の差分に起因する変形応力が導電性接合部材１６０に印可された場合、端子延長部１９０Ｃは結節部１９１を基点として、端子下面１２１に対し水平方向に弾性変形が可能であるため、導電性接合部材１６０への変形応力を緩和することが可能である。   According to the present embodiment, when the deformation stress resulting from the difference between the linear expansion coefficient of the package 100C and the linear expansion coefficient of the printed circuit board 170 is applied to the conductive bonding member 160, the terminal extension 190C is based on the knot 191. As described above, since the elastic deformation in the horizontal direction with respect to the terminal lower surface 121 is possible, the deformation stress on the conductive bonding member 160 can be reduced.

（第５の実施形態）
図６は本発明の第５の実施形態によるパッケージ１００Ｄを示している。本実施形態では、端子延長部１９０Ｄの位置が第１の実施形態と異なる。 (Fifth embodiment)
FIG. 6 shows a package 100D according to a fifth embodiment of the present invention. In the present embodiment, the position of the terminal extension 190D is different from that of the first embodiment.

本実施形態では、金属端子１２０は金属端子１２０のヒートスプレッダ１４０側の側面１２３と同一の平面に一辺を接し、かつ下面１２１からパッケージ１００Ｄに対し垂直方向に延びる端子延長部１９０Ｄと、結節部１９１で接続している。   In the present embodiment, the metal terminal 120 includes a terminal extension 190D that is in contact with the same plane as the side surface 123 of the metal terminal 120 on the heat spreader 140 side and extends in a direction perpendicular to the package 100D from the lower surface 121, and a knot 191 Connected.

換言すれば、端子延長部１９０Ｄ（第２部材）は、図６に示すように、半導体チップ１３０側（半導体側）の金属端子１２０（第１部材）の端に配置される。これにより、端子延長部１９０Ｄの成形が容易となる。また、パッケージ１００Ｄをプリント基板１７０へ実装するのに必要な面積が小さくなる。   In other words, the terminal extension 190D (second member) is disposed at the end of the metal terminal 120 (first member) on the semiconductor chip 130 side (semiconductor side), as shown in FIG. Thereby, shaping | molding of terminal extension part 190D becomes easy. Further, an area necessary for mounting the package 100D on the printed circuit board 170 is reduced.

パッケージ１００Ｄは端子延長部１９０Ｄおよびヒートスプレッダ１４０において導電性接合部材１６０および１６１を介してプリント基板１７０上に設けられたランド１８０および１８１において電気的および機械的に接合される。   The package 100D is electrically and mechanically joined to lands 180 and 181 provided on the printed circuit board 170 via the conductive joint members 160 and 161 in the terminal extension 190D and the heat spreader 140.

本実施形態によれば、パッケージ１００Ｄの線膨張係数とプリント基板１７０の線膨張係数の差分に起因する変形応力が導電性接合部材１６０に印可された場合、端子延長部１９０Ｄは結節部１９１を基点として、端子下面１２１に対し水平方向に弾性変形が可能であるため、導電性接合部材１６０への変形応力を緩和することが可能である。   According to the present embodiment, when the deformation stress resulting from the difference between the linear expansion coefficient of the package 100D and the linear expansion coefficient of the printed circuit board 170 is applied to the conductive bonding member 160, the terminal extension 190D is based on the knot 191. As described above, since the elastic deformation in the horizontal direction with respect to the terminal lower surface 121 is possible, the deformation stress on the conductive bonding member 160 can be reduced.

（第６の実施形態）
図７は本発明の第６の実施形態によるパッケージ１００Ｅを示している。本実施形態では、パッケージ１００Ｅは、ヒートスプレッダ延長部１９５をさらに備え、ヒートスプレッダ延長部１９５とランド１８１は、導電性接合部材１６０を介して接合される点が第１の実施形態と異なる。 (Sixth embodiment)
FIG. 7 shows a package 100E according to a sixth embodiment of the present invention. In the present embodiment, the package 100E further includes a heat spreader extension 195, and the heat spreader extension 195 and the land 181 are different from those of the first embodiment in that the heat spreader extension 195 and the land 181 are bonded via the conductive bonding member 160.

本実施形態では、ヒートスプレッダ１４０は下面１４１からパッケージ１００Ｅに対し垂直方向に延びるヒートスプレッダ延長部１９５と、結節部１９６で接続している。   In the present embodiment, the heat spreader 140 is connected to the heat spreader extension 195 extending from the lower surface 141 in the direction perpendicular to the package 100E by a knot 196.

パッケージ１００Ｅは端子延長部１９０およびヒートスプレッダ延長部１９５において導電性接合部材１６０および１６１Ｅを介してプリント基板１７０上に設けられたランド１８０および１８１において電気的および機械的に接合されている。   The package 100E is electrically and mechanically bonded to lands 180 and 181 provided on the printed circuit board 170 via conductive bonding members 160 and 161E in the terminal extension 190 and the heat spreader extension 195.

換言すれば、パッケージ１００Ｅ（半導体パッケージ）は、図７に示すように、半導体チップ１３０（半導体）を搭載するヒートスプレッダ（ヒートスプレッダ１４０、ヒートスプレッダ延長部１９５）を備える。詳細には、ヒートスプレッダは、プリント基板１７０（基板）に対向するモールド樹脂１１０（封止部）の面（下面１０１）と同一面上に配置されるヒートスプレッダ１４０（第３部材）と、プリント基板１７０に対向するヒートスプレッダ１４０の面（１４１）からプリント基板１７０に向かって伸び、弾性を有するヒートスプレッダ延長部１９５（第４部材）と、を有する。   In other words, the package 100E (semiconductor package) includes a heat spreader (heat spreader 140, heat spreader extension 195) on which the semiconductor chip 130 (semiconductor) is mounted, as shown in FIG. Specifically, the heat spreader includes a heat spreader 140 (third member) disposed on the same surface as the surface (lower surface 101) of the mold resin 110 (sealing portion) facing the printed circuit board 170 (substrate), and the printed circuit board 170. And a heat spreader extension 195 (fourth member) that extends from the surface (141) of the heat spreader 140 facing the printed circuit board 170 toward the printed circuit board 170 and has elasticity.

本実施形態によれば、パッケージ１００Ｅの線膨張係数とプリント基板１７０の線膨張係数の差分に起因する変形応力が導電性接合部材１６０および１６１Ｅに印可された場合、端子延長部１９０は結節部１９１を基点として、また同時にヒートスプレッダ延長部１９５は結節部１９６を基点として、端子下面１２１に対し水平方向に弾性変形が可能であるため、導電性接合部材１６０および導電性接合部材１６１Ｅへの変形応力を緩和することが可能である。   According to the present embodiment, when the deformation stress resulting from the difference between the linear expansion coefficient of the package 100E and the linear expansion coefficient of the printed circuit board 170 is applied to the conductive bonding members 160 and 161E, the terminal extension 190 is connected to the knot 191. At the same time, the heat spreader extension 195 can be elastically deformed in the horizontal direction with respect to the lower surface 121 of the terminal, with the node 196 as a base point. Therefore, the deformation stress to the conductive bonding member 160 and the conductive bonding member 161E It can be mitigated.

なお、本発明は上記した実施形態に限定されるものではなく、様々な変形例が含まれる。例えば、上述した実施形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施形態の構成の一部を他の実施形態の構成に置き換えることが可能であり、また、ある実施形態の構成に他の実施形態の構成を加えることも可能である。また、各実施形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。   In addition, this invention is not limited to above-described embodiment, Various modifications are included. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to the one having all the configurations described. Further, a part of the configuration of an embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of an embodiment. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

上記実施形態において、金属端子１２０（第１部材）と端子延長部１９０（第２部材）は、例えば、一体に構成されるが、別体で構成されるようにしてもよい。この場合、金属端子１２０（第１部材）と端子延長部１９０（第２部材）は、互いに異なる部材で構成されるようにしてもよい。   In the above embodiment, the metal terminal 120 (first member) and the terminal extension 190 (second member) are configured integrally, for example, but may be configured separately. In this case, the metal terminal 120 (first member) and the terminal extension 190 (second member) may be configured by different members.

上記実施形態において、端子延長部１９０（第２部材）の形状は、例えば、棒状、板状等の柱状であるが、任意の形状であってもよい。   In the above embodiment, the terminal extension 190 (second member) has a columnar shape such as a rod shape or a plate shape, but may be any shape.

本発明の実施形態は、以下の態様であってもよい。   The following aspect may be sufficient as embodiment of this invention.

（１）半導体チップと、前記半導体チップの電気信号を外部に接続する金属端子１と、前記半導体チップで生じる熱を外部に放熱するヒートスプレッダと、を持ち、前記金属端子１の一面と前期ヒートスプレッダの一面はパッケージの一面と同一面上に位置するモールドパッケージにおいて、前記金属端子１から前記一面に対し垂直方向に延びる金属端子２を有することを特徴とするモールドパッケージ。   (1) It has a semiconductor chip, a metal terminal 1 for connecting an electric signal of the semiconductor chip to the outside, and a heat spreader for radiating heat generated in the semiconductor chip to the outside, and one surface of the metal terminal 1 and the previous heat spreader A mold package, wherein one surface has a metal terminal 2 extending in a direction perpendicular to the one surface from the metal terminal 1 in a mold package located on the same surface as the one surface of the package.

（２）（１）のモールドパッケージにおいて、前記垂直方向に延びる金属端子２は前記金属端子１上に有することを特徴とするモールドパッケージ。   (2) The mold package according to (1), wherein the metal terminal 2 extending in the vertical direction is provided on the metal terminal 1.

（３）（１）のモールドパッケージにおいて、前記垂直方向に延びる金属端子２は前記ヒートスプレッダ上に有することを特徴とするモールドパッケージ。   (3) The mold package according to (1), wherein the metal terminals 2 extending in the vertical direction are provided on the heat spreader.

１０…半導体アセンブリ
１００…半導体パッケージ（集積回路パッケージ）
１０１…半導体パッケージの下面
１０２…半導体パッケージの側面
１１０…モールド樹脂
１２０…金属端子
１２１…金属端子の下面
１２２…金属端子の側面
１３０…半導体チップ
１４０…ヒートスプレッダ
１４１…ヒートスプレッダの下面
１５０…ワイヤ
１６０…金属端子と接合する導電性接合部材
１６１…ヒートスプレッダと接合する導電性接合部材
１７０…基板
１８０…金属端子側のランド
１８１…ヒートスプレッダ側のランド
１９０…端子延長部
１９１…結節部 DESCRIPTION OF SYMBOLS 10 ... Semiconductor assembly 100 ... Semiconductor package (integrated circuit package)
DESCRIPTION OF SYMBOLS 101 ... Semiconductor package lower surface 102 ... Semiconductor package side surface 110 ... Mold resin 120 ... Metal terminal 121 ... Metal terminal lower surface 122 ... Metal terminal side surface 130 ... Semiconductor chip 140 ... Heat spreader 141 ... Heat spreader lower surface 150 ... Wire 160 ... Metal Conductive bonding member 161 bonded to the terminal ... conductive bonding member 170 bonded to the heat spreader ... substrate 180 ... land 181 on the metal terminal side ... land 190 on the heat spreader side ... terminal extension 191 ... knot portion

Claims (8)

半導体と、
前記半導体を封止する封止部と、
前記半導体に電気的に接続される端子と、を備え、
前記端子は、
基板に対向する前記封止部の面と同一面上に配置される第１部材と、
前記基板に対向する前記第１部材の面から前記基板に向かって伸び、弾性を有する第２部材と、を有する
ことを特徴とする半導体パッケージ。 Semiconductors,
A sealing portion for sealing the semiconductor;
A terminal electrically connected to the semiconductor,
The terminal is
A first member disposed on the same surface as the surface of the sealing portion facing the substrate;
And a second member having elasticity and extending from the surface of the first member facing the substrate toward the substrate. 請求項１に記載の半導体パッケージであって、
前記第２部材は、
前記半導体と反対側の前記第１部材の端に配置される
ことを特徴とする半導体パッケージ。 The semiconductor package according to claim 1,
The second member is
A semiconductor package, wherein the semiconductor package is disposed at an end of the first member opposite to the semiconductor. 請求項１に記載の半導体パッケージであって、
前記第２部材は、
前記半導体側の前記第１部材の端に配置される
ことを特徴とする半導体パッケージ。 The semiconductor package according to claim 1,
The second member is
A semiconductor package, wherein the semiconductor package is disposed at an end of the first member on the semiconductor side. 請求項１に記載の半導体パッケージであって、
前記半導体を搭載するヒートスプレッダをさらに備え、
前記ヒートスプレッダは、
前記基板に対向する前記封止部の面と同一面上に配置される第３部材と、
前記基板に対向する前記第３部材の面から前記基板に向かって伸び、弾性を有する第４部材と、を有する
ことを特徴とする半導体パッケージ。 The semiconductor package according to claim 1,
A heat spreader on which the semiconductor is mounted;
The heat spreader is
A third member disposed on the same surface as the surface of the sealing portion facing the substrate;
And a fourth member having elasticity and extending from the surface of the third member facing the substrate toward the substrate. 請求項１に記載の半導体パッケージであって、
前記第２部材は、
前記基板に対向する前記第１部材の面に垂直である
ことを特徴とする半導体パッケージ。 The semiconductor package according to claim 1,
The second member is
A semiconductor package characterized by being perpendicular to the surface of the first member facing the substrate. 半導体、前記半導体を封止する封止部、及び前記半導体に電気的に接続される端子を有する半導体パッケージと、
前記端子に対向するランドを有する基板と、を備えた半導体アセンブリであって、
前記端子は、
基板に対向する前記封止部の面と同一面上に配置される第１部材と、
前記基板に対向する前記第１部材の面から前記基板に向かって伸び、弾性を有する第２部材と、を有し、
前記第２部材と前記ランドは導電性接合部材で接続される
ことを特徴とする半導体アセンブリ。 A semiconductor package having a semiconductor, a sealing portion for sealing the semiconductor, and a terminal electrically connected to the semiconductor;
A semiconductor assembly comprising: a substrate having lands facing the terminals;
The terminal is
A first member disposed on the same surface as the surface of the sealing portion facing the substrate;
A second member that extends from the surface of the first member facing the substrate toward the substrate and has elasticity,
The semiconductor assembly, wherein the second member and the land are connected by a conductive bonding member. 請求項６に記載の半導体アセンブリであって、
前記導電性接合部材は、
前記第２部材に対向する前記ランドから前記第１部材まで形成される
ことを特徴とする半導体アセンブリ。 The semiconductor assembly according to claim 6, comprising:
The conductive bonding member is
The semiconductor assembly is formed from the land facing the second member to the first member. 請求項６に記載の半導体アセンブリであって、
前記導電性接合部材は、
前記第２部材に対向する前記ランドから前記第２部材の先端まで形成される
ことを特徴とする半導体アセンブリ。 The semiconductor assembly according to claim 6, comprising:
The conductive bonding member is
The semiconductor assembly is formed from the land facing the second member to the tip of the second member.
JP2015248392A 2015-12-21 2015-12-21 Semiconductor package and semiconductor assembly Expired - Fee Related JP6621321B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015248392A JP6621321B2 (en) 2015-12-21 2015-12-21 Semiconductor package and semiconductor assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015248392A JP6621321B2 (en) 2015-12-21 2015-12-21 Semiconductor package and semiconductor assembly

Publications (2)

Publication Number Publication Date
JP2017117825A true JP2017117825A (en) 2017-06-29
JP6621321B2 JP6621321B2 (en) 2019-12-18

Family

ID=59231965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015248392A Expired - Fee Related JP6621321B2 (en) 2015-12-21 2015-12-21 Semiconductor package and semiconductor assembly

Country Status (1)

Country Link
JP (1) JP6621321B2 (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02168640A (en) * 1987-11-04 1990-06-28 Nec Corp Connection structure between different substrates
JPH05243463A (en) * 1992-03-02 1993-09-21 Sharp Corp Plastic molded type semiconductor device
JPH07211847A (en) * 1994-01-21 1995-08-11 Mitsubishi Electric Corp Semiconductor device, its manufacture, its mounting structure and mounting method
JPH0864745A (en) * 1994-08-19 1996-03-08 Sony Corp Semiconductor device
JPH08181266A (en) * 1994-12-21 1996-07-12 Hitachi Ltd Lead frame, and semiconductor device constituted, using it
JPH1070227A (en) * 1996-06-18 1998-03-10 Lg Semicon Co Ltd Bottom lead type semiconductor package
JP2000077598A (en) * 1998-09-02 2000-03-14 Nec Corp Semiconductor device
JP2004228166A (en) * 2003-01-20 2004-08-12 Sanyo Electric Co Ltd Semiconductor device and its producing process
JP2006210956A (en) * 1997-02-27 2006-08-10 Fujitsu Ltd Semiconductor device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02168640A (en) * 1987-11-04 1990-06-28 Nec Corp Connection structure between different substrates
JPH05243463A (en) * 1992-03-02 1993-09-21 Sharp Corp Plastic molded type semiconductor device
JPH07211847A (en) * 1994-01-21 1995-08-11 Mitsubishi Electric Corp Semiconductor device, its manufacture, its mounting structure and mounting method
JPH0864745A (en) * 1994-08-19 1996-03-08 Sony Corp Semiconductor device
JPH08181266A (en) * 1994-12-21 1996-07-12 Hitachi Ltd Lead frame, and semiconductor device constituted, using it
JPH1070227A (en) * 1996-06-18 1998-03-10 Lg Semicon Co Ltd Bottom lead type semiconductor package
JP2006210956A (en) * 1997-02-27 2006-08-10 Fujitsu Ltd Semiconductor device
JP2000077598A (en) * 1998-09-02 2000-03-14 Nec Corp Semiconductor device
JP2004228166A (en) * 2003-01-20 2004-08-12 Sanyo Electric Co Ltd Semiconductor device and its producing process

Also Published As

Publication number Publication date
JP6621321B2 (en) 2019-12-18

Similar Documents

Publication Publication Date Title
US20140167237A1 (en) Power module package
JP6012533B2 (en) Power semiconductor device
JP6493317B2 (en) Semiconductor device
JPH1012790A (en) Semiconductor integrated circuit device
JP2015056638A (en) Semiconductor device and method of manufacturing the same
JP6092645B2 (en) Semiconductor device
JP2016219778A (en) Power semiconductor device
JP6607077B2 (en) Semiconductor device
JPWO2013047231A1 (en) Semiconductor device and manufacturing method thereof
JP6621321B2 (en) Semiconductor package and semiconductor assembly
JP2014103183A (en) Electronic circuit, manufacturing method of the same, and electronic component
CN108257940B (en) Semiconductor device and method for manufacturing the same
JP2015002245A (en) Electronic apparatus with mold package
JPWO2018150556A1 (en) Electronic device and connector
TWI745525B (en) Conductive clip connection arrangements for semiconductor packages
WO2015052880A1 (en) Semiconductor device and method for producing same
KR20100035957A (en) Light emitting device
JP2016062904A (en) Semiconductor device
JP2016029688A (en) Semiconductor device for power
JP2013168669A (en) Quad flat no-lead (qfn) integrated circuit (ic) package with enhanced paddle and method of designing the same
JP2019117893A (en) Semiconductor package
JP7425587B2 (en) electronic control unit
WO2023176332A1 (en) Electronic device
KR101214964B1 (en) Lead Frame and Semiconductor Device Package Using the Same
US20230380068A1 (en) Electronic Control Device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180905

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20181016

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181115

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190507

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190618

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20191112

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20191119

R150 Certificate of patent or registration of utility model

Ref document number: 6621321

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees