JPH0855884A - Semiconductor device and its measurement method - Google Patents

Abstract

PURPOSE:To test the electrical characteristics of a semiconductor device in a wafer state efficiently and certainly. CONSTITUTION:Wirings L1 and L2 for testing are formed on a plurality of semiconductor devices X formed in one piece on a same semiconductor wafer 5 so that the wirings are connected to each target PD to be measured and at the same time are connected to bonding pads EX1 and EX2 for contacting a probe formed at an empty region of the semiconductor wafer 5 via a lead-out wiring formed on a scribe line existing between the semiconductor devices X. Then, a probe is brought into contact with the bonding pads EX1 and EX2 to supply power and signals when testing the electrical characteristics of the target PD to be measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a structure in which an electrical characteristic test (for example, probe inspection) of each circuit formed on a wafer can be performed in the wafer state before dicing processing. The present invention relates to a semiconductor device and a measuring method thereof.

[0002]

2. Description of the Related Art In the process of mass-producing individual semiconductor devices and integrated circuits (hereinafter collectively referred to as "semiconductor devices"), quality is checked in each process according to a predetermined efficient and leak-free inspection program. Assurance inspections are conducted, and establishment of such a quality assurance system is extremely important.

In the probe inspection of the quality assurance inspections, a dicing process is performed after a plurality of semiconductor devices are collectively manufactured on a semiconductor wafer by a stepper technique or the like, and then separated into individual chip-shaped semiconductor devices. Before performing the test, an electrical characteristic test is performed on each semiconductor device in the state of the semiconductor wafer, the problem in batch manufacturing is analyzed from the test result, and the semiconductor device does not have a predetermined quality. Is found, and is subjected to a screening process for removing the abnormal chip after the dicing process.

[0004]

However, as described above, to test each semiconductor device manufactured in a batch in the state of a semiconductor wafer is to probe (test) a desired test portion of a semiconductor device that is microfabricated. Since it requires extremely delicate and delicate operations such as contacting the probe, the difficulty is high, and it is more difficult to test the finished product after it is housed in an IC package or the like.

In particular, when each semiconductor device has a configuration including a plurality of circuit blocks having different functions and different characteristics, each block is tested according to different test items. Since it must be performed, extremely delicate operation is required, and there is also a problem that a sufficient test cannot be executed because such delicate operation is difficult.

Further, in a semiconductor device having an analog system and a digital system, which has an optical device and its associated amplification circuit block and digital circuit block, the above-mentioned optical device and amplification circuit block are analog. Electrical characteristic test, digital circuit block, such as function test for digital electrical characteristic test, so that different types of electrical tests can be carried out without adversely affecting each other Must be done and is extremely difficult.

Further, not only when the analog system and the digital system are built in, but, for example, when the characteristics of the optical device described above are an important factor that determines the quality of the semiconductor device, It is necessary to test only the optical device separately from other analog systems, and even in such a case, there arises a problem that the precise operation of the probe becomes difficult.

Further, since it is difficult to bring the probe into direct contact with the element to be measured in the semiconductor device as described above, the test bonding pad electrically connected to the element or the like is connected to the semiconductor device. A method has been devised in which the probe is brought into contact with the test bonding pad during the probe test by integrally forming it in the internal circuit, but such a test bonding pad is used only for the probe test. However, unlike the power supply bonding pad and the signal input / output bonding pad for operating the semiconductor device originally, it is useless when it is housed in the IC package after the dicing process to be a finished product. Therefore, the integral formation of such a test bonding pad in the internal circuit causes it to remain as it is even though it is finally unnecessary, which leads to an increase in the size of the semiconductor chip.
There is also a problem that the cost of the semiconductor device is increased.

The present invention provides a semiconductor device having a structure that enables an electrical characteristic test such as a probe test in a wafer state to be performed efficiently and in a leak-free state, and the semiconductor device is also provided. It is intended to provide a measuring method of.

[0010]

In order to achieve such an object, the present invention provides a plurality of semiconductor devices integrally formed on the same semiconductor wafer to be subjected to a test such as a probe inspection, and a measuring method thereof. In the case of integrally forming each of the semiconductor devices on the same semiconductor wafer, the test wiring connected to an object to be measured in each semiconductor device and the test wiring on a scribe line existing between the semiconductor devices. To form a lead wire connected to the lead wire and a bonding pad for contacting the probe connected to the lead wire in an empty area of the semiconductor wafer, and contact the probe with the bonding pad to measure the electrical characteristics of the object to be measured. I chose

[0011]

With the test wiring and the lead wire, common wiring is formed for the object to be measured (single semiconductor device, integrated circuit, etc.) provided in the plurality of semiconductor devices manufactured on the semiconductor wafer. Since the wiring is connected to the bonding pad formed in the empty area of the semiconductor wafer, a probe (probe) is brought into contact with the bonding pad to apply a predetermined power supply voltage or a predetermined test signal. It is possible to measure electrical characteristics such as voltage and current when applied.

Further, since the dedicated wiring and the above-mentioned bonding pad are provided for each object to be measured, different electrical characteristic tests can be conducted for each object to be measured.

Further, since the bonding pad is formed in a vacant region of the semiconductor wafer outside each semiconductor device, it is easy to contact the probe, the probe test can be easily conducted, and the bonding pad is efficient and leak-free. The test can be conducted.

When the above wiring is formed on the scribe line existing between the semiconductor devices, the wiring is cut at the same time only by performing a dicing process for separating each semiconductor device into each chip. It is possible to automatically remove the influence of the above wiring on the measurement target. Therefore, the next process such as the assembling process can be performed without considering the presence or absence of the wiring, and a problem such as an extra process is not caused.

Further, since the test bonding pad as in the prior art is not formed in the internal circuit of each semiconductor device, the semiconductor chip can be downsized.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention will be described below with reference to the drawings. First, based on FIG. 1, a circuit example of one semiconductor device of a plurality of semiconductor devices collectively manufactured on a semiconductor wafer will be representatively described. Such a semiconductor device is an optoelectronic semiconductor device (OE) used in an optical receiver or the like for converting an optical signal into an electric signal in the field of optical communication.
IC) is manufactured by a chemical semiconductor manufacturing process. Bonding pad 1 for applying first power supply voltage V _PD , bonding pad 2 for applying second power supply voltage V _DD , and these power supply voltage V
Power supply voltage lower than _PD and V _DD (eg ground voltage)
A bonding pad 3 for applying V _EE and a bonding pad 4 for outputting the output signal Vo are formed. As is well known, these bonding pads 1 to 4 are formed around the internal circuit of a semiconductor device on a semiconductor wafer, and when they are housed in an IC package and assembled, they serve as predetermined lead terminals of the IC package. Wire-bonded between.

In the internal circuit, a PIN photodiode P that generates a photocurrent corresponding to the intensity of the light when the light is received.
D and an amplifier circuit for converting the photocurrent of the PIN photodiode PD into a voltage, amplifying it with a predetermined voltage amplification factor, and outputting the voltage-amplified output signal Vo to the bonding pad 4.

The cathode of the PIN photodiode PD is connected to the first bonding pad 1, and its anode is connected to the gate of the transistor Q2 which is one component of the amplifier circuit. The source of the transistor Q2 has three diodes D1 to D3 connected in series with each other.
Is connected to a third bonding pad 3 via a drain, and its drain is connected to a second bonding pad 2 via an active load composed of a transistor Q1 and a resistor R1 and also connected to a gate of the transistor Q3. There is. The drain of the transistor Q3 is connected to the second bonding pad 2. The source of the transistor Q3 has three diodes D4 to D6 connected in series with each other.
Is connected to the third bonding pad 3 via the active load transistor Q4, and is also connected to the gate of the transistor Q5. The drain of the transistor Q5 is connected to the second bonding pad 2, and its source is three diodes D7 to D connected in series with each other.
It is connected to the third bonding pad 3 via the active load transistor 9 and the transistor 9 for active load, and is also connected to the bonding pad 4 for signal output. Further, a negative feedback resistor Rf is connected between the drain of the active load transistor Q4 and the gate of the transistor Q1.

When a semiconductor device having such an internal circuit is separated into individual chips by a dicing process and housed in an IC chip to be a finished product, a predetermined lead terminal is provided to each of the bonding pads 1 to 3 through a predetermined lead terminal. When the power supply voltage is applied, predetermined photoelectric conversion and amplification processing is performed, and the output signal Vo is output to a predetermined lead terminal of the IC package via the bonding pad 4.

That is, the PIN photodiode PD supplies a photocurrent to the gate of the transistor Q2 in response to the incidence of an optical signal, and the transistor Q2 converts this photocurrent into a voltage, and at the same time, a predetermined voltage amplification factor (transistor Q2 Of the transistor Q3 and Q5 which form a two-stage source follower circuit by generating a voltage signal V _Q2 amplified by a voltage amplification factor gm · R _L ), which is determined by the transconductance gm of Q1 and the active load R _{L of} Q1 and R1. The voltage signal V _Q2 is power-amplified and output to the bonding pad 4 as the output signal Vo. The feedback resistor Rf is provided for defining the frequency band and the amplification factor of the entire amplification circuit.

Further, the cathode of the PIN photodiode PD has a test wiring L1 used for probe inspection.
Is extended to the scribe line side, and the test wiring L2 similarly used in the probe inspection is extended to the scribe line side at the anode of the PIN photodiode PD. The test wirings L1 and L2 are formed simultaneously with the aluminum wiring in the internal circuit in the manufacturing process. Therefore, it is designed in advance as a mask pattern for manufacturing such a semiconductor device.

Since a plurality of semiconductor devices having such a circuit structure are collectively manufactured on a semiconductor wafer by the stepper technique or the like, the semiconductor device X having the same structure on the semiconductor wafer 5 as indicated by the symbol X in FIG. Are regularly arranged in a matrix.

Further, in the scribe line formed between the semiconductor devices X, a lead-out wiring M1 commonly connecting the test wiring L1 extending from each semiconductor device X and a test wiring extending from each semiconductor device X. Lead-out wiring M2 commonly connecting L2 is formed, the end portion of the lead-out wiring M1 is connected to the test bonding pad EX1 formed in the empty area of the semiconductor wafer 5, and the end portion of the lead-out wiring M2 is the same. It is connected to another test bonding pad EX2 formed in the empty area.

The lead-out wirings M1 and M2 are formed simultaneously with the test wirings L1 and L2 in the manufacturing process step, and are designed in advance by a predetermined mask pattern like the test wirings L1 and L2. Therefore, by performing the normal manufacturing process, the lead wirings M1 and M2 are simultaneously formed. Further, the test bonding pads EX1 and EX2 are bonding pads 1 to 1
4 is formed at the same time in the process of forming 4. That is, the test bonding pad EX is included in the mask pattern for forming the bonding pads 1 to 4.
The patterns for forming 1 and EX2 are also integrally designed in advance.

More specifically, referring to FIG. 3 which is an enlarged view of a part of the semiconductor wafer 5 shown in FIG. 2, when each semiconductor device X is formed on the same semiconductor wafer 5, it is accompanied by it. , The test wiring L1 extending from the cathode of each PIN photodiode PD included in each semiconductor device X,
The lead wiring M1 formed on the scribe line is commonly connected to the test bonding pad EX1. At the same time, the test wiring L2 extending from the anode of each PIN photodiode PD is commonly connected to the lead wiring M2 formed on the scribe line and connected to the test bonding pad EX2.

Next, a probe inspection method for a semiconductor device having such a structure will be described. PIN photodiode P
When the electrical characteristics of D are measured independently of the amplifier circuit, probes are brought into contact with the bonding pads for testing EX1 and EX2, and a predetermined power supply voltage according to the test item is applied via these probes. For example, the ground voltage is applied to the test bonding pad EX2, and the rated power supply voltage and various power supply voltages around it are applied to the test bonding pad EX1. Then, the voltage fluctuation occurring between the probes is measured for a long time in a predetermined temperature environment, and the fluctuation of the current flowing through each PIN photodiode PD via the probe is measured.

Since no power supply voltage is applied to the amplifier circuit during this test, it is possible to measure only the electrical characteristics of the PIN photodiode PD without being affected by the amplifier circuit. Particularly in the semiconductor device of this embodiment, since the quality of the characteristics of the PIN photodiode PD is the most important factor that influences the quality of the device, it is extremely important to measure the PIN photodiode PD independently. Bring effect.

When a predetermined test is completed, a dicing process is performed along the scribe line,
Each semiconductor device X is separated into chips. At this time, FIG.
As shown in FIG. 5, since the lead wirings M1 and M2 are formed on the scribe line, the lead wirings M1 and M2 are cut at the same time as the dicing process, and the test wirings L1 and L2 are divided for each semiconductor device X. You lose your electrical meaning. Therefore, it is not necessary to newly add a special process for removing these wirings L1, L2, M1, M2 after the end of the test.

As described above, according to this embodiment, the semiconductor devices X having the PIN photodiode PD to be measured are collectively formed on the same semiconductor wafer 5, and at the same time, the predetermined PIN photodiode PD is formed. Wirings L1, L2, M1, M for applying the test power supply voltage
2 is formed along the scribe line and the bonding pads EX1 and EX2 for contacting the probe are formed in the empty area of the semiconductor wafer 5, so that the probe for testing the PIN photodiode PD for each semiconductor device X is formed. Since it is not necessary to bring them into contact with each other, simple and reliable measurement can be realized.

Further, since the test bonding pad is not provided side by side like a normal bonding pad, a semiconductor device having high integration efficiency can be realized.

In this embodiment, the case of the optoelectronic semiconductor device is described, but this is an example of the present invention, and a case where a specific circuit of the internal circuit including various kinds of circuits is measured separately from other circuits. It can be widely applied to, and the same effect as this embodiment can be obtained.

In this embodiment, the case where the electrical characteristic of the PIN photodiode PD is measured has been described, but the present invention is not limited to this, and a plurality of objects to be measured may be included in each semiconductor device. When present, it also includes the case where the similar test wirings L1 and L2, the lead-out wirings M1 and M2, and the bonding pads EX1 and EX2 are provided in parallel.

[0033]

According to the present invention as described above,
The test wiring and the lead wire form a common wiring for the device under test (single semiconductor device, integrated circuit, etc.) that is provided in a plurality of semiconductor devices manufactured on a semiconductor wafer, and the wiring is a semiconductor. Since it is connected to the bonding pad formed in the vacant area of the wafer, when a probe (probe) is brought into contact with the bonding pad to apply a prescribed power supply voltage or a prescribed test signal. It is possible to measure electric characteristics such as voltage and current.

Further, since the dedicated wiring and the above-mentioned bonding pad are provided for each object to be measured, different electrical characteristic tests can be conducted for each object to be measured.

Further, since the bonding pad is formed in a vacant region of the semiconductor wafer outside each semiconductor device, the probe can be easily brought into contact therewith, the probe test can be easily performed, and the bonding pad is efficient and leak-free. The test can be conducted.

When the above wiring is formed on the scribe lines existing between the semiconductor devices, the wiring is cut at the same time only by performing a dicing process for separating each semiconductor device into each chip. It is possible to automatically remove the influence of the above wiring on the measurement target. Therefore, the next process such as the assembling process can be performed without considering the presence or absence of the wiring, and a problem such as an extra process is not caused.

Further, since the test bonding pad as in the conventional case is not formed in the internal circuit of each semiconductor device, the semiconductor chip can be downsized.

As described above, according to the present invention, many effects are exhibited, and it is possible to greatly contribute to the establishment of an efficient and leak-free quality assurance system in the process of mass-producing semiconductor devices.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor device of an embodiment.

FIG. 2 is an explanatory diagram showing the arrangement of semiconductor devices formed on the same semiconductor wafer.

FIG. 3 is an explanatory view of a main part showing a partial structure of the semiconductor wafer of FIG.

[Explanation of symbols]

PD ... PIN photodiodes, 1, 2, 3, ... Bonding pads for applying power supply voltage, 4 ... Bonding pads for signal output, EX1, EX2 ... Bonding pads for testing, L1, L2 ... Wiring for testing, M1, M2 ... Lead wiring.

Claims (3)

[Claims] 1. A plurality of semiconductor devices integrally formed on the same semiconductor wafer, which are formed on scribe lines existing between the semiconductor devices while being connected to an object to be measured in the respective semiconductor devices. A semiconductor device having a test wiring connected to a bonding pad for probe contact formed in an empty region of a semiconductor wafer through a lead wiring. 2. A plurality of semiconductor devices integrally formed on the same semiconductor wafer, connected to photoelectric conversion elements formed in each of the semiconductor devices, and on scribe lines existing between the semiconductor devices. A semiconductor device having a test wiring connected to a bonding pad for probe contact formed in a vacant region of a semiconductor wafer through a lead wiring formed in the semiconductor device. 3. A method of measuring a plurality of semiconductor devices integrally formed on the same semiconductor wafer, wherein when each semiconductor device is integrally formed on the same semiconductor wafer, it is connected to an object to be measured in each semiconductor device. Test wiring, a lead wiring connected to the test wiring on a scribe line existing between the semiconductor devices, and a probe contact bonding pad connected to the lead wiring in an empty area of the semiconductor wafer. Then, a probe is brought into contact with the bonding pad to measure the electrical characteristics of the object to be measured.