JPH085217B2 - Surface coating method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a surface coating method capable of performing surface coating of graphic data at high speed with a line printer or the like.

Conventional technology and problems Non-impact line printers that use laser light are equipped with an image memory and develop print data for one page in the memory, then read the memory and operate the printer to print. There is something. The printing target is not limited to characters, but includes graphic data, that is, figures. Although the sides of a figure, such as a triangle, are generated by a vector generating circuit, an operation called surface painting is performed to color or pattern the inside of the three sides.

Characters are represented by 30 dots x 30 dots, etc., and horizontal 30 dots (dot lines in the horizontal X direction are called dot lines) are printed 30 times in the vertical Y direction to print one character. Is substantially the same as this, and the only pattern is not a character, but dots, diagonal lines, or any other suitable pattern for painting.

When character and / or graphic data is expanded in the image memory, it takes a long time to write 1 bit (corresponding to 1 dot). Therefore, a method of simultaneously writing a plurality of bits, for example, 32 bits is used. The character is 30 x 30 dots,
If 2 bits are added to the space between the left and right characters, it becomes 32 x 30 bits, and simultaneous writing of 32 bits does not hinder. Since the character position specification becomes coarser every 32 dots, for example, 1
It is necessary to devise to be able to specify the position in dot units (this point is explained in the specification filed at the same time). To write surface-painted figure data in this 32-bit boundary image memory, a rectangle / area including the figure and its surroundings is written in 32 bits in the horizontal X direction and in each dot (line) in the vertical Y direction. It is recommended to divide into sections 1 and treat each section in the same way as a 1-character dot line (32 bits x 1 bit). FIG. 2 shows how to divide the figure in the case of a triangle, and L ₁ , L ₂ , ... Show the dot lines. Dot lines L ₁ and L ₂ are lines that surround the figure F and do not include fill data, L ₃ includes lines that do not include fill data at both ends but include fill data in the center, and L ₄ Lines in the figure that include the surface painting data in all, L ₅ and L ₆ are lines that include the surface painting data only in the start end portion or the end portion.

Dot line L ₄ etc., which are all surface filling data, simply need to be written simultaneously at 32 bits, and dot line L ₃ etc. containing only part of the surface painting data write the surface painting data, do not write Since they must be controlled, it is possible to separate them and handle them in another circuit. Examples thereof are shown in FIGS. 3 and 4. FIG. 3 is a circuit for generating surface-painting data for a dot line that partially contains surface-painting data, and FIG. 4 is a circuit for a dot-line that entirely contains surface-painting data. The operation of FIG. ₃ will be described with respect to the line L ₃ of FIG. 2. The circuit (not shown) generates the start point address (x, y) of the fill data portion of this line, and y
The address is in the Y address register YAR and the x address is X
Set in address register XAR. The length l is set in the length counter CNT2. Since the address x is on the 32-bit line L ₃ and this line L ₃ is one of the sections divided by 32 bits on one page, the lower n bits of the address x (here, n = 5) Indicates the x point on L ₃ , and the remaining upper m bits indicate the starting point address of L ₃ . The address y indicates the number of the dot line counted from the upper end on one page, and the detailed description is omitted here. The counter CNT1 is an n-bit counter, and the count value S1 of this counter and the lower-order n bits S2 of the register XAR are input to the comparator CMP, and this comparator is L (low) when S1 <S2.
Level and output S3 of L (high) level when S1 and S2
Cause DR2 is a data register that stores dot dots, diagonal lines, and other appropriate surface painting patterns, and DR1 is a data register that stores write data to an image memory (not shown). Each has a capacity of one dot line, and this is a 32-bit capacity. With capacity.

A paint bit PNTb command is issued at the time of surface painting, and it is set by this and flip-flops FF1 and FF2 output Q output S
Set 4, S5 to H level. The output S4 is input to the counter CNT1 and the enable terminals EBL of the data registers DR1 and DR2 to start them, and the output S5 opens the AND gate G1. The counter CNT1 counts clocks (not shown) and outputs the count value.
0,1,2, ... This is X on line L _{3 in} FIG.
This is equivalent to advancing the address one dot at a time from the start point to the right (the condition is satisfied for m, and the X address is
As entered the L _3). At this stage a S ₃ = L because it is still S1 <S2, the AND gate G1, thus the G2 is closed, the surface coating pattern of the register DR2 of the shift operation is read bit by bit in synchronism with the clock Data is not input to the write data register DR1
0 is written next to.

Eventually, when S1 becomes S2, the output S3 of the comparator CMP becomes H, the gates G1 and G2 are opened, and the surface painting pattern data of the register DR2 is written into the register DR1 bit by bit.
At the same time, the counter CNT2 starts counting down, resets the flip-flop FF2 whose count value becomes 0, and outputs S5
To L. Therefore, the gates G1 and G2 are closed, and 0 is written in the register DR1 again. Thus, only the part l in FIG. 2 has surface painting data, and a line L ₃ of 0 at both ends is stored in the register DR1 and written from the register to the image memory. The same applies to the other lines L ₅ , L _6, etc.

For the line L ₄ containing only the surface painting data, the 32-bit surface painting pattern data of the register DR2 is input to the write data register DR1 as shown in FIG. In this case, a paint word PNTw instruction is issued, which sets the flip-flop FF3 to set its Q output to H and open the AND gate G3. R is a register in which the number of lines such as the line L ₄ continues and therefore the number of times writing is performed in this circuit is set, and its output (number of times) S8 is the writing control section of the image memory. It is sent to the write counter. S7 is an output signal from the write control unit, which appears every time a 32-bit write is performed, and joins the X address register XAR through the AND gate G3 which is now open. Then, the X address is updated in 32-bit units. S6 is a carrier signal of the write counter of the write controller, and what occurs is that the number of writes set in the register R has ended. signal
S6 resets flip-flop FF3, which causes X
The address update is stopped and the writing in this circuit is stopped.

In the method of FIGS. 3 and 4, it is necessary to divide each dot line into all surface painting data or part of the surface painting data, which increases the amount of programming. Also, the counter is used to count the surface painting start point, which slows down the processing speed. Moreover, each uses different hardware, which is not a good idea.

An object of the present invention is to improve such points and to provide a surface coating method capable of performing high speed surface coating with a simple process.

According to the present invention, an image memory having a plurality of storage areas divided in units of a plurality of pixels, and all possible surface coating mask patterns for graphic data in the storage area are stored. Is provided with a mask pattern memory that is accessed by the relative fill start address and fill width information in the storage area, and when the fill data is stored in the image memory,
For each storage area of the image memory, the mask pattern memory is accessed by the relative surface coating start address and surface coating width information in the storage area, and the image is read using the read surface coating mask pattern. The surface of the corresponding storage area of the memory is painted, which will be described below with reference to an embodiment.

Embodiment of the Invention FIG. 1 shows an embodiment of the present invention. IMM is the above-mentioned image memory, and DR is the same write data register as DR1 in FIG. G is a gate circuit corresponding to the same G2, and its input signal Sc is surface painting pattern data for painting such as dots and diagonal lines output from the same DR2. MR is a read-only memory, which is a mask ROM in this example, and stores mask patterns for the dot lines L ₃ , L _4, etc. in FIG.
For example, the part l of the line L ₃ is 1,1, ... 1, and both ends are 0,
32-bit data of 0, ... 0 is provided for the dot line L ₃ , and the same applies to other dot lines. There are four types of fill data: the central part like line L ₃ , the right end like line L ₅ , the left end like line L ₆ , or the whole line L _4. (line
Items such as L ₁ and L ₂ that do not have surface painting data are not applicable, and of course you may have one all 0)
All of these combinations for 32 bits are Maschrome MR
It is only necessary to write the data in, and the write data can be easily output to the computer. For example, the write data is as follows.

The access address for the mask ROM MR is the fill width data Sa and the lower n bits Sb of the X address. The lower n bits indicate x in FIG. 2, and the surface painting width data is the same as l.
As a result, the dot pattern of the line L ₃ is determined, and the 32-bit pattern data Sd of the line L ₃ of 00 …… 011 …… 100 …… 0 can be output in parallel from the mask ROM MR. The same applies to the other lines. That is, by configuring the access address of the mask ROM MR with a combination of Sa and Sb, any 32-bit pattern data in which the number of consecutive 1s is represented by Sa and the leading 1 position is represented by Sb Sd can be selectively read from the Maschrome MR. This access address is generated by a processing program for performing surface painting.
The reading of the mask ROM MR is performed every time the upper m bits of the X address are updated in the figure area.

A pair of image memories IMM are provided. When one is read out and the other is being driven while the printer is being driven, the other is written and the characters and / or graphics in one page are developed. When 32-bit simultaneous writing is completed from the upper left corner to the lower right corner of the image memory IMM, the writing is completed. Although the gate G is shown as one in the figure, 32 pieces of the gate G and the like are provided because it is a 32-bit parallel processing.

Effects of the Invention As described above, according to the present invention, surface coating can be performed at high speed with relatively simple processing, which is extremely effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of a processing procedure, and FIGS. 3 and 4 are block diagrams showing other examples of surface coating processing. In the drawings, IMM the image memory, F is graphic, L _3, L ₄ ...... is partitioned, MR read-only memory, x is X address surface coating begins, l the surface coating width, G is the gate circuit.

Claims (1)

[Claims] 1. An image memory having a plurality of storage areas divided in units of a plurality of pixels, and all possible surface coating mask patterns for graphic data in the storage area are stored. A mask pattern memory that is accessed by the relative fill start address and fill width information in the storage area, and when storing fill data in the image memory, the storage area of the image memory Each time, the mask pattern memory is accessed by the relative surface painting start address and information of the surface painting width in the storage area, and the corresponding storage area of the image memory is used by using the read surface painting mask pattern. A surface coating method, which comprises performing a surface coating process on the surface.