JPH0764850A - Painting-out plotter - Google Patents

Abstract

PURPOSE:To paint out a large area on a picture memory with one picture element value or a periodic pattern at a higher speed in the case that write data is not changed. CONSTITUTION:In a painting-out plotting part 12 which paints out an area on the picture memory, where picture data outputted to the output device of a computer system is stored as the information of picture elements, with a picture element value, it is discriminated whether write data is changed in the continuous write to the picture memory or not, by a transverse scan sequencer 1201 in a painting-out plotting sequencer 120. When it is discriminated that write data is not changed, write is so controlled that write to the picture memory is continuously performed at a speed higher than the limit determined by the switching time of write data, thus increasing the painting-out plotting speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to writing drawing data to an image memory storing data of each pixel of a display screen of a computer system or an image memory storing image data to be printed on a printer. In relation to the controlling device, a large area on the image memory is set to one pixel value,
Alternatively, it relates to a means for speeding up the process of filling with the periodic pattern.

[0002]

2. Description of the Related Art Conventionally, an image memory storing image information to be output to a printer or screen information of a computer is filled in a horizontal straight line region having a width of one pixel or a rectangular region. The horizontal filling, the primary scanning in the horizontal direction, and the secondary scanning in the vertical direction are performed respectively, and the filling processing by the horizontal scanning is performed in the dynamic memory forming the image memory or the image. The speed was increased by using the page write function of the dual port memory.
As this type of filling method, there is a "high-speed horizontal line drawing control method" described in Japanese Patent Laid-Open No. 4-137186.

Here, the dynamic access memory (DR
The basic operation of AM) is explained.

In DRAM, / RAS (Row Address Strobe) and / C
Control is performed based on two control signals called AS (Column Address Strobe). Here '/' means instead of overbar.

In addition, / OE (Output Enable) and / WE (Writ
e Enable) signal is used to control the distinction between read and write.

A normal read or write access to the DRAM is performed by sequentially lowering / RAS and / CAS as shown in FIG. The read or write address is designated as RA (Row Address) and CA (Column Address) on the address signal line when / RAS and / CAS fall.
This is done by specifying one address.

The distinction between read and write is made by / OE and / WE.

The DRAM read and write modes are:
It can be classified into two modes, a mode called Early Write and a mode that is not Early Write. These two modes are distinguished by the value of / WE at the time of the fall of / CAS.
If the / WE value is Lo at the falling edge of, the Write mode is entered, and if the / WE value is Hi at the / CAS falling edge, the Early Write mode is set.
The mode is not Write.

In the Early Write mode (FIG. 15), the data input / output is in the input mode regardless of the value of / OE (the latter will be described later), and the data input at the falling edge of / CAS is DR.
It is written in the position specified by AM RA and CA.

In the mode which is not Early Write (FIG. 17), /
While both OE and / CAS are Lo, the data input / output is in the output mode, and the data at the position specified by DRAM RA and CA is output from the data input / output (FIG. 17 (a)). Also, after / CAS is dropped, / OE is kept high, data input / output is set to the input state, and / WE is dropped while data is being input externally. Value of DRAM is R
It is written in the position designated by A and CA (FIG. 17 (b)). This write method is called Delayed Write.

Read and Del in modes other than Early Write
It is possible to continuously perform ayed write while keeping / CAS at Lo (Fig. 17 (c)). At this time, after reading the location designated by RA and CA of DRAM, the data can be written at the same location. This access method is called read modify write. This is effective in speeding up the process of continuously performing reading and writing at the same position. As an example of this, in a memory system that simultaneously writes to a plurality of bits, when it is desired to rewrite part of the original data, the data is read once, updated partially, and then written back.

In the 1-bit configuration (the configuration in which only 1 bit of data is output from the memory package), there is no / OE and the data input and output are separate signals.

Next, page access will be described.

Between successive accesses having the same Row Address, the access can be executed by repeatedly lowering and raising the / CAS while keeping / RAS at Lo (FIG. 16). / R
Accessing more than once while keeping AS low is called page access. For page access, read,
Although early write, delayed write, and read modify write can be mixed, it is called page write access only for page write access, and page read access for page read access only. .

Further, the setup time and the hold time will be described.

During page write, the address and data values at the falling edge of / CAS are used as the column address and write data in the DRAM, respectively, but at the falling edge of / CAS. When the address or data changes, the DRAM cannot specify the address or data at the falling edge of / CAS,
Operation is not guaranteed. To guarantee the operation of DRAM,
The circuit controlling the DRAM must keep the address and data at a constant value before and after the falling edge of / CAS for the time determined by the specifications of each DRAM product.

The address setup time is the time during which the address must be defined before the falling of / CAS, and the address hold time is the time during which the address must be held after the falling of / CAS. / C
The time that data must be settled before the fall of AS is called the data setup time, and the time that the data must be held after the fall of / CAS is called the data hold time.

Further, the memory with a mask function will be described.

In the image dual port memory, the value of the data input at the fall of / RAS can be used as a mask for each bit in the subsequent write operation.
(Figure 18). This function is called a write per bit function. This function is enabled by setting / WE to Lo at the fall of / RAS. At the fall of / RAS, / WE
When is set to Hi, the mask function does not work and all bits are written as in the conventional DRAM.

[0020]

In the filling processing of a large area, the time for page write access is
Since it occupies most of the entire processing time, shortening the page write cycle time (the time required for one write when writing continuously in page access) is effective for high performance. .

In page write, the minimum value of / CAS page cycle time, which is the repetition period of / CAS, the minimum value of address setup time and hold time, and the minimum value of data, which are defined as the specifications of individual DRAM products. The minimum value of the setup time and the hold time has been an obstacle to shortening the page write cycle time (Fig. 6).

In particular, as shown in FIG. 7, when the filling and drawing means has a configuration in which the control signal and the address of the memory are output from the same LSI and the data is output from another LSI, the control signal and the address The timing skew between them is small, but the timing skew between the control signal and data is large. As shown in FIG. 19, when the data advances to / CAS, the data hold time becomes severe. If the data is delayed with respect to / CAS, the data setup time becomes severe.

Even when all the signals to and from the memory are output from one LSI, as shown in FIG. 20, due to the limitation of simultaneous change noise of the output signal pins of the LSI, the signal line In some cases, only the output driver for the data signal line having a large number of lines is configured with the output driver slower than the output drivers for the other signal lines.
As shown in 1, when the dispersion of the propagation time of the buffer itself is larger in the low speed buffer than in the high speed buffer and the delay becomes small, the data hold time becomes severe and the delay becomes large. Makes the data setup time strict.

The page write cycle time (when not interleaved) according to such a conventional technique is shown in FIG.
Shown in. FIG. 23 shows the page write cycle time in the case of interleaving. The interleave will be described later.

An object of the present invention is to shorten the page write cycle time and speed up the filling process.

[0026]

In order to solve the above problems, according to the present invention, an image memory for storing image data to be output to an output device of a computer system as pixel information is filled with pixel values. In the filling and drawing apparatus for performing the above, the judgment means for judging whether or not the write data is changed in the continuous writing to the image memory, and switching of the write data when the judgment means judges that the write data does not change It is possible to provide a writing control unit that continuously writes to the image memory at a speed higher than the time limit.

Further, in a fill drawing apparatus that interleaves a plurality of image memories that store image data to be output to an output device of a computer system as pixel information, in an interleaved image memory Write data, and a determination unit that determines whether the write data in continuous writing to the image memory changes, and a write control to each image memory when the determination unit determines that the write data does not change It is also possible to provide a write control unit that outputs signals simultaneously and continuously writes data to the image memory at a higher speed than the limit due to the data switching time.

[0028]

In the image memory system which does not use interleaving, it is determined whether or not the condition of being filled with one pixel value is satisfied. If this condition is met, the page cycle time is reduced by eliminating the limitation on the setup time and hold time of data by utilizing the property that the data does not change between successive writes in page access. Reduce page cycle time by changing to less than the setup and hold time limits.

In the image memory system using the interleave, it is judged whether or not the condition of being filled with one pixel value is satisfied. If this condition is satisfied, the property that the write data is the same in each bank is used to lower the / CAS of all banks at the same time, and the data does not change between successive writes in page access. By taking advantage of this property, the page setup time and the hold time are eliminated, so that the page cycle time is changed to be equal to or shorter than the data setup time and the hold time limit, and the page cycle time is shortened.

No interleaving is used, and
In an image memory system configured to write a plurality of pixels in one writing to the image memory, a condition that an integer multiple of the horizontal period of the filling pattern is equal to the number of horizontal pixels in the writing area in one writing. It is determined whether or not holds. When this condition is satisfied, the page cycle time can be reduced by eliminating the limitation of the data setup time and the hold time by utilizing the property that the data does not change between successive writes in page access. Reduce page cycle time by changing to less than the setup and hold time limits.

In an image memory system using interleaving and writing to a plurality of pixels by writing once to each bank, an integer multiple of the horizontal period of the filling pattern is set to each bank. It is determined whether or not the condition that the number of pixels in the horizontal direction of the writing area is equal to that of one writing is satisfied. If this condition is satisfied, the property that the write data is the same in each bank is used to lower the / CAS of all banks at the same time, and the data does not change between successive writes in page access. By taking advantage of this property, the page setup time and the hold time are eliminated, so that the page cycle time is changed to be equal to or shorter than the data setup time and the hold time limit, and the page cycle time is shortened.

[0032]

FIG. 1 shows a computer system for carrying out the present invention. Reference numeral 10 is a central processing unit (CPU) that controls the entire system, 11 is a main storage device that stores instructions and data for the CPU to operate, 12 is a solid drawing unit that performs solid drawing according to the present invention, and 13 is an image memory. , 14 is a color lookup table for converting the data stored in the image memory into display colors, and 15 is a display device.
The fill drawing unit 12 is set by the CPU 10 so that
A one-pixel width horizontal straight line area or a rectangular area in the image area stored in the image memory is filled with one value or a periodic pattern having a period in the horizontal and vertical directions. In FIG. 1, the filling drawing unit 12 is drawn as one large-scale integrated circuit (LSI), but controls the shape of the drawing in the image memory in the filling drawing unit and activates the image memory control means. All or part of the fill drawing sequencer, the image memory control sequencer for controlling the image memory, and the data creation unit for creating data may be different LSIs.

Next, the shape of what is drawn by the filling drawing unit 12 (see FIG. 1) will be described with reference to FIG.
The filling / drawing unit 12 fills a linear area 20 having a width of one pixel in the horizontal direction and a rectangular area 21. The designation of these shapes is performed, for example, by the CPU setting a value for designating an area in a predetermined register of the filling and drawing unit 12. The combination of registers for designating these areas is, for example, in the case of a linear area of 1 pixel width in the horizontal direction, the coordinates and width of the left end (FIG. 2A), or the horizontal and vertical coordinates of the left end. The horizontal component of the directional component and the rightmost coordinate (FIG. 2B). In the case of a rectangular area, the upper left coordinate and size (FIG. 2C), or the upper left coordinate and lower right coordinate. (Fig. 2 (d)).

Next, the structure of the filling drawing unit 12 (see FIG. 1) will be described with reference to FIG. The fill drawing unit 12 controls writing and controls the image memory control sequencer 12
1 includes a solid drawing sequencer 120 for starting up, an image memory control sequencer 121 for controlling the image memory, and a data creating unit 122 for creating drawing data. Further, the fill-drawing sequencer 120 is a vertical scan sequencer 12 that performs a vertical scan of a rectangular area to be filled.
00 and a horizontal scan sequencer 1201 for performing horizontal scanning.

Next, the operations of the vertical scan sequencer 1200 and the horizontal scan sequencer 1201 will be described with reference to FIG. The vertical scan sequencer 1200 is, for example,
When the drawing is activated by register setting from the CPU 10 (see FIG. 1), the horizontal scan sequencer 1201 is activated while scanning the filling position in the vertical direction.

When the horizontal scan sequencer 1201 is activated by the vertical scan sequencer 1200, the horizontal scan sequencer 1201 paints while scanning in the horizontal direction. Further, in one writing to the image memory 13, the writing boundary is a horizontal line area fixed to the image memory, or the writing boundary is a rectangular area fixed to the image memory. The image memory control sequencer 121 is activated in turn from the top side, the bottom side,
For writing on the left side and the right side, in general, the boundary between the writing unit and the drawing object is not aligned, so a boundary mask is generated.

The shape of the boundary mask will be described with reference to FIG. FIG. 4 shows a scan order when filling the rectangle 21 and a mask (shown by shading) in each writing. The uppermost horizontal scan 30 is composed of a mask on the left side, a mask on the right side, and a mask on the upper side.
Includes a mask on the left side and the mask on the right side and a mask on the lower side, and the other horizontal scans 31 include masks on the left side and the right side. For example, 300 is an area corresponding to the leftmost writing of the uppermost horizontal scan, and is composed of masks on the upper side and the left side.

There are three methods for realizing the pixel masks on the left and right sides at the time of horizontal scanning which is neither the top nor the bottom, for example, as shown in FIG. Hereinafter, these three types will be described with reference to FIG. 5 and FIG. 13, which is a time chart corresponding to (a), (b), and (c) of FIG. 5, respectively.

In the first method shown in FIG. 5A, memory is allocated so that each pixel written at one time corresponds to a different dynamic memory chip, and a chip control signal, for example, / CAS is assigned to each memory. This is a method of controlling writing / not writing in the pixel direction by providing each pixel and controlling each pixel. With this method, the page access function can be used over the drawing of one line. Time chart (Fig. 1
The correspondence with 3) is shown below. At the left end (410 in FIG. 5), a plurality of / CAS signals (in FIG. 13, as a representative two
A part of the / CAS signals (/ CASa, / CASb is shown) is dropped to write (410W), and in the middle (411), all / CAS are dropped to write (411W) to the right end. In (412), a part of / CAS is shut down to write (4
12W).

The second method, which is shown in FIG. 5B, is a method of reading the data of the writing destination into the filling drawing unit 12, updating only a part of it, and writing it back. In this method, the read-modify-write cycle or the page access function between the read cycle and the write cycle can be used between the read and the write, and the page access function can be continuously used even between the middle part of the horizontal line. . The correspondence with the time chart (FIG. 13) is shown below.
At the left end (410), after reading (410R), writing (410W) is performed, at the middle (411), only writing (411W) is performed, and at the right end (412), reading (4
After 12 R), writing (412 W) is performed.

The third method shown in FIG. 5C is a method in which an image dual port memory is used as an image memory and a light per bit function which is the function of the image dual port memory is used. . In this method, the page access function cannot be used at the left end and the right end because the mask in the pixel direction changes, but the page access function can be used at the middle part of the horizontal line because the mask in the pixel direction does not change. The correspondence with the time chart (FIG. 13) is shown below. At the left end (410), after setting the mask (410M), writing (410W) is performed, and the middle (4
In 11), after the mask is released (411M: all bit write is permitted), writing (411W) is performed, and at the right end (412), the mask is set (412M) and then writing (412W) is performed.

In the above-mentioned three examples, the horizontal scan sequencer performs the start of the read cycle and the write cycle of the image memory and the instruction as to whether or not to perform the page access, and the image memory control sequencer instructs the horizontal scan sequencer. In accordance with, cause a cycle of image memory.

As the horizontal size of the area to be filled is larger than the horizontal size of the area written in the image memory at one time, the process of repeating the write operation by page access is much of the drawing process. Since it takes time, the performance can be improved by shortening the time (page write cycle time) required for one write when the write is repeated in the page access. The page write cycle time is limited to the page write cycle time of the memory / CAS signal shown in Fig. 6, the setup time and hold time for the column address / CAS fall, and the setup for the write data / CAS fall. Time and hold time. The most severe of these is the page write cycle time of / CAS in the typical dynamic memory specifications.

However, as shown in FIG. 7, a sequencer LSI1 including a solid drawing sequencer (120 in FIG. 3) and a sequencer for controlling image memory (121 in FIG. 3).
23, and a data creation unit (similar to FIG. 3 (122))
In the case where the data creation LSI 124 consisting of only the above is a different LSI, the / CAS signal and the address are output from the same sequencer LSI 123, but the data may be output from another data creation LSI 124.

In this case, the timing skew between the / CAS signal and the address signal is such that the timing for creating these signals is created from the same input clock to the LSI, and when the LSI is created. Since there is no difference in the process of, it can be kept small.

On the other hand, the timing skew between the / CAS signal and the data signal is the wiring from the clock generator to the LSIs 123 and 124 when the clock that is the basis of the timing for creating these signals is reached. Propagation delay difference due to difference in length, LSI 123, 1
The skew becomes large due to the difference in the process at the time of making 24, the difference in the temperature during operation, and the difference in the power supply voltage.

Considering the skew, the address setup time and hold time with respect to / CAS fall can satisfy the memory specifications, but the data setup and hold time with respect to / CAS fall cannot be satisfied. The situation occurs.

Further, control signals such as / CAS, address signals,
Also, even if all the data signals are output from the same LSI, the number of data signal lines is generally larger than the number of control signal lines and address signal lines such as / CAS. A high-speed driver can be used for the driver that drives the control signal line and the address signal line due to the malfunction of the LSI due to the above, and the restriction of electromagnetic radiation radiated to the outside of the device. The driver cannot be used, and the address signal line can satisfy the setup and hold time for / CAS, but the data signal line cannot satisfy the setup time and hold time for / CAS.

The present invention uses the / C
It is applied when the setup time and hold time for AS is the most severe, and the page write cycle time is used for the setup time and hold time for address / CAS,
Or it speeds up to the limit by the page write cycle time of / CAS. FIG. 9 shows a time chart when the page write cycle is accelerated by this method. In FIG. 9, hatched portions indicate periods in which data is not determined due to skew between signals. FIG. 9 (a)
In the case where the data changes between pages, the data setup time and hold time with respect to the falling edge of / CAS are a bottleneck in shortening the page write cycle. FIG. 9B shows a case where the data does not change between pages, until either the address setup time and hold time with respect to / CAS fall or the / CAS page write cycle time becomes a bottleneck. The page write time can be shortened.

Further, in the actual dynamic memory specifications, the constraint on the page write cycle time of / CAS is the strictest, and the page write cycle time is defined by the page write cycle time of / CAS, and the present invention makes sense. Even if it does not exist, if interleaving is used for memory access, the / CAS write cycle time will not become a bottleneck, and the present invention will be meaningful.

Interleaving means, as shown in FIG.
For a plurality of memory banks 130 and 131, addresses,
In addition, the data is commonly connected, only the control signal is connected to each bank, and the timing of the control signal for each bank is shifted to perform control for each bank. For example, at the time of write, by shifting the falling timing of / CAS or / WE in each bank and fixing the write data at the falling edge of each / CAS, the data corresponding to each bank is written, and at the time of reading, , The read data is sequentially output from each bank by sequentially setting / CAS or / OE to a low level in each bank, and the read data is sequentially captured in the LSI for controlling the memory.

According to the present invention, in the memory system performing interleaving, if the data between the banks are the same as in the case of filling with one value, / C of all banks is
AS is turned off at the same time, and the page write cycle time is accelerated up to the page write cycle time of / CAS or the limit value of the address setup time and hold time. FIG. 10 shows a time chart when the page write cycle is accelerated by this method. 10a
In the case where data changes between interleaved banks, the setup time and hold time of data with respect to the falling edge of / CAS becomes a bottleneck in shortening the page write cycle. FIG. 10b shows a case where the data does not change between the interleaved banks, and / C
The page write time can be accelerated until either the address setup time and hold time for the fall of AS or the / CAS page write cycle time becomes a bottleneck.

The present invention also relates to a memory system which does not use interleaving, in which write data does not change between successive writes in page access, and a memory system which uses interleaving.
It can be used when the data to be written to each bank is equal to each other and the write data does not change between successive writes in page access. Therefore, if this condition is satisfied, it is not a single value, but a fill pattern. The present invention can be applied to the case of filling.

When interleaving is not performed, in which case the page write cycle time is shortened, or when interleaving is performed, in which case / CAS is simultaneously lowered. In addition, the horizontal line drawing sequencer (1201 in FIG. 3) in the filling drawing unit 12 (see FIG. 3) determines whether to shorten the page write cycle time. An example of a pattern setting method and an example of determination means corresponding to the pattern setting method are shown in FIGS.
2 shows four.

The four examples shown in FIG. 11 and FIG. 12 correspond to four types of filled drawing parts having different pattern setting methods. In one filled drawing part, the pattern setting method is usually , One of them is decided.

The pattern setting method of the first example (FIG. 11A) is to set the cycle pattern and the cycle of the pattern in the register in the solid drawing unit 12 (see FIG. 3). In this case, in the present invention, the filling drawing unit 12
Is a size 140 in which an integral multiple of the horizontal cycle s1410 of the cycle pattern 1400 is written to the image memory at one time.
1 (300 in FIG. 4, 410 to 4 in FIG. 5)
It is determined whether or not the condition 1212) that the number of pixels in the horizontal direction is a1411 is satisfied. The data written at one time is held in the memory in the data creation unit of FIG.

When it is determined that the above condition is not satisfied, the page write cycle time is as shown in FIG. 9A when interleaving is not performed, and as shown in FIG. 10A when interleaving is performed. To This cycle time is equal to the conventional one.

When it is determined that the above conditions are satisfied, the page write cycle time is as shown in FIG. 9B when not interleaved, and as shown in FIG. 10B when interleaved. To do.

That is, when interleaving is not performed, the page write cycle time is shortened to the / CAS page write cycle or the limit of the setup time and hold time for the address / CAS. In addition, when interleaving is performed, in addition to simultaneously stopping / CAS, / CAS page write cycle,
Alternatively, the page write cycle time is shortened to the limit of the setup time and hold time for the address / CAS.

In FIG. 11A, for example, the horizontal width smax1412 of the maximum size 1402 of the pattern that can be set is 16.
And the horizontal cycle s1410 of the set cycle pattern.
Is 1, 2, 4, 8 or 16 and the number of pixels a1411 in the horizontal direction of the size written by one writing is 8, in the horizontal period s1410 of the set cycle pattern,
Only when 1, 2, 4, or 8, which is the number of horizontal pixels a1411 or less of the size to be written in one writing, is set, the / CAS page write cycle or the setup time for the address / CAS and The page write cycle time is shortened until the hold time is limited (that is, as shown in FIG. 9B). In addition, when interleaving is performed, in addition to falling / CAS at the same time, / CAS page write cycle or address / C
The page write cycle time is shortened to the limit of the setup time and hold time for the AS (that is, as shown in FIG. 10B).

The pattern setting method of the second example (FIG. 11B) is to set all the fixed-size periodic patterns 1400 to the registers in the solid drawing section 12 (see FIG. 3). is there. In this case, the fill drawing unit 12
The set pattern 1400 is divided by the number of pixels a1411 in the horizontal direction of the size 1401 written in the image memory at one time, and the divided sections are compared with each other, and it is determined whether or not the condition that all are equal is satisfied. .

When it is determined that this condition is not satisfied, the page write cycle time is shown in FIG. 9A when interleaving is not performed, and FIG. 10A when interleaving is performed. Like This cycle time is equal to the conventional one.

When it is determined that the above conditions are satisfied, the page write cycle time is set as shown in FIG. 9B when not interleaved, and as shown in FIG. 10B when interleaved.

That is, when interleaving is not performed, the page write cycle time is shortened to the / CAS page write cycle or the limit of the setup time and hold time for the address / CAS.

When interleaving is performed, the / CAS page write cycle or the page write cycle time until the / CAS page write cycle, or the setup time and hold time for the / CAS of the address is limited, in addition to the simultaneous fall of / CAS. To shorten.

In FIG. 11B, the set periodic pattern 14
The horizontal cycle s1410 of 00 is 16, for example, and the number of horizontal pixels a1411 of the size 1401 written in the image memory at one time is smaller than 16, which is the horizontal cycle s1410 of the settable pattern pattern. In the case of 8, the 8 pixels in the horizontal direction of the set periodic pattern 1400 are compared with each other, and only when they are all equal to each other, the / CAS page write cycle, or the setup time and the hold time for the / CAS of the address. Reduce page write cycle time up to the limit of.

When interleaving is performed, the / CAS page write cycle, or the page write cycle time until the / CAS page write cycle, or the setup time and hold time for the / CAS of the address is limited, in addition to the simultaneous fall of / CAS. To shorten.

The third example (FIG. 12A) is shown in FIG.
In (a), in particular, the horizontal pixel number a 1411 of the size 1401 written in the image memory at one time is the maximum horizontal size of the set periodic pattern 1402 sm.
This is the case of an integral multiple of ax 1412.

In the fourth example (FIG. 12B), the period set by the number of horizontal pixels a 1411 of size 1401 written in the image memory at once is set in FIG. 11B. This is the case where the horizontal cycle s 1410 of the pattern 1400 is an integral multiple.

In these cases, the page write cycle time is set as shown in FIG. 9B when not interleaved, and as shown in FIG. 10B when interleaved. This shortens the page write cycle time up to the / CAS page write cycle, or the address setup time and hold time for / CAS if the horizontal line is filled. In addition, when interleaving is performed, in addition to simultaneously stopping / CAS, / CAS
Page write cycle or page write cycle time is shortened up to the limit of setup time and hold time for address / CAS.

[0071]

EFFECTS OF THE INVENTION For an image memory system that does not use interleaving, it is determined whether or not the condition of filling with one pixel value is satisfied, and it is determined that the filling is with one pixel value. In this case, by taking advantage of the fact that the data does not change between page write cycles, by changing the page cycle time below the data setup time and hold time limits, the page write time consumes most of the processing time. It is possible to speed up the filling with one pixel value occupied.

For the image memory system using interleave, it is judged whether or not the condition of being filled with one pixel value is satisfied, and it is judged as being filled with one pixel value. In this case, the write data is the same in each bank, and the data does not change between consecutive writes in page access. By changing the value to be less than or equal to the data setup time and hold time limits, it is possible to speed up the filling with one pixel value that occupies most of the page write time.

No interleave is used, and
For an image memory system configured to write to a plurality of pixels in one writing to the image memory, when filling with a periodic filling pattern, an integral multiple of the horizontal period of the filling pattern is an area to be written in one writing. Determine whether the condition that the number of pixels in the horizontal direction is equal,
When the condition that the integral multiple of the horizontal direction of the fill pattern is equal to the number of horizontal pixels of the writing area in one write is satisfied, the property that the data does not change between page write cycles is used. By changing the time to less than or equal to the data setup time and the hold time limit, it is possible to speed up the filling in the filling pattern in which the page write time occupies most of the processing time.

When the interleaving is used and the image memory system is configured to write a plurality of pixels in one writing to the image memory, at the time of filling with the periodic filling pattern, the horizontal period of the filling pattern is changed. It is determined whether or not the condition that the integral multiple is equal to the number of pixels in the horizontal direction of the writing area in one writing is satisfied, and the integral multiple of the horizontal cycle of the filling pattern is the same as the number of pixels in the writing area in one writing. When the condition that the number of pixels in the horizontal direction is equal is satisfied, the write data is the same in each bank, and the property that the data does not change between successive writes in page access is used to take advantage of all the banks.
/ CAS is turned off at the same time, and the page cycle time is changed to less than the data setup time and hold time limits to speed up the fill in the fill pattern that occupies most of the processing time. You can

[Brief description of drawings]

FIG. 1 is a system configuration diagram to which the present invention is applied.

FIG. 2 is an explanatory diagram of a region designation method at the time of painting.

FIG. 3 is an internal configuration diagram of a filling drawing unit.

FIG. 4 is an explanatory diagram of a scan order.

FIG. 5 is an explanatory diagram of a method for realizing left and right pixel masks.

FIG. 6 is an explanatory diagram of a page write cycle neck portion.

FIG. 7 is a configuration diagram of a filling drawing unit when interleaving is not performed.

FIG. 8 is a configuration diagram of a filling drawing unit in the case of interleaving.

FIG. 9 is an explanatory diagram of speeding up a page write cycle.

FIG. 10 is an explanatory diagram of speeding up a page write cycle during interleaving.

FIG. 11 is an explanatory diagram of a repeat pattern setting method and a speedup determination method.

FIG. 12 is an explanatory diagram of a repeat pattern setting method and a speed-up determination method.

FIG. 13 is an explanatory diagram of a memory cycle for realizing left and right end pixel masks.

FIG. 14 is an explanatory diagram of basic operation of RAS and CAS.

FIG. 15 is an explanatory diagram of an early write mode.

FIG. 16 is an explanatory diagram of a page write mode (early write mode).

FIG. 17 is an explanatory diagram of a mode other than early write.

FIG. 18 is an operation explanatory diagram of the memory with a mask write function.

FIG. 19 is an explanatory diagram of address and data skew with respect to CAS.

FIG. 20 is an explanatory diagram showing the proper use of a high speed buffer and a low speed buffer.

FIG. 21 is an explanatory diagram of a delay of an output buffer.

FIG. 22 is an explanatory diagram of a conventional page write cycle.

FIG. 23 is an explanatory diagram of a conventional page write cycle.

[Explanation of symbols]

10 ... CPU, 11 ... Main memory, 12 ... Fill drawing section,
13 ... Image memory, 14 ... Color lookup table, 15 ... Display device, 21 ... Rectangular area to be filled, 120
... Filling and drawing sequencer, 123 ... Sequencer LS
I, 124 ... Data creation LSI, 130, 131 ... Image memory banks, 400 ... Set periodic pattern, 40
1 ... size written by one writing, 402 ... maximum size of settable periodic pattern, 410 ... horizontal period of set periodic pattern, 411 ... horizontal direction written by one writing No. of pixels, 412 ... The maximum width of the cycle pattern that can be set.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Tsuzaki 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture Hitachi Systems Office Systems Division (72) Inventor Nori Kurokawa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Expression company Hitachi Microelectronics Equipment Development Laboratory (72) Inventor Hideo Haruta 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Micro Software Systems (72) Inventor Yasuhiro Furukawa Totsuka, Yokohama-shi, Kanagawa 292 Yoshida-cho, Tokyo, within Hitachi Micro Software Systems Co., Ltd. (72) Inventor, Hitoshi Kawaguchi 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Inside Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor, Okayama Kaoru Yokohama City Kanagawa Prefecture 292 Yoshida-cho, Tsuka-ku Inside Hitachi, Ltd. Microelectronics Device Development Laboratory

Claims (4)

[Claims] 1. A fill drawing apparatus for filling an image memory, which stores image data to be output to an output device of a computer system as pixel information, with a pixel value, and write data in successive writing to the image memory. And a determination unit that determines whether the write data does not change, and when the determination unit determines that the write data does not change, continuous writing to the image memory is performed at a speed faster than the limit due to the switching time of the write data. A fill drawing apparatus, comprising: a writing control unit, which speeds up fill drawing. 2. A fill drawing apparatus for interleaving a plurality of image memories for storing image data to be output to an output device of a computer system as pixel information, in an interleaved image memory. Write data, and a determination means for determining whether or not the write data in continuous writing to the image memory changes, and a write control for each image memory when the determination data determines that the write data does not change By writing signals simultaneously, and in continuous writing, the writing control means for continuously writing to the image memory at a speed faster than the limit by the data switching time is provided, thereby increasing the speed of fill drawing. A fill drawing device characterized by the above. 3. The filling / drawing device according to claim 1 or 2, wherein the filling / drawing device receives a periodic pattern and fills the image memory with the periodical pattern. A fill drawing apparatus characterized in that the judgment is made by judging whether or not the number of horizontal pixels to be filled is an integer multiple of the number of horizontal pixels of the periodic pattern. 4. The filling and drawing apparatus according to claim 1, wherein the filling and drawing apparatus receives the periodic pattern and fills the image memory with the periodic pattern. The periodic pattern is divided in the horizontal direction by the number of pixels in the horizontal direction, and the divided periodic patterns are compared with each other to determine whether or not they are all equal, thereby performing the determination by the determination means. Filling and drawing device characterized by.