JPH0766349B2 - Shifter circuit - Google Patents

Description

DETAILED DESCRIPTION [Outline] A shifter circuit that aligns a series of data read in word units with a write destination word based on a designated write destination address. Data is alternately stored in two sets of registers, each time the data is stored, the data is transferred in parallel to the shifter, and then rotational shift is performed according to the difference between the read address and the write address.
The multiplexer is configured to alternately take out the right or left word unit data after the rotation shift.

As described above, in the transfer of a series of data in word units, data that can be transferred by one write access can be obtained.

[Industrial application field]

The present invention relates to an improvement in a shifter circuit that performs a write operation on a bitmap memory or the like.

When a figure or the like is output on a display device, a printer, etc., a memory (bitmap memory) corresponding to the pattern data for one screen is provided to store the output information, and the output information is output by the reading method according to each output means. There is.

The writing of the pattern data to the bitmap memory is performed in word units for the purpose of speeding up, but it is necessary to align the write pattern data with a predetermined word address in the bitmap memory, and a shifter circuit is used. ing.

However, in the conventional shifter circuit, there is a problem that a continuous pattern cannot be obtained because the shift is performed word by word, and the number of write operations increases and the control becomes complicated.

Therefore, a high-speed and inexpensive shifter circuit is required.

[Conventional technology]

A conventional shifter circuit will be described by taking display movement processing in a display device as an example.

FIG. 2 (a) shows the configuration of the bitmap memory 1 of the CRT display device in association with the display screen. In the figure, 01, 02, ... 08 each represent a word-structured memory that stores the display information of the horizontal first raster of the screen in bit correspondence. Similar memories are provided for the raster in the vertical direction. There is.

When the pattern data in the area 2 on the screen is moved and displayed in the area 3, the start addresses M and N of the source and destination and the vertical and horizontal sizes of the area 2 are designated.

Area 2 of the move source of bitmap memory 1 by the above specification
Pattern data is read out and the writing process to the address in the area 3 is performed. Since this read / write process is performed in word units, it is necessary to match the intra-word addresses of the movement source and the movement destination, and the shift is performed. The operation is performed.

The shift operation will be described with reference to FIG.

In the movement processing from the area 2 to the area 3, the pattern data is sequentially read in word units from the head address M in the horizontal direction,
A shift operation is performed to write to the corresponding address in the area 3, and after the writing in the horizontal direction is completed, the operation is sequentially performed in the vertical direction.

FIG. 2B shows a processing method for moving the area 2a of one line in the horizontal direction to the area 3a. Word addresses of the area 2a are sequentially word 0, word 1, word 2, from the head address M, The word address of the area 3a is sequentially shown by word 0'and word 1'from the head address N, and FIG. 2 (b)-
(1) is a detailed view of area 2a, (8) is a detailed view of area 3a,
(2), (4), and (6) show data in which the contents of words 0, 1, and 2 are read out, and (3), (5), and (7) show a state in which the above data is shifted.

(A) First, the contents of word 0 are read [Fig. 2 (b)-
(2)], the address difference between the words of the addresses M and N is left-shifted with a shift amount [4 bits in the case of FIG. 2B].

(B) The above information is masked and written in the destination word 0 '.

(C) Next, after reading word 1, after performing a 4-bit shift (rotational shift), the region of the rotation-shifted (rotation) area is written in the destination word 0'with the left 12 bits masked, and the subsequent information is written. Write to word 1 '.

(D) The information in the area 2a is sequentially read word by word by the above method, and after shifting, the information is written in the area 3a.

The above procedure is stepped in the vertical direction and repeated to move the pattern data in the designated area.

[Problems to be solved by the invention]

As described above, the conventional method in which the bit map memory is read and shifted in word units and then written to the destination is increased in the number of times of writing and requires complicated control, which increases the processing time and becomes expensive. I had a problem.

[Means for solving problems]

The above-mentioned conventional problem is, as shown in FIG. 1 (a), a shifter circuit that aligns a series of data read in word units with write destination words, and the read data is written in word units. Two sets of registers (A, B) that are alternately stored and two words of data stored in the above two sets of registers are transferred in parallel, depending on the difference between the read source address and the write destination word address. A multiplexer (11) for alternately selecting and extracting a pair of right-side or left-side word data as write destination word data from the shifter (10) rotationally shifted to the left and the two-word data after the rotational shift. This can be solved by a shifter circuit having

[Action]

The sequentially read data in word units are alternately stored in the registers A and B. Then, for each storage, the data of the two words is transferred to the shifter 10 in parallel, and is rotationally shifted (rotated) to the right or left according to the difference between the addresses in the read source and write destination words. And
Right or left one-word data is alternately taken out of the shifter 10 that has been rotationally shifted.

As described above, the write data aligned with the write destination word is obtained. Therefore, when a series of data is moved word by word in the bit map memory, etc., when the read source address and the write destination address in the word are different, the data can be transferred by one read and one write access. Become.

〔Example〕

 An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 (a) is a block diagram of the present invention, FIG. 1 (b) is an operation time chart, FIG. 1 (c) is a left shift operation principle diagram, and FIG. 1 (d) is a right shift operation principle diagram. is there.

〔Operating principle〕

The operation principle of each of the left shift and the right shift will be described with reference to FIGS.

(1) Figure 1 (c) shows the case of left shift.
Each of A and B is a 1-word register, 10 is a shifter that rotates (rotates) a 2-word width by a predetermined amount, and outputs the contents after the shift by 2 words, and 11 is a multiplexer.

To shift left, first write the contents of word 0 to the A register,
Then, word 1 is written into the B register.

The shifter 10 to which the contents of the two words of the A and B registers are input shifts in the designated direction by the designated amount and then outputs the same. The multiplexer 11 selectively outputs the upper 10a of the shifter 10.

Subsequently, word 2 is written in the A register, and after a predetermined amount of rotational shift as shown in FIG. 1 (c), the lower 10b data of the shifter 10 is selectively output. As a result, data aligned with the write destination word is obtained as shown by word 0'and word 1'in FIG. 1 (c). It should be noted that when writing the first word and the last word, if necessary (for example, 0 to 4 bits of word 0 ') are masked, it is not necessary to mask other words in the meantime, and only one write access is required. Can be crowded.

The shift direction and shift amount are determined by the source and destination head addresses.

(2) FIG. 1 (d) shows the case of right shift.
First write word 0 to register A, then multiplexer 11
Selects and outputs the upper 10a of the shifter 10. Then word 1
Is written in the B register, the lower 10b of the shifter 10 is selected and output, then the word 2 is written in the A register, and the shifter 10a is selected and output.

By the above processing, the continuous pattern data can be aligned in the destination words 0 ', 1', 2'as shown in FIGS. 1 (c) and (d), and the number of times of writing can be reduced.

〔Constitution〕

In FIG. 1A, 12 is a shifter control circuit, 13 is a flip-flop, and 14 and 15 are NAND circuits.

The shifter control circuit 12 determines the shift amount and the shift direction based on the write command to the A and B registers and the move source and move destination head addresses, and sends the shift amount to the shifter 10 and the aforementioned selection signal to the multiplexer 11, respectively. It has a function to do.

The flip-flop 13 and the NAND circuits 14 and 15 constitute a circuit that sends a write command to the A and B registers.

Throughout all the other drawings, the same symbols represent the same objects.

[Description of Operation] The operation of each unit will be described with reference to the operation time chart of FIG.

(1) The read signal [FIG. 1 (b)-(3)] read word by word from the bit map memory is the write command (b).
-(1), (b)-(2) are alternately stored in the A register and the B register and input to the shifter 10, respectively.

(2) The shifter 10 shifts a predetermined amount according to a shift command designating a shift amount and a shift direction, and outputs it in parallel for two words.

(3) By multiplexer 11, upper 10a of shifter 10
And the shift output of the lower 10b are alternately selected and output as the destination write signals (b)-(7).

Note that (b) to (6) show selection signals at the time of left shift.

The write signals (b)-(6) output by the above processing are written in the destination word address as described above.

〔The invention's effect〕

As described above, according to the present invention, since the continuous pattern data twice as large as the write unit is shifted by the predetermined amount, the continuous pattern data write information can be obtained even after the shift.
By reducing the number of writing operations, it is possible to reduce the cost and speed up the writing operation.

[Brief description of drawings]

1A is a block diagram of the present invention, FIG. 1B is an operation time chart, FIG. 1C is a left shift operation principle diagram, and FIG. 1D is a right shift operation principle diagram. FIG. 2 (a) is a diagram showing a bitmap memory of a CRT display device, and FIG. 2 (b) is a diagram illustrating a conventional bitmap memory moving processing method. 1 is a bitmap memory, 10 is a shifter 10a is an upper part of the shifter 10, 10b is a lower part of the shifter 10, 11 is a multiplexer, 12 is a shifter control circuit, 13 is a flip-flop, 14,15 is a NAND circuit, A and B are registers ,.

Front page continuation (72) Inventor Hisao Kobayashi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP-A-48-68209 (JP, A) JP-A-49-98537 (JP, A)

Claims (1)

[Claims] 1. A shifter circuit for arranging a series of data read in word units into write destination words, wherein the read data are alternately stored in word units.
A pair of registers (A, B) and the two-word data stored in the above two sets of registers are transferred in parallel, and the shifter rotates right or left according to the difference between the read-source and write-destination word addresses. (1
0) and 1 word on the right side or the left side as the write destination word data from the 2-word data of the shifter after the rotation shift.
And a multiplexer (11) for alternately selecting and extracting a set of word data.