JPH0846209A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To remove defects concentrating and existing on the surfaces of a source region and a drain region by forming an active layer, in which at least the source region and the drain region and a channel forming region are formed, and etching the surfaces of the source region and the drain region in thickness of a specific value or less. CONSTITUTION:Impurity ions are implanted into source-drain regions, and the surfaces of the source/drain regions 200 are etched in thickness of 100Angstrom . The regions 200 may by etched in thickness of approximately 50-500Angstrom . Regions, in which there are defects on the surfaces of the source region 209 and the drain region 210 concentrically, can be removed through the process. The source/ drain regions are recrystallized and activated by applying laser beams or intense light. Defects do not exist on the surfaces of the source/drain regions concentrically at that time, thus preventing absorption to the surfaces of laser beams or intense light.

Description

Detailed Description of the Invention

[0001]

2. Description of the Related Art Conventionally, a thin film transistor (commonly referred to as a TFT) formed on a substrate having an insulating surface such as glass has been known. This thin film transistor is used for a thin film integrated circuit such as a memory, or is arranged in a pixel portion of an active matrix type liquid crystal display device and used for driving a pixel.

An amorphous silicon film or a crystalline silicon film constitutes a thin film transistor formed on a glass substrate or the like. When an amorphous silicon film is used, there is a problem that the device characteristics are not sufficient. On the other hand, when a crystalline silicon film is used, high mobility and high switching speed can be obtained. The crystalline silicon film means a silicon film containing a crystal component such as polycrystalline silicon or microcrystalline silicon.

However, a thin film transistor using a crystalline silicon film has a problem that an OFF current (also called a leak current) is large. This is because it is practically impossible to obtain a crystalline silicon film having a single crystal structure, and many crystalline grain boundaries are present in the obtained crystalline silicon film. That is, during the OFF operation of the thin film transistor, carriers move through the crystal grain boundaries in the active layer, particularly the crystal grain boundaries in the vicinity of the interface between the channel formation region and the drain region, and the OFF current is It is the cause of existence.

As a method for solving the above problems, LDD
(Light-doped-drain) and offset gate structures are known. These configurations alleviate the electric field concentration at the interface between the channel formation region and the drain region and in the vicinity thereof, and prevent or reduce the movement of carriers via the crystal grain boundaries described above during the OFF operation. With the goal.

However, even if the above LDD structure or offset gate structure is adopted, the required O is sufficiently low.
At present, the FF current cannot be obtained. In particular, when a thin film transistor is used in an active matrix type liquid crystal display device, electric charges must be retained in the pixel electrode for a predetermined time.
The current needs to be as small as possible.

[Process leading to the invention] As a configuration for obtaining a lower OFF current than when the LDD structure or the offset gate structure is adopted, there is a structure as shown in FIG. Figure 2
The configuration as shown in FIG.
No. 563 and Japanese Patent Application No. 6-17015.

The thin film transistor shown in FIG. 2 is (D),
Source / drain regions 209 and 21 as shown in FIG.
0, lightly doped region 214, offset gate region 2
15 and. Then, the lightly doped region 214
And the offset gate region 215 alleviate the concentration of the electric field at the interface between the source / drain region and the channel forming region 216 and its vicinity, and particularly at the interface between the drain region 210 and the channel forming region 216 and its vicinity, and reduce It realizes an OFF current value.

A manufacturing process of the thin film transistor shown in FIG. 2 will be described. First, a silicon oxide film serving as a base film is formed on the glass substrate 201 to a thickness of 2000 Å by a sputtering method. Next, an amorphous silicon film is formed by a plasma CVD method or a low pressure thermal CVD method, and heating or laser light irradiation is performed to obtain a crystalline silicon film. Then, the crystalline silicon film is patterned to obtain the active layer 203. After the active layer 203 is obtained, a silicon oxide film 204 functioning as a gate insulating film is formed with a thickness of 1000Å by the plasma CVD method.

Further, a gate electrode 205 is formed by forming an aluminum film having a thickness of 5000 Å and containing 0.1% by weight of scandium by a sputtering method and performing patterning. Then, the substrate is immersed in an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia, and anodization is performed using the gate electrode 205 as an anode. Here, a thin anodic oxide layer (not shown) of about 200 Å is formed by this anodic oxidation.

Then, a resist mask 206 is formed.
Then, the substrate is immersed in a 10% nitric acid aqueous solution and anodized to form an anodic oxide layer 207 having a porous structure with a thickness of about 5000 Å. The gate electrode 20
Since the resist mask 206 exists on the upper surface of No. 5, the oxide layer is not formed. (FIG. 2 (B))

Next, the resist mask 206 is removed to expose the upper surface of the gate electrode 205. Then, the substrate is immersed in an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia, and anodization is performed using the gate electrode 205 as an anode. Here, this anodic oxidation causes 10
An oxide layer 208 is formed to a thickness of 00Å. Figure 2 (C)

Next, the exposed portion of the silicon oxide film 204 is etched by dry etching. After this etching, the portion indicated by 203 'of the silicon oxide film remains. Here, the active layer 203 is doped with an impurity imparting one conductivity type by an ion implantation method or a plasma doping method. In this step, the gate electrode 205, the porous anodic oxide layer 207 around the gate electrode, and the dense anodic oxide layer 208 serve as a mask, and the source region 209 and the drain region 210 are formed in a self-aligned manner.

At this time, a pair of lightly doped regions 21 are formed.
4 and the pair of offset gate regions 215 are formed in a self-aligned manner. The light-doped region 214 is formed because the remaining silicon oxide film 203 ′ is present, and the amount thereof is reduced when the ions permeate the silicon oxide film 203 ′. Thus, the offset gate region and the lightly doped region are formed between the channel forming region and the source / drain regions. (Fig. 2 (E))

Then, the interlayer insulating film 211 is made of a silicon oxide film or the like, and a source electrode 212 and a drain electrode 213 are formed through a hole forming process, so that the source electrode 212 and the drain electrode 213 are formed, as shown in FIG.
The thin film transistor shown in is completed.

The thin film transistor as shown in FIG. 2 can suppress the OFF current lower than that of the conventional thin film transistor having the LDD structure or the offset gate structure. However, ・ Various characteristics such as mobility are low. -The characteristics vary greatly.・ Significant deterioration of characteristics. There is such a problem.

As a result of examining the above problems, the present inventors have obtained the following findings. That is, in the step shown in FIG. 2D, the exposed source region 20
Impurity ions are implanted into the drain region 9 and the drain region 210, but at this time, the surface of the source / drain region is greatly damaged by the impact of the ions, and the surface state becomes uneven or rough. As a result, defects are concentrated on the surface of the source / drain region.

As a result of defects being concentrated on the surface of the source / drain region, the following problems are considered to occur. (1) Defects on the surface of the source / drain region cause variations and deterioration in characteristics of the thin film transistor. (2) Carriers that conduct in the source / drain regions (carriers move in the vicinity of the surface of the active layer) are trapped and scattered by defects that are concentrated on the surface of the source / drain regions. Therefore, various characteristics of the thin film transistor such as mobility are deteriorated. (3) After the step shown in FIG. 2D, when the source / drain regions are crystallized and activated by irradiation with laser light, the laser light is intensively absorbed by defects on the surface of the source / drain regions. As a result, recrystallization and activation of the source / drain regions cannot be performed sufficiently.

The surface of the source / drain region is covered with a silicon oxide film or the like, and if impurity ions are implanted through the film covering the surface of the source / drain region, the above problem occurs. Absent. That is, in this case, defects are not concentrated on the surface of the source / drain region.

[0019]

SUMMARY OF THE INVENTION The invention disclosed in this specification aims to obtain at least one of the following items. (1) To solve the problem of defect concentration on the surface of the source / drain region due to the implantation of impurity ions into the source / drain region. (2) Defects concentrate on the semiconductor surface when ions are implanted.

[0020]

A main invention disclosed in the present specification has an active layer in which at least a source region, a drain region and a channel forming region are formed, and the source region and the drain region are provided. Is characterized by being etched to a thickness of 50Å or more.

A specific configuration of the above configuration is shown in FIG. In the thin film transistor shown in FIG. 1, the surfaces of the source / drain regions shown by 209 and 210 are etched as shown by 200. This etching is source /
Since it is intended to remove defects concentrated on the surface of the drain region, it is necessary to remove at least the surface of the active layer with a thickness of 50 Å or more.

In the invention disclosed in this specification, it is effective to use, as a semiconductor layer or an active layer, a crystalline silicon film crystallized by the action of a metal element that promotes crystallization of silicon. As the metal element that promotes the crystallization of silicon, Ni (nickel) can be mentioned as a material having a particularly remarkable effect. For example, if a thin film of Ni is formed on the surface of the amorphous silicon film and then the amorphous silicon film is crystallized by heating, 550
A crystalline silicon film having sufficient crystallinity can be obtained by heating at 4 ° C. for about 4 hours. This is 60 in the past.
It can be said that this is extremely superior and significant as compared with the case where the heat treatment at a temperature of 0 ° C. or higher for 12 hours or longer was required.

The metal elements that promote the crystallization of silicon are Fe, Co, Ni, Ru, Rh, Pd, and O.
One or more elements selected from s, Ir, Pt, Cu, Ag, and Au can be used.

The metal element that promotes the crystallization of silicon (especially in the case of Ni) is within the concentration range of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ cm ^{-3 in} the crystallized silicon film. It is desirable to go out. If the density is lower than this,
This is not preferable because the promotion effect during crystallization becomes small. On the other hand, if the concentration is higher than this concentration, the electrical characteristics of the obtained crystalline silicon film will be metallic, which is not preferable.

Another main structure disclosed in the present specification has an active layer in which at least a source region, a drain region and a channel forming region are formed, and the surface of the source region and the drain region is 50 Å or more. It is characterized in that it is etched to a thickness, and a metal compound layer is formed on the surfaces of the source region and the drain region.

In the above structure, the metal compound layer formed on the surfaces of the source region and the drain region is the source / source layer.
It is formed by forming a metal thin film on the drain region and then performing heat treatment or laser light irradiation. As the metal used here, one or more kinds selected from titanium, nickel, molybdenum, tungsten, platinum and palladium can be used.

The presence of the metal compound layer can prevent the source / drain regions that have been thinned by etching from being etched and opened in a later step of forming a contact hole. In particular, when a crystalline silicon film is obtained by introducing the above-mentioned metal element that promotes crystallization of silicon, the hydrofluoric acid resistance of the crystalline silicon is greatly reduced. For example, only the silicon oxide film is not etched. Even in such a case, the crystalline silicon film (having hydrofluoric acid resistance) is also etched.
Therefore, it is extremely useful to form a metal compound on the exposed surface of the active layer containing the metal element that promotes the crystallization of silicon to enhance the etching resistance of the active layer.

Another structure of the present invention is a method of manufacturing a thin film transistor having an active layer in which at least a source region, a drain region and a channel forming region are formed, wherein impurity ions are implanted into the exposed source region and drain region. And performing a step of etching the surfaces of the source region and the drain region.

Another structure of the present invention is a method for manufacturing a thin film transistor having an active layer in which at least a source region, a drain region and a channel forming region are formed, wherein impurity ions are implanted into the exposed source region and drain region. And a step of removing the surface of the source and drain regions damaged in the step.

Another structure of the present invention is a method of manufacturing a thin film transistor having an active layer in which at least a source region, a drain region and a channel forming region are formed, wherein impurity ions are implanted into the exposed source region and drain region. And a step of etching the surface of the source region and the drain region, and a step of forming a metal compound layer on the surface of the source region and the drain region.

[0031]

By implanting impurity ions into the exposed semiconductor layer and then removing the surface of the semiconductor layer, the defects concentrated on the surface of the semiconductor layer can be removed. It is possible to solve various problems (for example, deterioration of characteristics of a semiconductor device) caused by the problems.

For example, when the source / drain regions of the thin film transistor are formed by implanting impurity ions,
If impurity ions are directly implanted into the exposed active layer, defects due to ion damage are concentrated on the surface of the active layer, which causes deterioration and instability of characteristics of the obtained thin film transistor. In this case, after the implantation of the impurity ions, the surface of the implantation region of the ions is removed by etching, and the defects existing concentrated on the surface are removed, thereby suppressing the deterioration and instability of the characteristics of the thin film transistor. can do.

Further, when the surface of the source / drain region of the thin film transistor is removed by etching, a problem caused by thinning of the active layer by forming a metal compound layer on the surface of the source / drain region (after-hole formation) In the process, the problem that the source / drain regions are etched) can be solved.

[0034]

【Example】

[Embodiment 1] FIG. 1 illustrates a manufacturing process of a thin film transistor of this embodiment. First, a silicon oxide film 202 serving as a base film is formed on a glass substrate 201 to a thickness of 2000 Å by a sputtering method. Next, plasma CVD or reduced pressure heat C
An amorphous silicon film is formed by the VD method. Then, a nickel acetate solution is used to introduce Ni, which is a metal element that promotes crystallization, into the amorphous silicon film. Here, the nickel acetate solution is spin-coated on the surface of the amorphous silicon film by the spin coating method to introduce Ni element into the amorphous silicon film.

Then, a crystalline silicon film is obtained by heat treatment at 550 ° C. for 4 hours. Then, the crystalline silicon film is patterned to obtain the active layer 203. When the active layer 203 is obtained, the silicon oxide film 204 functioning as a gate insulating film is set to 1000
It is formed to a thickness of Å by the plasma CVD method.

Further, a gate electrode 205 is formed by forming an aluminum film having a thickness of 5000 Å and containing 0.1% by weight of scandium by a sputtering method and performing patterning. Then, the substrate is immersed in an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia, and anodization is performed using the gate electrode 205 as an anode. Here, a thin anodic oxide layer (not shown) of about 200 Å is formed by this anodic oxidation.

After the anodizing step, the resist mask 2
06 is formed. Then, the substrate is immersed in a 10% nitric acid aqueous solution and anodized to form an anodic oxide layer 207 having a porous structure with a thickness of about 5000 Å. A resist mask 206 is formed on the upper surface of the gate electrode 205.
Is present, no oxide layer is formed. (Figure 1
(B))

Next, the resist mask 206 is removed and the upper surface of the gate electrode 205 is exposed. Then, the substrate is immersed in an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia, and anodization is performed using the gate electrode 205 as an anode. Here, 20
An oxide layer 208 is formed to a thickness of 00Å. (Figure 1
(C))

Next, the exposed portion of the silicon oxide film 204 is etched by dry etching. After this etching, the portion indicated by 203 'of the silicon oxide film remains. Here, the active layer 203 is doped with an impurity imparting one conductivity type by an ion implantation method or a plasma doping method. Here, phosphorus ion doping is performed.

In this step, the gate electrode 205,
Using the porous anodic oxide layer 207 and the dense anodic oxide layer 208 around the gate electrode as a mask, the source region 209 and the drain region 210 are formed in a self-aligned manner.

At this time, a pair of light-doped regions 21
4 and the pair of offset gate regions 215 are formed in a self-aligned manner. The light-doped region 214 is formed because the remaining silicon oxide film 203 ′ is present, and the amount thereof is reduced when the ions permeate the silicon oxide film 203 ′. Thus, the offset gate region and the lightly doped region are formed between the channel forming region and the source / drain regions. (Fig. 1 (D))

After implanting the impurity ions into the source / drain regions, the surface of the source / drain regions is etched to a thickness of 100Å, as indicated by 200. The thickness of this etching may be, for example, about 50 to 500 Å. In this step, the source region 209 and the drain region 21
Regions where defects are concentrated on the 0 surface can be removed. Here, this etching is performed by wet etching using hydrofluoric nitric acid. (Figure 1
(E))

After obtaining the state shown in FIG. 1E, laser light or intense light is irradiated to recrystallize the source / drain regions (the source / drain regions are amorphized at the time of implanting impurity ions). Have been activated) and activation. At this time, since the defects are not concentrated on the surface of the source / drain region, it is possible to prevent the laser light or the strong light from being absorbed on the surface. Then, the entire source / drain region can be uniformly annealed.

Instead of irradiating the source / drain regions with laser light or strong light, a heating method may be used. In addition to irradiation with laser light or strong light,
It is effective to use the heating method together.

After the annealing of the source / drain regions is completed, a silicon oxide film 211 is formed as an interlayer insulating film by a plasma CVD method, and a source electrode 212 and a drain electrode 213 are formed through a hole forming process. . Then, heat treatment is performed for 1 hour in a hydrogen atmosphere at 350 ° C., whereby the thin film transistor illustrated in FIG. 1F is completed.

It is effective to form a metal compound layer on the surface of the source / drain regions in the step (E) of this embodiment. This is because it is possible to prevent the source / drain region from being over-etched in the step of boring the source / drain region due to the fact that the thickness of the source / drain region becomes thin due to the etching of the surface. is there.

[Embodiment 2] This embodiment relates to the structure of a thin film transistor having no offset gate region or lightly doped region. FIG. 3 shows the manufacturing process of this embodiment.
First, as shown in (A), a glass substrate 301 is prepared, and a silicon oxide film is used as a base film on the glass substrate 301.
A film is formed to a thickness of 00Å by a sputtering method. Next, an amorphous silicon film is formed to a thickness of 500Å by plasma CVD method or low pressure thermal CVD method.

Then, the surface of the amorphous silicon film is spin-coated with a nickel acetate solution and heat-treated at 550 ° C. for 4 hours to obtain a crystalline silicon film. Further patterning is performed to obtain the active layer 303 made of a crystalline silicon film.

Next, a silicon oxide film 304 functioning as a gate insulating film is formed by plasma CVD or sputtering to a thickness of 1000 Å. Further, a film containing microcrystalline silicon having one conductivity type (here, N type) as a main component is formed to a thickness of 5000 Å by a low pressure thermal CVD method, and patterned to form a gate electrode 305.

Simultaneously with or after the formation of the gate electrode, the silicon oxide film 304 is patterned to form regions (306, 3) to be source / drain regions as shown in FIG. 3B.
(Area indicated by 08) is exposed. Then, phosphorus, which is an impurity imparting N-type conductivity, is implanted by ion implantation or plasma doping using the gate electrode 305 as a mask. By the implantation of the impurity ions, the source region 30
6, the drain region 308, and the channel formation region 307 are formed in a self-aligned manner.

In the step of implanting the impurity ions, the exposed surface of the active layer 303 is greatly damaged.
Therefore, the damaged surface of the active layer is removed by etching in the step (C). Here, the exposed active layer is etched to a thickness of 200 Å by wet etching using hydrogen peroxide. In this etching process, it is possible to remove the damage at the time of ion implantation concentrated on the upper part of the active layer.

In the above step, an etchant obtained by mixing perhydrogen ammonia with a surfactant is used. This is to enhance the flatness of the surface of the active layer.

Further, a titanium film having a thickness of 50 to 500 Å here is formed on the entire surface by a sputtering method to a thickness of 200 Å, and heat treatment is performed to form a titanium silicide film (metal compound layer) 309. The source region 306 and the drain region 308, into which the impurity ions have been implanted in the previous ion implantation step, are activated. The titanium film is removed after the titanium silicide film is formed.

The metal compound layer may be formed and the source / drain regions may be activated by irradiation with laser light or intense light instead of heating.

Then, a silicon oxide film 31 is formed as an interlayer insulating film.
0 is deposited to a thickness of 7000Å, and a source electrode 311 and a drain electrode 312 are formed by laminating a titanium nitride film (a titanium film may be used) and an aluminum film through a hole forming process. The use of the titanium nitride film here is useful for obtaining good contact between the source / drain regions and the source / drain electrodes.

The source region 306 and the drain region 30
In the step of forming the hole in FIG. 9, since the titanium silicide film is formed on the upper surface of the source / drain region, the source / drain region is over-etched due to the process variation (holes are formed in the source / drain region). Can be prevented. Particularly, in the structure shown in this embodiment, the nickel concentration in the active layer is 10 ¹⁸ cm.
^-3 , the etching selectivity for the silicon oxide film is greatly reduced. Therefore, by forming the titanium silicide film on the exposed surface of the active layer, the problem of etching selectivity can be solved. Then, a thin film transistor is completed by performing a heat hydrogenation treatment at 350 ° C. in a hydrogen atmosphere.

[0057]

EFFECTS OF THE INVENTION By removing by etching the defects on the surface of the active layer caused by the implantation of impurity ions into the exposed active layer, the characteristics such as mobility are high and the characteristics can be stably obtained. It is possible to obtain a thin film transistor whose characteristics do not vary.

[Brief description of drawings]

FIG. 1 shows a manufacturing process of a thin film transistor.

2A to 2C show a manufacturing process of a thin film transistor.

FIG. 3 shows a manufacturing process of a thin film transistor.

[Explanation of symbols]

201, 301 Glass substrate 202, 302 Silicon oxide film (base film) 203, 303 Active layer 204, 304 Silicon oxide film (gate insulating film) 205, Gate electrode made of a material containing aluminum as a main component 206 Resist mask 207 Porous Anodic oxide layer 208 dense anodic oxide layer 209, 306 source region 203 ', 304 remaining gate insulating film 210, 308 drain region 214 lightly doped region 215 offset gate region 216, 307 channel forming region 211, 310 interlayer insulation Film 212, 311 Source electrode 213, 312 Drain electrode 309 Titanium silicide film (metal compound layer) 305 Gate electrode

Claims (14)

[Claims] 1. An active layer having at least a source region, a drain region and a channel forming region formed therein, wherein the surface of the source region and the drain region is etched to a thickness of 50 Å or more. Semiconductor device. 2. An active layer having at least a source region, a drain region and a channel forming region formed therein, wherein the surfaces of the source region and the drain region are etched to a thickness of 50 Å or more. A semiconductor device, wherein a metal compound layer is formed on the surfaces of the drain region and the drain region. 3. The active layer according to claim 1, wherein the active layer contains 1 × 10 ¹⁵ cm of a metal element that promotes crystallization of silicon.
^-3 to 1 × 10 ¹⁹ cm ^-3 contained in the semiconductor device. 4. The semiconductor device according to claim 3, wherein Ni element is used as the metal element. 5. The metallic element according to claim 3,
Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, C
A semiconductor device, wherein one or more elements selected from u, Ag, and Au are used. 6. A method of manufacturing a thin film transistor having an active layer in which at least a source region, a drain region, and a channel forming region are formed, wherein after implanting impurity ions into the exposed source region and drain region, A method for manufacturing a semiconductor device, comprising a step of etching the surfaces of a source region and a drain region. 7. A method of manufacturing a thin film transistor having an active layer in which at least a source region, a drain region, and a channel formation region are formed, the step of implanting impurity ions into the exposed source region and drain region, A step of removing the surface of the source and drain regions damaged in the step, and a method of manufacturing a semiconductor device. 8. A method of manufacturing a thin film transistor having an active layer in which at least a source region, a drain region and a channel forming region are formed, the step of implanting impurity ions into the exposed source region and drain region, A method of manufacturing a semiconductor device, comprising: a step of etching the surface of the source region and the drain region; and a step of forming a metal compound layer on the surface of the source region and the drain region. 9. A method of manufacturing a thin film transistor having an active layer in which at least a source region, a drain region, and a channel forming region are formed, the step of implanting impurity ions into the exposed source region and drain region, A semiconductor comprising: a step of removing the surface of the source and drain regions damaged in the step; and a step of forming a metal compound layer on the surfaces of the etched source and drain regions. Method for manufacturing device. 10. The method for manufacturing a semiconductor device according to claim 6, wherein Ni element is used as the metal element. 11. The metal element according to claim 6, wherein Fe, Co, Ni, Ru, Rh, Pd, Os, and
A method of manufacturing a semiconductor device, wherein one or more kinds of elements selected from Ir, Pt, Cu, Ag and Au are used. 12. A method for manufacturing a semiconductor device, comprising: a step of implanting impurity ions into an exposed semiconductor; and a step of removing a surface of the semiconductor into which the impurity ions are implanted. 13. The N as the metal element according to claim 12.
A method for manufacturing a semiconductor device, wherein an i element is used. 14. The metal element according to claim 12, which is F.
e, Co, Ni, Ru, Rh, Pd, Os, Ir, P
A method of manufacturing a semiconductor device, wherein one or more kinds of elements selected from t, Cu, Ag, and Au are used.