JPH0846081A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPH0846081A JPH0846081A JP17887294A JP17887294A JPH0846081A JP H0846081 A JPH0846081 A JP H0846081A JP 17887294 A JP17887294 A JP 17887294A JP 17887294 A JP17887294 A JP 17887294A JP H0846081 A JPH0846081 A JP H0846081A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- semiconductor chip
- area
- hole
- mounting area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップを搭載す
る搭載域、この搭載域の周囲に半導体チップに接続され
る配線パターンを備えたチップキャリアに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting area for mounting a semiconductor chip and a chip carrier having a wiring pattern connected to the semiconductor chip around the mounting area.
【０００２】[0002]
【従来の技術】従来、半導体チップを搭載する搭載域，
この搭載域の周囲に半導体チップに接続される配線パタ
ーン、および同電位の複数の回線を備えたチップキャリ
アが知られている。このチップキャリアは、半導体チッ
プにボンデングワイヤ等で接続される配線パターンとこ
の配線パターンから間隔をおいて絶縁された同電位の複
数の回線を同一面の同一領域内に形成されているが故
に、配線パターンの密度が高まり、その結果、配線パタ
ーンの自由度が減少するだけでなく配線パターン内の相
互の短絡が発生するおそれがあり、信頼性の点でも問題
であった。2. Description of the Related Art Conventionally, a mounting area for mounting a semiconductor chip,
There is known a chip carrier having a wiring pattern connected to a semiconductor chip and a plurality of lines having the same potential around the mounting area. Since this chip carrier has a wiring pattern connected to a semiconductor chip with a bonding wire or the like and a plurality of lines of the same potential insulated at intervals from the wiring pattern in the same area on the same surface. The density of the wiring pattern is increased, and as a result, not only the degree of freedom of the wiring pattern is reduced, but also short circuits may occur in the wiring pattern, which is a problem in terms of reliability.
【０００３】[0003]
【発明が解決しようとする課題】本発明は上記の事情に
鑑みてなされたもので、その目的とするところは、配線
パターンの自由度の増大と配線パターン内の相互の短絡
を回避するのに有用なチップキャリアを提供するもので
ある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to increase the degree of freedom of wiring patterns and to prevent short circuits between the wiring patterns. It is intended to provide a useful chip carrier.
【０００４】[0004]
【課題を解決するための手段】本発明の請求項１に係る
チップキャリアは、半導体チップを搭載する搭載域１、
この搭載域１の周囲に半導体チップに接続される配線パ
ターン２、および配線パターン２と搭載域１との間にべ
た張りの同電位の導電体域３を上面に、この導電体域３
に導通するスルホール４とこのスルホール４に導通する
回線５を内層６に、さらにスルホール４に導通する端子
７を下面に備えたことを特徴とするものである。A chip carrier according to claim 1 of the present invention comprises a mounting area 1 for mounting a semiconductor chip,
The wiring pattern 2 connected to the semiconductor chip around the mounting area 1 and the conductor area 3 having the same electric potential, which is sticky between the wiring pattern 2 and the mounting area 1, are provided on the upper surface.
The inner layer 6 is provided with a through hole 4 which is electrically connected to the through hole 4 and a line 5 which is electrically connected to the through hole 4, and a terminal 7 which is electrically connected to the through hole 4 is provided on the lower surface.
【０００５】[0005]
【作用】本発明の請求項１に係るチップキャリアは、半
導体チップＣを搭載する搭載域１、この搭載域１の周囲
に半導体チップＣに接続される配線パターン２、および
配線パターン２と搭載域１との間にべた張りの同電位の
導電体域３を上面に、この導電体域３に導通するスルホ
ール４とこのスルホール４に導通する回線５を内層６
に、さらにスルホール４に導通する端子７を下面に備え
るので、べた張りの同電位の導電体域３は、半導体チッ
プＣに接続される配線パターン２と半導体チップＣを搭
載する搭載域１の間に形成され、同電位の導電体域３の
導通する回線は配線パターン２が形成された上面とは異
なる内層６に形成されているので、同一面内で同一領域
内に半導体チップＣに接続される配線パターンと同電位
の複数の回線を備えた従来のチップキャリアと比べる
と、配線パターンの密度は低下する。In the chip carrier according to claim 1 of the present invention, the mounting area 1 for mounting the semiconductor chip C, the wiring pattern 2 connected to the semiconductor chip C around the mounting area 1, and the wiring pattern 2 and the mounting area are provided. The upper surface is a conductor region 3 having the same potential as that of the conductor 1 and a through hole 4 conducting to the conductor region 3 and a line 5 conducting to the through hole 4 are the inner layer 6
In addition, since the terminal 7 which is electrically connected to the through hole 4 is provided on the lower surface, the solid conductor area 3 having the same potential is provided between the wiring pattern 2 connected to the semiconductor chip C and the mounting area 1 on which the semiconductor chip C is mounted. Since the conductive line of the conductor area 3 having the same potential is formed in the inner layer 6 different from the upper surface on which the wiring pattern 2 is formed, it is connected to the semiconductor chip C in the same area in the same surface. The density of the wiring pattern is lower than that of a conventional chip carrier having a plurality of lines having the same potential as the wiring pattern.
【０００６】[0006]
【実施例】以下、本発明を図面を援用しながら説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【０００７】図１は、本発明の一実施例に係るチップキ
ャリアの平面図で、図２は図１のＹ−Ｙ断面図である。
図示の如く、本発明のチップキャリアは、絶縁基板１０
の上面に半導体チップＣを搭載する搭載域１が形成され
ている。この搭載域１を囲む周囲には、この搭載域１に
搭載される半導体チップＣにたとえばボンデングワイヤ
で接続される配線パターン２が形成されている。この配
線パターン２はインナーリードとも呼ばれ、マザーポー
ドのプリント回路板の回路パターンに導通するものであ
る。FIG. 1 is a plan view of a chip carrier according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line YY of FIG.
As shown in the figure, the chip carrier of the present invention comprises an insulating substrate 10
A mounting area 1 for mounting the semiconductor chip C is formed on the upper surface of the. A wiring pattern 2 connected to the semiconductor chip C mounted in the mounting area 1 by, for example, a bonding wire is formed around the mounting area 1. The wiring pattern 2 is also called an inner lead, and is electrically connected to the circuit pattern of the mother board printed circuit board.
【０００８】この配線パターン２と搭載域１との間に
は、べた張りの同電位の導電体域３が上記搭載域１を囲
む形態で形成され、したがって絶縁基板１０の同一面で
ある上面には、搭載域１とこの搭載域１に搭載される半
導体チップＣに接続される配線パターン２とべた張りの
同電位の導電体域３とが形成されている。すなわち、べ
た張りの同電位の導電体域３を搭載域１と配線パターン
２との間に形成することによって、配線パターンと同一
の領域内に形成されていた複数の同電位の回線を配線パ
ターンの領域外に移転し、その結果、多数の回線が集合
した配線パターンの回線の密度は低下する。これによ
り、配線パターンの自由度の増大と配線パターン内の相
互の短絡を回避することができる。Between the wiring pattern 2 and the mounting area 1, a solid conductive area 3 having the same potential is formed so as to surround the mounting area 1. Therefore, the insulating substrate 10 is provided on the same upper surface of the insulating substrate 10. The mounting area 1 and the wiring pattern 2 connected to the semiconductor chip C mounted on the mounting area 1 and the conductor area 3 having the same electric potential and being solid are formed. That is, by forming the sticky conductor region 3 having the same potential between the mounting region 1 and the wiring pattern 2, a plurality of lines having the same potential formed in the same region as the wiring pattern are connected to the wiring pattern. , The density of the lines of the wiring pattern in which a large number of lines are gathered is reduced. Thereby, the degree of freedom of the wiring pattern and the short circuit between the wiring patterns can be avoided.
【０００９】本発明のチップキャリアは、さらに絶縁基
板１０を貫通するスルホール４が形成され、このスルホ
ール４は、導電体域３に導通するスルホールである。こ
のスルホール４には、絶縁基板１０の下面に層着された
絶縁基板１１とこの絶縁基板の上面に形成された複数本
の回線５とを備えた内層材１２の回線５が導通し、した
がって、導電体域３に導通する回線５は内層６に形成さ
れている。すなわち、配線パターンの領域内に形成され
ていた従来の同電位の複数本の回線は、配線パターン２
が形成された絶縁基板１０の上面とは異なる内層６に形
成することによって、配線パターン２を構成する多数の
回線の密度が低下する。これにより、配線パターンの自
由度の増大と配線パターン内の相互の短絡を回避するこ
とができることに帰結する。The chip carrier of the present invention is further provided with a through hole 4 penetrating the insulating substrate 10. The through hole 4 is a through hole which is electrically connected to the conductor region 3. The line 5 of the inner layer material 12 including the insulating substrate 11 layered on the lower surface of the insulating substrate 10 and the plurality of lines 5 formed on the upper surface of the insulating substrate is conducted to the through hole 4, and therefore, A line 5 is formed in the inner layer 6 and is electrically connected to the conductor area 3. That is, a plurality of conventional lines having the same potential formed in the area of the wiring pattern is the wiring pattern 2
By forming the inner layer 6 different from the upper surface of the insulating substrate 10 on which the wirings are formed, the density of a large number of lines forming the wiring pattern 2 is reduced. This results in an increase in the degree of freedom of the wiring pattern and the avoidance of mutual short circuits in the wiring pattern.
【００１０】さらにこの回線５は、内層材１２を構成す
る絶縁基板１１の下面に形成された端子７に絶縁基板１
１の下面に開口するスルホール８とスルホール８に導通
する絶縁基板１１の下面の回線９を介して導通する。こ
の端子７によって、マザーボードのプリント回路板の回
路パターンとの導通接続が可能なチップキャリアを構成
することができる。Further, the line 5 is connected to the terminal 7 formed on the lower surface of the insulating substrate 11 constituting the inner layer material 12 by the insulating substrate 1.
Conduction is performed through a through hole 8 opened on the lower surface of 1 and a line 9 on the lower surface of an insulating substrate 11 that is electrically connected to the through hole 8. The terminals 7 can form a chip carrier that can be electrically connected to the circuit pattern of the printed circuit board of the mother board.
【００１１】[0011]
【発明の効果】本発明の請求項１に係るチップキャリア
は、上記のように構成されているので、同一面内で同一
領域内に半導体チップＣに接続される配線パターンと同
電位の複数の回線を備えた従来のチップキャリアと比べ
ると、配線パターンの密度は低下し、その結果、配線パ
ターンの自由度の増大と配線パターン内の相互の短絡を
回避することができるのである。Since the chip carrier according to the first aspect of the present invention is configured as described above, a plurality of wiring patterns having the same potential as the wiring pattern connected to the semiconductor chip C in the same area in the same plane. As compared with the conventional chip carrier having a line, the density of the wiring pattern is lowered, and as a result, the degree of freedom of the wiring pattern and the mutual short circuit in the wiring pattern can be avoided.
【図１】本発明の一実施例に係るチップキャリアの平面
図である。FIG. 1 is a plan view of a chip carrier according to an embodiment of the present invention.
【図２】図１のＹ−Ｙ断面図である。FIG. 2 is a sectional view taken along line YY of FIG.
Ｃ 半導体チップ １ 搭載域 ２ 配線パターン ３ 導電体域 ４ スルホール ５ 回線 ６ 内層 ７ 端子 C Semiconductor chip 1 Mounting area 2 Wiring pattern 3 Conductor area 4 Through hole 5 Line 6 Inner layer 7 Terminal
Claims (1)
（１）、この搭載域（１）の周囲に半導体チップ（Ｃ）
に接続される配線パターン（２）、および配線パターン
（２）と搭載域（１）との間にべた張りの同電位の導電
体域（３）を上面に、この導電体域（３）に導通するス
ルホール（４）とこのスルホール（４）に導通する回線
（５）を内層（６）に、さらにスルホール（４）に導通
する端子（７）を下面に備えたことを特徴とするチップ
キャリア。1. A mounting area (1) for mounting a semiconductor chip (C), and a semiconductor chip (C) around the mounting area (1).
A wiring pattern (2) connected to the wiring pattern, and a conductor area (3) having the same electric potential, which is solid between the wiring pattern (2) and the mounting area (1), on the upper surface, and on the conductor area (3). A chip carrier comprising a through hole (4) that conducts and a line (5) that conducts to the through hole (4) in the inner layer (6) and a terminal (7) that conducts to the through hole (4) on the lower surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17887294A JPH0846081A (en) | 1994-07-29 | 1994-07-29 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17887294A JPH0846081A (en) | 1994-07-29 | 1994-07-29 | Chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0846081A true JPH0846081A (en) | 1996-02-16 |
Family
ID=16056175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17887294A Pending JPH0846081A (en) | 1994-07-29 | 1994-07-29 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0846081A (en) |
-
1994
- 1994-07-29 JP JP17887294A patent/JPH0846081A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7563645B2 (en) | Electronic package having a folded package substrate | |
| JPH06181283A (en) | Method for cross-linking programming for multichip module | |
| KR19990029348A (en) | Semiconductor devices | |
| JPH0236285Y2 (en) | ||
| US20040238951A1 (en) | Semiconductor component | |
| JP3031323B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2001502845A (en) | RF power package with double grounding | |
| JPH0846081A (en) | Chip carrier | |
| US7196409B2 (en) | Semiconductor device, semiconductor body and method of manufacturing thereof | |
| JP2000223799A (en) | Wiring board and its manufacture | |
| JP2002050715A (en) | Manufacturing method of semiconductor package | |
| JPH05102621A (en) | Conductive pattern | |
| JPS5980957A (en) | Semiconductor device | |
| JPS62259500A (en) | Circuit board | |
| JP2766361B2 (en) | Semiconductor device | |
| JPH0741161Y2 (en) | Hybrid integrated circuit | |
| TWI242399B (en) | Method of selected plating | |
| JPH0745745A (en) | Multilayered circuit board | |
| JP2743524B2 (en) | Hybrid integrated circuit device | |
| TWI221321B (en) | Method of selected plating | |
| JPH0774475A (en) | Mesh pattern structure | |
| JPH0427131A (en) | Electronic component mounting board | |
| JPH0119395Y2 (en) | ||
| JP3929302B2 (en) | Large circuit board | |
| JP2571902Y2 (en) | Electronic component mounting structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20020305 |