JPH0844454A - Data processor - Google Patents

Abstract

PURPOSE:To synchronize plural data processing parts with each other by including a clock generating means for generating at least one clock signal synchronized in phase with an original clock signal in each data processing part constituting this data processor. CONSTITUTION:At the time of receiving an original clock signal (K) 1011, a clock generator 101 can generate non-overlapped two-phase clock signals (K1, K2) with fixed duty which are in phase-synchronism with the same frequency as the signal K. Namely clocked inverter 1334 controlled by an external signal 1337 and a signal 1338 obtained by inverting the signal 1337 by an inverter circuit 1335 selects a signal 1309 when the signal 1337 is 'High' or selects the signal 1011 when the signal 1337 is 'Low' as an input of a two-phase clock generator 1305. Phases of signals K1, K2 are shifted from that of the signal 1011 by 90 deg. because the inverter 1334 is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing apparatus and system for processing information or data controlled by a clock signal, and particularly to data (or information) suitable for shortening a clock cycle for speeding up. The present invention relates to a processing device and a data processing system.

[0002]

2. Description of the Related Art A first conventional example of information processing controlled by a clock signal is shown in FIG. Reference numeral 201 is a clock oscillator that outputs the original clock signal 211, and 202 is a clock generator that receives the original clock signal 211 and generates a clock signal 212 necessary for controlling the logic devices 203 to 1206. Reference numeral 213 is an interface unit between logic devices whose timing is controlled by the clock 212.

As the clock 212 for controlling the logic device, a multi-phase clock of normally 2 to 4 phases each having a different phase is used. This clock is illustrated in FIGS. 4, 5 and 6. What is called a non-overlap two-phase clock is shown in FIG. 4, and both of the sections t ₁ and t ₂ are low level.
Is a clock having. Also, FIG. 5 shows an overlap clock with a duty of 50%, which is out of phase with each other by approximately 90 degrees. In addition, FIG.
It is a four-phase clock with a short width, which is phase-shifted by 0 degree. These clocks are selected according to the circuit format of the logic circuit forming the logic device or the design method of the logic device.

These multi-phase clock signals are generated by the clock generator 202 based on the clock 211,
It is distributed to each logical unit. The clock signal is not processed in the logic device. Moreover, the data transfer between the logic devices is performed in synchronization with the clock signal 211.

FIG. 3 shows a second conventional example of an information processing apparatus using a clock signal. 301 and 302 are clock oscillators, 311 and 312 are original clock signals, 3
Reference numerals 03 and 304 denote information processing units controlled by the clock signals 311 and 312, and reference numeral 313 denotes interface signals between the information processing units 303 and 304. This information processing device is composed of two information processing units,
Each information processing device has a separate clock oscillator 301, 3
Have 02. Processing the original clock signal,
A clock generator for generating a multi-phase clock signal as shown in FIGS. 5 and 6 is provided in each information processing unit. Data exchange between the information processing units 303 and 304 is performed asynchronously through the interface 313.

FIGS. 7 to 9 show a third conventional example of an information processing apparatus controlled by a clock signal.
This method is described in IEE, Journal of Solid State Circuit, SC 17, (1982) pp. 51-56 (IEEE Jaurn
al of Solid-State Circuits Vol. SC-17, pp
51-56).

FIG. 7 is an overall view. 701 is an oscillator for transmitting a clock signal 711, and 702 is a clock signal 71.
It is a frequency divider that divides 1 into 1 / N. Information processing unit 70
3 and the information processing unit 704 receive both the clock signal 711 and the clock signal 712. The interface between both processing units is 713.

FIG. 8 shows the internal configuration of the information processing unit 703. Reference numeral 801 denotes a PLL (Phase lock loop) circuit that delays the clock signal 711 so as to have a specific phase relationship with the clock signal 712. PLL circuit 8
01 sends out a clock signal 811 for controlling the logic device 802. On the other hand, the clock signal 712 is a clock obtained by dividing the clock 711 by N, as described above, and controls the interface circuit 803. That is, the logic device inside the information processing unit is
1 is controlled by the low speed clock 712 for communication between the information processing units which require time for signal propagation.

When two types of clock signals are used as shown in FIG. 8, the metastability (Met) is used for the data exchange between the interface circuit 803 and the logic unit 802.
A problem called astability) occurs. This will be described with reference to FIG. Consider a case where data is sent from the interface circuit 803 to the logic device 802. It is assumed that the interface uses edge-triggered flip-flops. In the interface circuit 803, when the clock signal 712 rises from the first potential level Low to the second potential level High, data is taken in from the interface 713 and the logic circuit 8
Data is sent to the signal 02 via signal 812. on the other hand,
In the logic device 802, the clock signal 811 changes from low to high.
When it rises to gh, it takes in the transmitted data. Now, when the phase relationship between the clock signal 712 and the clock signal 811 is deviated by the skew and the rising edge of the clock 712 overlaps with the rising edge of the clock 811 (the portion indicated by t _{c in} FIG. 9), the flip-flop in the logic device is The input becomes unstable when hit by the clock signal 811, and the output of the flip-flop is not fixed for a long time.
This is metastability.

In order to avoid the above-mentioned metastability, in this conventional example, as shown in FIG.
The phase relationship between the clock signal 711 and the clock signal 712 is fixed to the relationship shown in FIG.

[0011]

First, the first conventional example shown in FIG. 2 will be described. The first problem of this conventional example is that the multi-phase clock signal 212 must be distributed to the entire information processing apparatus. For this reason, the clock skew usually increases, and the duty of each clock signal also deviates from the desired value. This problem is especially caused by the increase in machine cycles due to the high speed, and the multiphase clock signal 2
It is remarkable when 12 becomes a high frequency. That is, a large part of the machine cycle is taken due to clock skew. On the other hand, an advantage of this conventional example is that since the same multiphase clock signal 212 is distributed to the entire information processing apparatus, data can be exchanged between the logic devices in a synchronous manner.

Next, the second conventional example shown in FIG. 3 will be described. This configuration is found in microprocessor systems and the like. The information processing unit corresponds to the LSI chip. The first problem of this conventional example is that each information processing unit is controlled by different clock signals, so that the interface between the information processing units must be performed asynchronously. Asynchronous interfaces require synchronization of asynchronous signals and are slower than synchronous interfaces. This becomes a problem especially when it is desired to create a high-speed system in which data is frequently exchanged between information processing units. However, the advantage of this conventional example is that the clock signal is generated inside each information processing unit, and the distribution of the clock signal is also within one information processing unit, so the clock skew can be reduced. That is the point.

The second problem of this conventional example is that a high-frequency original clock signal must be supplied from the outside of the information processing unit. Usually, in order to generate a clock signal with a correct duty, the original clock signal is divided within the information processing section. Therefore, for example, considering the case where the frequency is divided by 2 and the machine cycle is 40 MHz, 80 MH is externally applied.
The z original clock signal must be provided. This is difficult when considering an LSI chip stored in a package as the information processing unit hardware. This problem becomes even more pronounced when the machine cycle is further increased.

Next, problems with the third embodiment shown in FIGS. 7 to 9 will be described. The first problem of this conventional example is that the high-speed clock signal 711 is received from the outside of the information processing unit.
Must be supplied. The second problem is that no consideration is given to the clock duty used inside the information processing unit.

A first object of the present invention is to synchronize clock signals among a plurality of information processing units which form an information processing system.

A second object of the present invention is to supply a clock signal with a small clock skew and an accurate duty into each information processing unit.

A third object of the present invention is to avoid supplying a high speed clock signal from the inside of the information processing section.

[0018]

According to the features of the present invention,
An original clock oscillator for transmitting at least one original clock signal K as a first clock signal, and a data processing device including a plurality of data processing units connected to the original clock signal K include a plurality of data processing units. , In phase with at least one original clock signal K, and in advance
It has a clock generation unit that generates at least one second clock signal K ₁ with a determined duty, and a data processing unit whose timing is controlled by the second clock signal K ₁ and is supplied from the clock generation unit. The external clock signal and the externally applied clock signal are switched by a control signal from the outside.

[0019]

By switching the clock signal supplied from the clock generation unit and the clock signal supplied from the outside by a control signal from the outside, the duty factor can be high-speed supplied from the clock generation unit during normal operation of the data processing device. It is possible to execute the test by operating with an accurate clock signal and supplying a low-speed clock signal from the outside when testing the data processing device. Since such clock signal distribution is performed to the plurality of data processing units, the respective data processing units can be phase-synchronized.

Further, in each data processing section, the phase is synchronized with at least one original clock signal K, and
Since the clock generation unit that generates at least one second clock signal K ₁ having a predetermined duty is built in, a clock signal with a small clock skew and an accurate clock signal with a duty is provided in each data processing unit. Can be supplied.

Further, the clock generation unit synchronizes the phase of the original clock signal K with the internal clock signal K _1. The frequency of the original clock K is the internal clock signal K.
_It need not be equal to or higher than the frequency of ₁ . Therefore, in a data processing device including a plurality of data processing units in which the frequency of the internal clock signal K ₁ is increased for speeding up, it is possible to avoid supplying a high-speed clock signal from the outside of each data processing unit. .

[0022]

EXAMPLE An example of the present invention will be described below.

FIG. 10 is an overall view of an information processing apparatus which is an embodiment of the present invention. 1001 is the original clock oscillator,
Reference numeral 1011 is an original clock signal, 1002 and 1003 are information processing units, and 1012 is an interface signal for exchanging data between both information processing units.

There may be various information processing apparatuses to which the present invention is applied. In this embodiment, a computer CPU constituted by an ultra high speed VLSI will be described as an example. Further, the information processing apparatus generally comprises a plurality of information processing units, but in the present embodiment, for simplicity, it is assumed that it comprises two information processing units.

Further, the information processing section is a part of the information processing apparatus, and is integrated as a logical function and a hardware. As for hardware,
One information processing unit may be a board on which a plurality of LSI packages are mounted, one formed on a single semiconductor substrate, that is, one LSI, or a part of one LSI. Or Further, wafer scale integration can be one block on a single semiconductor substrate wafer. In the present embodiment, the information processing section is one VLSI mounted in a package.

The explanation of the embodiment of the present invention is made by the information processing unit 100.
It is sufficient to describe only the interface between the information processing unit 2 and the information processing unit 1003, and what kind of processing the two information processing units share is not directly related to the present invention. Therefore, although not described in detail, the following two cases will be illustrated.

1) The information processing unit 1002 is provided with a BPU (Basic Processing Uni) for performing instruction decoding and basic instruction processing.
t), and the information processing unit 1003 is set to F for performing floating point arithmetic.
An example of the configuration of a PU (Floating Processing Unit) is shown in FIG.
4 shows. Reference numerals 101 and 3401 are clock generators of the information processing units 1002 and 1003, respectively. 102,
Reference numeral 3406 denotes a logic device that performs a desired logical operation on an input signal and outputs an output signal. Reference numerals 3402 and 3404 denote a bus controller that constitutes an interface unit. Reference numeral 3403 denotes a register MAR (Memory Address) that holds a memory address.
Register), 3405 is a register MDR (Memory Data Register) for holding memory data, and 3407 is a memory. The signal 3410 is an address bus, 3411 is a data bus, and 3412 is a control signal. Also, 3419
Is a signal indicating the type of floating point arithmetic instruction to be processed.

In this configuration example, the logical unit of the FPU 1003 does not have the address calculation function. It functions as a so-called coprocessor. Of floating point data from memory,
The operation is explained by taking the loading to the FPU as an example. When the logic unit 102 in the BPU 1002 decodes the floating-point operation instruction, it sends the instruction type to the FPU 1003 via the signal 3419. Meanwhile, the memory address is calculated, and the signal 34
Set to MAR3403 through 18. Also, the memory read activation is signaled to the bus controller 3402 by a signal 3415.
Send through. The bus controller 3402 controls the contents of MAR to be sent to the address bus 3410 by a signal 3413 in synchronization with the clock 3420. It also sends out a control signal 3412 for controlling the memory.

On the other hand, the bus controller on the FPU side receives the control signal 3412, and the memory 3407 receives the data.
The data fetch signal 3414 is sent to the MDR3405 at the timing of outputting to the data bus 3411. Operand MD
After fetching in R, the operand read end signal 3416 is sent to the logic unit 3406. Also, the loaded operand data is sent out through a signal 3417.

2) The information processing unit 1 is a master BPU and the information processing unit 2 is a slave BPU. That is, it is a computer in which the BPU is duplicated to improve reliability. The slave BPU has the same function as the master BPU and operates in synchronization with the master BPU. Then, when the master BPU writes to the memory, the slave BPU fetches the data into its own chip and compares it with its own data. If they do not match, the master BPU is notified of them.

FIG. 29 shows the configuration described above. 2900 is a memory. 2901 to 2905 are interface signals, 2901 is an address, and 2902.
Is an address strobe, 2903 is data, 2904 is a read / write signal, and 2905 is a slave BPU that is a master B.
This signal notifies the PU of an error. In addition, 2906 is
A signal indicating that the information processing unit is a master if it is High and a slave if the information processing unit is Low.

FIG. 30 is a timing chart showing the operation of the above embodiment. Since both information processing units operate in synchronization, when the master BPU writes, the slave BPU also has the write address and the write data. The memory cycle is extended by the clock skew between chips.

Next, the oscillator 1001 will be described. The oscillator 1001 is an oscillator that sends out the original clock signal 1011. Although the original clock signal 1011 may have multiple phases, it has one phase in this embodiment. The duty of the original clock does not necessarily have to be 50%. This is the feature of the present invention.

Further, for convenience, the oscillator is replaced by the information processing unit 1.
It can also be built into. FIG. 11 shows the configuration in this case. 1100 is an information processing unit 1002
And the oscillator 1001 in the same semiconductor substrate
It is an SI chip. Reference numeral 1001 is a crystal oscillator. Since the chip 1002 itself also takes in the original clock signal 1011 output from the oscillator once outside the chip, the relationship between the original clock signal, the information processing unit 1, and the information processing unit 2 is the same as in FIG. In the configuration of FIG. 11, the chip 1
Since 100 has a built-in oscillator, there is no need to attach an oscillator externally, and there is an advantage that the hardware becomes small.

FIG. 1 shows the internal structure of the information processing unit 1002 shown in FIG. 101 is a clock generator,
111 is a multi-phase clock signal, 102 is a logic device, 10
Reference numeral 3 is an interface circuit, and 112 is a signal line between the logic device 102 and the interface circuit 103. The clock generator 101 generates a multi-phase clock 111 including at least second and third clock signals from an original clock signal 1011 from the outside, and sends it to the logic device 102 and the interface circuit 103. There are various types of multiphase clocks as shown in FIGS. 4, 5, and 6, but here, non-overlap two-phase clocks K ₁ and K ₂ shown in FIG. 4 are used.

Next, the logic device 102 of FIG. 1 will be described. The logic device 102 is controlled by the two-phase clock signals K ₁ and K ₂ . There are various logic elements constituting the logic device 102, such as an inverter, a basic gate such as a 2NAND, a flip-flop, a PLA, a ROM, a RAM, and the like. Here, taking the PLA as an example, the clock signal K ₁ and the clock signal K _{2 are used.} Is used, and what is required for the clock signals K ₁ and K ₂ when reducing the machine cycle.

FIG. 12 is a circuit diagram of the PLA controlled by the two-phase clocks K ₁ and K ₂ . In addition, FIG. 13 shows this P
6 is a timing chart showing the operation of LA.

In FIG. 12, 1201 to 1207 are wirings 1
PMOS 120 for precharging 229-1235
9-1212 and 1219-1221 are clocked inverters, 1213-1218, and 1240 and 124.
Reference numeral 1 is an inverter, and 1222-1228 are 2-input NORs. Further, X, Y and Z are inputs, and L, M and N are outputs. This PLA implements the following logic.

L = X + Y.Z M = X.Z + X.Y N = Y.Z + X.Y As shown in FIG. 13, the wiring 1229 is precharged when K ₂ is (High) and K ₁ is (High). , And X =
When it is 0, the charge is extracted by the NMOS. On the other hand, X
When = 1, it cannot be pulled out. When X = 0, K ₁ is High
Must be pulled out during the period of time, that is, during t ₃ shown in FIG. When designing the clock system, t ₃
Is taken into account during clock distribution,
Even in the worst case, it is set so that the charge withdrawal of the wiring is completed.

On the other hand, the wiring 1235 is precharged when K ₁ is high, and the charge is extracted when K ₂ is high, that is, in the period t ₄ . t ₃ Similar t ₄ also, somewhat in the clock distribution, consideration to become narrower, in the worst case, the charge withdrawal of the wiring is set to end during t ₄ period.

Since t ₃ and t ₄ are used symmetrically as described above, t ₃ = t ₄ is designed. Furthermore, as you can see, in order to shorten the machine cycle,
It is important that the fluctuations of t ₃ and t ₄ are small, that is, the duties of K ₁ and K ₂ are accurate in the logic device 102 of FIG.

Next, the clock skew will be described.
In FIG. 12, the output of the inverter 1213 changes from High to Low when the wiring 1229 is pulled out. However, if this change is not completed before the output of the inverter 1218 becomes Low, the wiring 1233 is changed. You may accidentally pull it out. Therefore, the period t in FIG.
₁ must be a certain value or more. When designing a clock
In consideration of the fact that t ₁ becomes short during clock distribution, even in the worst case, the malfunction is set so as not to occur. The same applies to t ₂ . As is clear here, in order to shorten the machine cycle, it is important that the fluctuations of t ₁ and t ₂ are small, that is, the clock skew of K ₁ and K ₂ is small.

Logic device 1 controlled by clocks K ₁ and K ₂
In summary of No. 02, in order to shorten the machine cycle, it is required to minimize the deviation of the duty of the clock signal and the clock skew.

Next, the clock generator 101 will be described. FIG. 14 shows the operation of the clock generator. The clock generator 101 receives the original clock signal K,
Two-phase clock signals K ₁ and K ₂ are output. The duty of the original clock signal K does not have to be 50%. K ₁ and K ₂ are in phase synchronization with K, and K ₁ and K ₂ are set to t ₁ = t ₂ and t ₃ = t ₄ as described above. Phase synchronization here means that the phase relationship between K and K ₁ is constant,
Furthermore, it is said that the difference between the rise of K and the rise of K ₁ is constant. In FIG. 14, the frequencies of K and K ₁ and K ₂ are equal. However, they do not necessarily have to be equal. FIG. 15 shows another operation example of the clock generator 101. Although K and K ₁ or K and K ₂ are in phase synchronization, the frequency of K ₁ and K ₂ is twice that of K. This is preferable since the clock supplied from the outside of the chip can be kept at a low frequency while the machine cycle is increased inside the chip, and there is no restriction on its duty.

The "Low" of the original clock signal K which is the first clock signal is the first potential level "Hig".
h ”is the second potential level, and the second,
Of "Low" is K _1, K ₂ as the third clock signal the third potential level, "High" is the fourth potential level.

Here, preferably, the first potential level and the third potential level are substantially equal to each other, and the second potential level and the fourth potential level are substantially equal to each other.

Next, the detailed configuration of the clock generator 101 will be described.

FIG. 16 shows 1011 (thick clock signal K).
In response to this, non-overlap two-phase clocks K ₁ and K ₂ (Fig.
4) (corresponding to No. 4) is shown.

Phase comparator 1301, low-pass filter (abbreviated as LPF hereinafter) 1302, voltage controlled oscillator (abbreviated as VOC: Voltage Control Oscillator hereinafter) 130
A closed loop loop of a 1/3 (for example, 1/2) frequency divider 1304 constitutes a PLL. That is, the phase difference and frequency difference between 1011 and 1309 are detected by 1301, and a pulse signal corresponding to the difference is output to 1306.
1302 integrates 1306 to form a DC signal (voltage value) 13
07, and 1303 oscillates at a frequency according to 1307 and outputs to 1308. 1304 outputs a clock signal with a duty of 50% to 1309 by dividing 1308 by half. Therefore, 1309 becomes a clock signal of which the phase is synchronized with that of 1011 by the PLL, the frequency becomes equal, and the frequency is divided by 1304 to obtain a duty of 50%.

The two-phase clock generator 1305 receives the clock signal 1309 with a duty of 50% and outputs the non-overlap two-phase clock signals K ₁ and K ₂ . In Figure 17
A configuration example of a gate level of 1305 is shown.

The outputs K ₁ and K ₂ of the 2-input NOR circuits 1311 and 1312 are cross-connected to one of the inputs, and the other is connected to the complementary signals of the inverted signals 1313 and 1309 of 1309 by the inverter circuit 1310.

FIG. 18 shows operation waveforms at each point in FIGS. 16 and 17. By PLL of 1301 to 1304, 1011
And 1309 are in phase with each other and have the same frequency. Therefore, the oscillation output 1308 of 1303 before being divided in half by 1304 has a frequency twice that of 1011, with a delay Δt _{0 of} 1304. 1309 is 1308 1
Since the frequency is divided by half at 304, the duty becomes 50%. 1313 is offset from 1309 by a delay Δt _{1 of} 1310. Since both K ₁ and K ₂ are 2-input NOR circuit outputs, both inputs are
High when Low. That is, _one of K ₁ and K ₂ is Hi
In the case of gh, the other always has a relationship of Low, and there is no overlap. 1309 for K ₁ to rise
Get up, from the fall of the delay t ₁ after the K ₂ of 1312, it rises after delay t ₂ of 1311. Conversely, K ₂
To rise, 1309 falls, 1313 rises after a delay Δt _{1 of} 1310, K ₁ falls after a delay t _{2 of} 1311, and rises after a delay t _{1 of} 1312. Therefore, the time when both K ₁ and K ₂ are Low is 1311,1.
The delays t ₂ and t ₁ of 312 are the same as the circuit configurations of 1311 and 1312, and t ₁ = t ₂ can be set by making the loads of K ₁ and K ₂ equal. Further, the pulse widths of K ₁ and K ₂ (time of High state) t ₃ and t ₄ satisfy the following equation.

[0053]

[Equation 1]

[0054]

[Equation 2]

From the equations (1) and (2),

[0056]

Equation ₃ t ₁ + t ₃ −Δt ₁ = t ₂ + t ₄ + Δt ₁ (Equation 3)

By the way, the delay Δt ₁ of 1310 is 131
The circuit driven by 0 is only 1311, the load of 1313 is very small, and the delays t ₂ and t _{1 of} 1311 and 1312 are small.
It can be ignored compared to. Therefore, the expression (3) becomes t ₁ + t ₃ = t ₂ + t ₄ . If t ₁ = t ₂ is set as described above, t ₃ =
At t ₄ , an ideal non-overlap two-phase clock signal can be obtained. In addition, this two-phase clock K ₁ ,
K ₂ is generated from 1309 in synchronization with 1011,
The phase relationship with 1011 is constant.

From the above, it is possible to generate a clock signal having a predetermined duty in phase synchronization with 1011 (original clock K).

In order to reduce the clock skew between the information processing units, it is preferable that the clock generators among the plurality of information processing units have the same configuration.

FIG. 19 shows another configuration example of the gate level 1305. 19, the same reference numerals as those in FIG. 17 indicate the same parts and the same functions.

From the outputs 1320 and 1321 of the 2-input NAND circuits 1314 and 1315 to the delay circuits 1316 and 131, respectively.
7, one of the inputs, 1322, 1323, is connected to intersect, and the other is connected to the complementary signals 1309, 1313, respectively. Inverter 131 to 1320 and 1321
Two-phase clocks K ₁ and K ₂ are output via 8, 1319. In this configuration, since feedback is provided from the output of the 2-input NAND circuit through the delay circuit, in order for K ₁ to rise, 1309 rises and then 1310, 1
It stands up via 315, 1317, 1314, 1318. On the other hand, the trailing edge from K ₂ falls through 1310, 1315, 1319 after the trailing edge of 1309. Therefore, if the delays of 1316 and 1317 are made larger than the others, the time when both K ₁ and K ₂ are Low is 131
6,1317 can be set.

The operation waveforms of FIGS. 20 to 19 are shown. The solid lines indicate the delay times of the delay circuits 1316 and 1317, and the broken lines indicate the large delay times. That is, since the duty of the two-phase clocks K ₁ and K ₂ can be changed by the delay time of 1316 and 1317, a non-overlap two-phase clock signal having an arbitrary duty can be obtained. Therefore, by using the circuit of this configuration, the non-overlap two-phase clock water
w) can be set only for the amount that corresponds to the clock queue generated in the logic device.

In FIG. 21, when 1011 (original clock K) is received, phase synchronization is performed at a frequency higher than K (double the frequency),
FIG. 16 shows an example of the configuration of a clock generator 101 that generates non-overlap two-phase clock signals K ₁ and K ₂ (corresponding to FIG. 15) with a determined duty. 21, the same symbols as those in FIG. 16 indicate the same parts and the same functions.

The difference between FIG. 21 and FIG. 16 is that a half-frequency divider 1304 is added to the feedback loop of the PLL so that it has two stages and the input of the two-phase clock generator 1305 is the same as that of the previous stage.
This is the output 1323 of 04.

FIG. 22 shows the operation waveform of FIG. PLL
Is fed back through two stages of the 1/2 frequency divider, so 1303
Output 1322 has a frequency four times that of 1011. Further, since the output 1323 of the preceding stage 1304 is divided by half, the duty becomes 50%, the clock signal which is twice the frequency with respect to 1011, and which is out of phase by the delay Δt ₀ of the subsequent stage 1304. Becomes In response to this 1323, the 1305 outputs the non-overlap two-phase clock signals K ₁ and K ₂ . As described above, the 1305 can generate an ideal non-overlap two-phase clock signal from a clock signal with a duty of 50%. Therefore, even in this configuration, the ideal non-overlap two-phase clocks K ₁ and K ₂ are obtained. You can Also, since the phase relationship between 1323 and 1011 is constant (difference of Δt ₀ ), K ₁ , K ₂ and 101
The phase relationship of 1 is also constant.

As described above, it is possible to generate a high-frequency clock signal having a predetermined duty by performing phase synchronization from an external low-frequency clock signal.

FIG. 23 shows 1011 (original clock signal K).
In response to this, the phase is synchronized with K at the same frequency, and the overlapped four-phase clock signals K ₄₁ , K ₄₂ , and K having a predetermined duty are received.
₄ shows an example of the configuration of a clock generator 101 that generates ₄₃ and K ₄₄ . 23, the same symbols as those in FIG. 16 indicate the same parts and the same functions.

1301, 1302, 1303, 1/4
The closed loop of the frequency divider 1324 constitutes a PLL. Therefore, 1011 and 1309 are in phase with each other and have the same frequency. Since the frequency is divided into 1/4 in the closed loop of the PLL, the 1303 oscillates at a frequency four times that of 1011,
That is, a clock having a phase shift of 1309, that is, a delay Δt ₂ of 1011 and 1324, is output to 1322. 1309
Divides 1322, so the duty is 50%.

The 4-phase clock generator 1325 shifts the phase of the clock 1309 having a duty of 50% by 90 degrees with the clock 1322 having a frequency four times that of 1309, and the overlap 4
The phase clock signals K ₄₁ , K ₄₂ , K ₄₃ and K ₄₄ are output. FIG. 24 shows a configuration example of the gate level of 1325.

The clocked inverter 1327 and the dynamic latch by the inverter 1328 are connected in series,
Every other dynamic latch inverter 132
The inverted signals 1329 and 1322 of 1322 of 6 are controlled by complementary signals to form a shift register.

FIG. 25 shows the operation waveforms of FIGS. 23 and 24. As described above, 1322 has a frequency four times that of 1011 and has a phase difference of 1011 and Δt ₂ . 1309 is 10
11 has the same frequency, the same phase, and a duty of 50%. The dynamic latch output 1330 of the first stage by 1327 and 1328 is 13 after the rise of 1309.
When 29 starts for the first time, it rises in synchronization with 13
It falls in synchronization with the first rise of 1329 after the fall of 09. Next, according to 1327 and 1328, 2
The dynamic latch output K ₄₁ of the tier rises in synchronization when 1322 starts and rises after 1330 rises, and falls in synchronization when 1322 falls and 1322 begins and rises after 1330 falls. Therefore,
The phase of K ₄₁ is delayed by one cycle from 1309 to 1322. This relationship is K ₄₁ and K ₄₂ , K ₄₂ and K ₄₃ , K ₄₃ and K ₄₄
Is the same, and K ₄₁ , K ₄₂ , K ₄₃ , and K ₄₄ are 13
The phase is delayed by one cycle of 22. 1322 is 101
Since it has a period four times as large as 1, the phase is shifted by 90 °. That is, K _{41 to} K ₄₄ are ideal overlaps 4.
It is a phase clock signal. Further, since the phase relation between 1322 and 1011 is constant, K _{41 to} K synchronized with 1322
The phase relationship between ₄₄ and 1011 is constant.

From the above, it is possible to generate a clock signal having a predetermined duty in phase synchronization with 1011 (original clock K). In this configuration, 1309, which is a clock signal having the same frequency as 1011 is used as the signal whose phase is shifted, and the phase which is shifted is 10
Since a clock signal 1322 having a frequency four times that of 11 is used, the non-overlap four-phase clock signal having the same frequency as 1011 is used, but the same applies to the frequencies having a frequency of 1309 and 1322. Further, by making the number of shift resisters of 1325 equal to the number of multiplications of the frequency of 1322 from 1309, a multi-phase clock signal of an arbitrary number of phases can be obtained.

FIG. 26 shows 1011 (original clock signal K).
In response to the above, the phase is synchronized with K at the same frequency to generate non-overlap two-phase clock signals K ₁ and K ₂ having a predetermined duty. 2 shows an example of the configuration of the clock generator 101 capable of generating 26, the same reference numerals as those in FIG. 16 denote the same parts and the same functions.

26 is different from FIG. 16 in that the input of 1305 is the external signal 1337 and the signal is the inverter circuit 1
The clocked inverter 1334 controlled by the signal 1338 inverted at 325 selects 1309 when 1337 is high and 1011 when it is low. However, since the clocked inverter is used, the phases of K ₁ and K ₂ are shifted by 90 ° from 1011.

That is, when a two-phase clock signal with a fixed duty is required by operating at high speed, the clock signal is generated from the clock 1309 with a duty of 50%. On the other hand, when performing the function diagnosis of the logic device at a low frequency as in the case of testing, the two-phase clock signal can be directly generated from 1011.

As described above, in the present configuration, when operating the inside at a low frequency, a two-phase clock is directly generated from the external clock signal, and conversely, when operating the inside at a high frequency, the duty 50 is synchronized with the external clock signal. A two-phase clock part signal can be generated from the clock of%. Therefore, there is an effect that the range of the oscillation frequency with respect to the oscillator in the clock generator can be limited. Further, it is also possible to stop the clock signal and perform a DC-like functional test when diagnosing the internal logic device. Although this configuration has been described with respect to the case of generating a non-overlap two-phase clock signal having the same frequency as the original clock signal, as shown in FIGS. 27 and 28, a non-overlap two-phase clock signal of a higher frequency than the original clock signal is generated. , The external clock signal is different from the original clock signal, and the overlapping four-phase clock signal is generated, the same is true, the original clock signal is received, the phase is synchronized with the original clock signal, and A clock generator that generates at least one clock signal, by switching between a signal generated in the clock generator and a signal input from the outside as a signal to be input to a circuit that generates a clock signal for controlling a logic device. The above-mentioned effects can be obtained.

FIG. 33 shows an example of the configuration of the phase comparator 1301 shown in FIG. 3301 is an inverter, 33
02 is a 2-input NAND, 3303 is a 4-input NAND, 33
04 is a 4-input NAND.

35 (a) and 35 (b) show the phase comparator 1
FIG. 3 is a state diagram and a state transition diagram showing the operation of 301. Thirteen
01 consists of eight states a, b, c, d, e, f, g and h. The values written in the eight circles indicating the states are the outputs “P, D” of the phase comparator 1301. Also, the value written next to the arrow indicating the state transition is the input “1011 and 1309” of the phase comparator 1301 that carries over the state transition. As can be seen from this figure, the output P of the phase comparator becomes High in the states c and g, and the output D becomes High in
In the states e and h. That is, in the phase relationship between the inputs 1011 and 1309 of 1301, 1309 is 101
If it is later than 1, 1 from the rising edge of 1011
The output P becomes High until 039 rises, and conversely 13
When 09 is ahead of 1011, the output D is High from the rise of 1309 to the rise of 1011.

FIG. 36 is a time chart showing the operation of the phase comparator 1301. As can be seen from the description of FIGS. 35 (a) and 35 (b), the output P is the input 1011 and the input 1
It goes High during the phase advance with respect to 309. On the other hand, the exit D is High during the period in which the input 1101 is delayed in phase with respect to the input 1309. The above is the phase comparator 1301
Is the operation.

FIG. 37 shows the low-pass filter 130 of FIG.
It is a figure which shows one structural example of 2. This is a circuit called a charge pump, where 1301 and 1302 are NMOS transistors, 1303 are resistors, and 1304 is electrostatic capacitance.

FIG. 38 is a timing chart showing the operation of the low pass filter shown in FIG. Input P is High
At the time of, the NMOS 1301 is turned on and the pulse current i _P flows,
The potential of the node 1305 rises. On the other hand, input D is Hi
At gh, the NMOS 1302 is turned on, the pulse current i _D flows, and the potential of the node 1305 drops. In 1307,
The potential of 1305 is smoothed by the low-pass filter composed of the resistor 1303 and the capacitor 1304. As described above, the circuit 1302 outputs the output 130
It is a circuit that changes the potential in proportion to the pulse width of the input P and the pulse width of the input D from the potential of 7.

FIG. 39 shows an example of the structure of the VCO 1303 in FIG. In FIG. 39, 3901 is a multivibrator circuit, 3902 is a level shift circuit,
3903 is a level conversion circuit.

In 3901, NPN transistors 3906 and 3907 having collectors and bases cross-connected to each other perform switching operation in which one is in an ON state and the other is in an OFF state to form an astable multivibrator. 3906
Resistors 3904 and 3905 that supply current from the power supply V _CC are connected to the collector side of 3907. The emitter side is connected to each other by a capacitor 3908 and is grounded via NMOS transistors 3909 and 3910. The gates of 3909 and 3910 are LP
The output of F1302 is the control voltage input of 1303, which is 1307.
Is a bias current source that supplies a current according to the voltage value of 1307.

The operation of 3901 is as follows. First 3
Consider the case where 906 is in the ON state and 3907 is in the OFF state. If the current value of 3909, 3910 is I,
A current 2I of both 3909 and 3910 flows through the resistor 3904, and 3908 flows from 3922 to 3933.
A current I flowing from 910 flows. Therefore, 3920 is V _CC
Then, the voltage is reduced by a voltage drop of 3904, and 3921 is pulled up to V _CC by 3905. 3922 is 39
Since 06 is in the ON state, the potential drops from VBE of 3921 by V _{BE of the} bipolar transistor (the voltage between the base and emitter required for the bipolar transistor to turn ON, which is generally about 0.8 V in the case of the Si transistor). .
Since I flows in 3908, if the capacitance of 3908 is C, the potentials of 3922 and 3923 at both ends of 3908 change with I / C with time. And the potential of 3923 is 3
When the potential becomes V _BE lower than 920, the 3907 is turned on and the current I flowing in the 3908 is 3905.
Through 3907. Then 3921 is 390
Since the voltage drop of 5 decreases, the voltage between 3921 and 3922 becomes V _BE or less, and the 3906 is turned off.

That is, in 3901, the two transistors are switched alternately. 39 in FIG.
The operation waveform of 01 is shown. 3901, 3920, 392
A differential signal of 1 can be obtained. Further, since this oscillation frequency depends on the current value I passed through 3909 and 3910, the frequency can be changed by changing I. However, since the output amplitude of the multivibrator is small, when the CMOS is used as the internal circuit, it is necessary to amplify the output of the multivibrator to the logic amplitude of the CMOS.

Reference numeral 3903 denotes the level conversion circuit, which is 3
A level shift circuit 902 connects 3901 and 3903.

In 3902, the NPN transistor 3
The series circuit of 911, 3912 and resistors 3913, 3914 is 3901 input to the bases of 3911, 3912.
The differential output of 3920 and 3921 is reduced by V _BE to 392
It is output to 5,3924.

In 3903, the output 3924 of 3902,
PMOS transistor 391 with 3925 connected to the gate
6, 3918 are NMOS transistors 3917, 391
In the serial circuit of 9, the gates of 3917 and 3919 are commonly connected to the connection point of 3916 and 3917. That is, when the current of 3916 is large, the voltage drop of 3917 is also large and the impedance of 3919 is small.
In this case, the current of 3918 is small, so 1322 is Low.
Becomes On the contrary, when the current of 3916 is small, the voltage drop of 3917 is small and the impedance of 3919 is large. In this case, the current of 3918 is large and 1322 is Hi.
gh. That is, since 3903 operates as a push-pull, the amplitude of the output 1322 becomes large.

As described above, in this configuration example, it is possible to realize a VCO having CMOS level output.

FIG. 31 shows another configuration example of the logic device 102 of FIG. Reference numerals 3100 to 3103 are four sub logical devices that form a logical device. Reference numerals 3104 to 3106 are interfaces between the sub logical devices. Each sub logic device operates in synchronization with the clock 111.

FIG. 32 is a diagram showing the configuration of the sub logical unit 3100. 3201 is a clock generator, 320
Reference numeral 2 is a logic device and 3203 is an interface circuit. 3211 is a clock for controlling the logic device 3202. That is, the sub logical device 3100 has the same configuration as the information processing unit 1002. With such a hierarchical structure, for example, 1 MHz is used as the original clock signal 1011 for synchronizing the information processing unit, and 1 is used as the clock signal 111 for synchronizing the sub logic device.
0MHz and logic unit 3202 in subclock
The clock frequency can be gradually increased by using, for example, 100 MHz as the clock signal for controlling. With this hierarchical structure, even in a large-scale information processing apparatus, it is possible to shorten the machine cycle while keeping the clock distributed to the entire information processing apparatus at a low frequency.

[0092]

According to the present invention, the clock generating means for generating at least one clock signal K ₁ phase-synchronized with the original clock signal K inside each data processing section constituting the data processing apparatus. Since it has, the data processing units can be synchronized.

Further, according to the present invention, since the clock generating means generates the clock signal K ₁ having a predetermined duty, it is possible to generate a clock signal having an accurate duty. In addition, since the generated clock need only be distributed within each data processing unit,
The clock signal K ₁ having a small clock skew and a small duty deviation can be distributed in the logic device.

Further, according to the present invention, since the low frequency source clock signal from the outside of the data processing unit and the high frequency clock signal inside the data processing unit can be synchronized, the data processing system The original clock signal from the outside of the data processing unit can be kept at a low frequency while increasing the machine cycle.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a block diagram showing another conventional example.

FIG. 4 is a timing chart illustrating a conventional example.

FIG. 5 is a timing chart illustrating a conventional example.

FIG. 6 is a timing chart illustrating a conventional example.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a block diagram showing a conventional example.

FIG. 9 is a timing chart illustrating a conventional example.

FIG. 10 is an overall block diagram of an embodiment of the present invention.

FIG. 11 is an overall block diagram of an embodiment of the present invention.

FIG. 12 is a diagram illustrating a logic device according to an embodiment of the present invention.

13 is a timing chart illustrating the operation of FIG.

FIG. 14 is a timing chart illustrating the operation of the clock generator according to the embodiment of the present invention.

FIG. 15 is a timing chart illustrating the operation of the clock generator according to the embodiment of the present invention.

FIG. 16 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 17 is a block diagram and a timing chart illustrating a clock generator according to an embodiment of the present invention.

FIG. 18 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 19 is a block diagram and a timing chart illustrating a clock generator according to an embodiment of the present invention.

FIG. 20 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 21 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 22 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 23 is a block diagram and a timing chart illustrating a clock generator according to an embodiment of the present invention.

FIG. 24 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 25 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 26 is a block diagram and a timing chart illustrating a clock generator according to an embodiment of the present invention.

FIG. 27 is a block diagram and a timing chart illustrating a clock generator according to an embodiment of the present invention.

FIG. 28 is a block diagram illustrating a clock generator according to an embodiment of the present invention and a timing chart.

FIG. 29 is a diagram illustrating an interface between information processing units according to an embodiment of the present invention.

FIG. 30 is a diagram illustrating an interface between information processing units according to an embodiment of the present invention.

FIG. 31 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 32 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 33 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 34 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 35 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 36 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 37 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 38 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 39 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 40 is a diagram showing a configuration example of an embodiment of the present invention.

[Explanation of symbols]

101 ... Clock generator, 102 ... Logic device, 103 ...
Interface circuit, 1001 ... Original clock oscillator,
1002, 1003 ... Information processing unit, 1011 ... Original clock signal, 1012 ... Interface signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideo Maejima 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Institute, Ltd. (72) Inventor Shigeya Tanaka 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Inside the Hitachi Research Laboratory (72) Inventor Tadaaki Bando 4026 Kujimachi Hitachi, Ibaraki Prefecture Hitachi, Ltd.Hitachi Research Laboratory (72) Inventor Yasuhiro Nakatsuka 4026 Kujicho Hitachi City, Ibaraki Hitachi Research Laboratory, Ltd. (72) Inventor Kazuo Kato 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.

Claims (22)

[Claims] 1. A clock generator for receiving a first clock signal having a first frequency and generating a second clock signal having a second frequency and being in phase with the first clock signal. And a clock signal selection unit that is controlled by an external control signal and selects one of the second clock signal and a third clock signal given from the outside as an input clock signal, and the input signal. And a data processing unit for processing input data based on the above. 2. The data processing device according to claim 1, wherein the third clock signal corresponds to the first clock signal supplied to the clock generation unit. 3. The data processing device according to claim 1, wherein the third clock signal is different from the first clock signal supplied to the clock generation unit. 4. The data processing device according to claim 1, wherein the data processing device is formed on one semiconductor integrated circuit chip. 5. The data processing device according to claim 1, wherein the clock generation unit and the clock signal selection unit are formed in one semiconductor integrated circuit chip. 6. The clock generation section according to claim 1, wherein: (1) a first input section to which the first clock signal is input; and a fourth input section having a predetermined frequency.
Of the first and fourth clock signals input to or output from the first input section and the second input section. An oscillator for comparing the phases and controlling the frequency of the fourth clock signal according to the compared phase difference; and (2) the frequency of the fourth clock signal for generating the second clock signal. A frequency division part that divides into a predetermined integer value,
(3) The second clock signal is fed to the second portion of the oscillator.
And a feedback path connected to the input section of the data processing apparatus. 7. The second feedback section of the clock generating section according to claim 6, further comprising another dividing section, the dividing section being supplied to the second input section of the oscillating section. A data processing device, characterized in that the frequency of the clock signal is divided. 8. The oscillator according to claim 6, wherein (1) the first clock signal and the second clock signal are input, and the phase difference between the first and second clock signals is different. And (2) a low-pass filter for generating a voltage signal determined by the signal generated by the phase comparator, and (3) control by a voltage signal generated by the low-pass filter. And a voltage controlled oscillator that generates a fifth clock signal having a frequency that is an integer multiple of the first frequency, wherein the second clock signal is synchronized with a predetermined edge of the fifth clock signal. Then, the data processing device is characterized in that the falling edge of the clock signal and the duty due to the falling edge are set to predetermined values. 9. A data processing unit for processing input data based on an input clock signal, and a first clock signal having a first frequency and receiving a first clock signal having a second frequency. A second clock signal whose phase is synchronized with that of the clock signal is generated, and is controlled by an external bypass control signal to output one of the second clock signal and the third clock signal supplied from the outside. A data processing device comprising at least a clock generation unit which selects and outputs as an input clock signal to the data processing unit. 10. The data processing device according to claim 9, wherein the third clock signal corresponds to the first clock signal supplied to the clock generation unit. 11. The data processing device according to claim 9, wherein the third clock signal is different from the first clock signal supplied to the clock generation unit. 12. The data processing device according to claim 9, wherein the data processing device is formed on one semiconductor integrated circuit chip. 13. The data processing device according to claim 9, wherein the clock generation unit is formed in one semiconductor integrated circuit chip. 14. The clock generation unit according to claim 1, wherein: (1) a first input unit to which the first clock signal is input, and a fourth input unit having a predetermined frequency.
Of the first and fourth clock signals input to or output from the first input section and the second input section. An oscillator for comparing the phases and controlling the frequency of the fourth clock signal according to the compared phase difference; and (2) the frequency of the fourth clock signal for generating the second clock signal. A frequency division part that divides into a predetermined integer value,
(3) The second clock signal is fed to the second portion of the oscillator.
And a feedback path connected to the input section of the data processing apparatus. 15. The feedback path of the clock generation unit according to claim 14, further comprising another frequency division unit, the frequency division unit being supplied to the second input unit of the oscillation unit. A data processing device, characterized in that the frequency of the clock signal is divided. 16. The oscillator according to claim 15, wherein (1) the first clock signal and the second clock signal are input, and the phase difference between the first and second clock signals is different. Controlled by a phase comparator that generates a signal that represents, a low-pass filter that generates a voltage signal that is determined by the signal that is generated by the phase comparator, and a voltage signal that is generated by the low-pass filter. And a voltage controlled oscillator that generates a fifth clock signal having a frequency that is an integer multiple of the first frequency, wherein the second clock signal is synchronized with a predetermined edge of the fifth clock signal. Then, the data processing device is characterized in that the falling edge of the clock signal and the duty due to the falling edge are set to predetermined values. 17. A clock generation unit for receiving a first clock signal having a first frequency and generating a second clock signal having a second frequency and being in phase with the first clock signal. And a plurality of data processing units that respectively receive the second clock signal from the clock generation unit and process input data, wherein the clock generation unit includes (1) the first clock signal A first input section for receiving the
Of the first and fourth clock signals input to or output from the first input section and the second input section. An oscillator for comparing the phases and controlling the frequency of the fourth clock signal according to the compared phase difference; and (2) the frequency of the fourth clock signal for generating the second clock signal. A frequency division part that divides into a predetermined integer value,
(3) A plurality of output clock signals whose rise timing and fall timing are determined by the rise timing of the input clock signal supplied from the outside are generated, and the output clock signals are supplied to the data processing unit as the second clock signals. A clock generator for distributing the clock signal, (4) a feedback path connecting the second clock signal to the second input of the oscillator, and (5) controlled by an external control signal, A clock signal selecting unit that selects one of the first clock signal and the output clock signal generated by the frequency dividing unit as a clock signal to be supplied to the clock generating unit. Data processing device. 18. The oscillator according to claim 17, wherein (1) the first clock signal and the second clock signal are input, and the phase difference between the first and second clock signals is different. And (2) a low-pass filter for generating a voltage signal determined by the signal generated by the phase comparator, and (3) control by a voltage signal generated by the low-pass filter. And a voltage controlled oscillator that generates a fifth clock signal having a frequency that is an integer multiple of the first frequency, wherein the second clock signal is synchronized with a predetermined edge of the fifth clock signal. Then, the data processing device is characterized in that the falling edge of the clock signal and the duty due to the falling edge are set to predetermined values. 19. The feedback path of the clock generation unit according to claim 17, further comprising another frequency division unit, and the frequency division unit is supplied to the second input unit of the oscillation unit. A data processing device characterized by dividing the frequency of a second clock signal. 20. The clock generator according to claim 17, 18 or 19, for generating two non-overlapping clock signals having the same frequency as the first clock signal and a predetermined duty cycle. A data processing device comprising a phase clock generator. 21. The data processing device according to claim 17, 18, 19 or 20, wherein the data processing device is formed on one semiconductor integrated circuit chip. 22. The data processing device according to claim 17, 18, 19 or 20, wherein the clock generator is formed in one semiconductor integrated circuit chip.