JPH0573167A - Semiconductor logic integrated circuit - Google Patents

Abstract

PURPOSE:To provide the synchronizing semiconductor logic integrated circuit having a clock driver operating at a high speed. CONSTITUTION:This circuit includes a master clock driver 1 having an up- counter 1U and a down counter 1D inputting the external clock CLK and outputting two frequency divider clocks CLKA and CLKB, an EXOR gate 4 inputting the two frequency divider clocks CLKU and CLKD with the phase deviated by 90 deg. from the nodal points NU and ND of clock wiring 3U and 3D through local clock drivers 5U and 5D into two input terminals and a plurarity of EXOR gate counters 2G with a D flip-flop 2 inputting the EXOR output signal SO. Thus, operating the clock wiring with the frequency half of the clock CLK frequency to be inputted from the external part, simplifying the layout design of the circuit operating at 110MHz.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic integrated circuit, and more particularly to a semiconductor logic integrated circuit having a clock driver which operates synchronously at high speed.

[0002]

2. Description of the Related Art In a conventional semiconductor logic integrated circuit such as a gate array or standard cell type LSI, a master clock driver is an I / E / I (I
EEE), 1990, CIC C (CIC
C) Logic IC chip 7 of FIG. 3 described in 16.4
As shown in the schematic plan view of FIG. 2, the master clock driver 1a receives the clock CLK from the outside, passes the clock CLK to one thick clock wiring 3, and at the same time, to the local buffer 5 via a plurality of nodes N. Then, the output signal SB of the buffer 5 is input to the input terminal of the counter 2.

Here, in order to reduce the skew from the clock driver 1a to the counter 2, as the clock wiring 3, a wiring wider than a normal signal line is used, or
Although the output terminal of the local buffer 5 is short-circuited, the clock wiring 3 has a wiring capacitance CS extending between the clock wiring 3 and the substrate of the IC chip 7.

On the other hand, on the other hand, IEE, 1989, CICC (C
ICC) 15.4, the logic IC chip 7 master clock driver 1a of FIG. 3 is connected to four local buffer groups 5a to 5d, and from there to each input terminal of the counter 2. Connected.

[0005]

The conventional semiconductor logic integrated circuit has a problem that the reliability of the wiring is deteriorated and the life thereof is short when the clock operates at a high speed of 50 MHz or more.

For example, when aluminum is used for semiconductor wiring, the US military standard (MIL-M-38510) requires that the steady-state current density be 500,000 A or less per square cm. Normally, a pulsed current flows in a semiconductor logic gate in which a signal swings between a power supply potential and a ground potential. Therefore, a margin is taken as compared with the above current density, and the limit value is set to 200,000 A per square cm, for example. If the current value flowing through the wiring is I, the clock operating frequency is f, the load capacitance is C, and the power supply voltage is V, then I = fCV.

For example, the wiring length L of the clock wiring 3 in FIG. 3 is 10 mm, the wiring film thickness is 0.5 μm, the wiring capacitance per wiring width W 1 μm is 0.2 pF / mm, and the gate load capacitance such as the clock terminal of the counter 2 is 0.1 pF per unit and V =
When the allowable load capacitance is calculated from the current limit in the case of 5 V, C = 4 pF at f = 50 MHz, and the wiring capacitance C
Since S is 2 pF, 20 gates can be connected per 1 μm width corresponding to the remaining 2 pF, but at f = 100 MHz, C = 2 pF, and the wiring capacitance CS alone exceeds the wiring current limit. There is no room to connect the gate to. Therefore, there is a problem that the design becomes difficult as the operation speed becomes higher and the size of the logic IC chip 7 becomes larger.

[0008]

SUMMARY OF THE INVENTION A semiconductor logic integrated circuit according to the present invention comprises a master clock driver for inputting an external clock and outputting a plurality of multi-divided clocks having the same phase with each other, and the multi-divided clock. On a semiconductor chip, and a plurality of signal wirings for transmitting each of the above, and another input exclusive OR gate for inputting the multi-divided clock and supplying an internal clock signal to an internal logic circuit.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a schematic plan view of a chip according to an embodiment of the present invention. The logic IC chip 6 of the present embodiment has a master clock driver 1 that inputs an external clock CLK and outputs two divided clocks CLKU and CLKD that are 90 degrees out of phase with each other, and a divided clock CLKU. , CKLD
Through the clock wirings 5U and 5D, and local clock drivers 5U and 5D connected to branch nodes NU and ND in the clock wirings, respectively.
Multiple EXOR gate counters 2 to input CLKD
G and.

FIGS. 2A and 2B are a circuit diagram and a timing chart of each signal for explaining the operation of the logic IC chip of FIG. As shown in FIG.
The clock driver 1 has an up-counter 1U of a D-type flip-flop which receives the clock CLK and is synchronized with its rising time tU, and a down-counter 1D which is synchronized with its falling time tD. Where transistor Q
U and QD are initial setting transistors for fixing the clock outputs CLKU and CLKD when the power of each flip-flop is turned on to the "L" level.

Next, the operation of the circuit will be described with reference to FIG. 2B. The clock signal CLK is supplied from the outside of the IC chip 10.
Output signal CL in synchronization with the rising edge of clock CLK
Input to the up-counter 1U in which KU changes and the down-counter 1D that operates in synchronization with the fall, and further connect the inverting output terminals QB and the data input terminals D of the counters 1U and 1D, and set the initial value setting transistor QU. , QD have their drains connected to the power supply, so that when the power is turned on, the QB terminal is set to the "L" level and the non-inverted output terminal is set to the "H" level. Then, the output clock waveforms CLKU and CLKD at the output terminals Q of the counters 1U and 1D are half the frequency of the input clock CLK and are 90 degrees in phase with each other.
The waveforms are shifted, and these two clocks CLKU, C
When LKD is passed through the EXOR gate 4 of the EXOR gate counter 2G, the gate output signal SO is the original clock CL.
It has the same waveform as K.

Therefore, the master clock frequency f is 50 M because the rising and falling edges are both 10 ns in the past.
Even in the logic IC chip whose frequency is limited to Hz, according to the present embodiment, the dichotomous frequencies CLKU and CLKD can be set to 50 MHz, so that the master clock frequency f can be doubled to 100 MHz.

In this embodiment, the master clock driver 1
The divided clocks CLKU and CLKD are output from the input terminal to the 2-input EXOR gate 4 through the two clock wirings 3U and 3D, but the divided clock is divided into 4 and the 4-input clocks are input through the four clock wirings. When input to the EXOR gate,
The master clock frequency f can be set to 200 MHz.

In this embodiment, the clock branch nodes NU and ND are connected via the local clock drivers 5U and 5D.
Although the input terminals of the EXOR gate 4 are connected to each other, if the scale of the logic IC is small, the clock drivers 5U and 5D may be omitted and the chip area can be reduced.

[0015]

As described above, according to the present invention, the input frequency is divided into multiple frequencies, and a plurality of clock wirings which are out of phase with each other are wired as a group up to the input of the EXOR gate. There is an effect that the current density can be reduced and the reliability of the wiring can be improved.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a chip according to an embodiment of the present invention.

2A and 2B are a circuit diagram and a timing chart of each signal for explaining the operation of the logic IC chip of FIG.

FIG. 3 is a schematic plan view of a chip of an example of a conventional semiconductor logic integrated circuit.

FIG. 4 is a circuit diagram of another example of a conventional semiconductor logic integrated circuit.

[Explanation of symbols]

 1 Master Clock Driver 2 Counter 2G EXOR Gate Counter 3D, 3U Clock Wiring 4 EXOR Gate 5U, 5D Local Clock Driver 6 Logic IC Chip CLK Clock CLKD, CLKU 2 Divided Clock ND, NU Branch Node QD, QU Transistor SO EXOR gate output signal tD falling time tU rising time

Claims (2)

[Claims] 1. A master clock driver which inputs an external clock and outputs a plurality of multi-divided clocks which are in phase with each other, a plurality of signal wirings which respectively transmit the multi-divided clock, and the multi-divided clock. A semiconductor logic integrated circuit having a multi-input exclusive OR gate for inputting a clock and supplying an internal clock signal to an internal logic circuit on a semiconductor chip. 2. The master clock driver has a divide-by-two up counter and a divide-by-2 down counter for inputting an external clock, and each divide-by-two clock output by each has two signal wirings. 2. The semiconductor logic integrated circuit according to claim 1, wherein the two-input exclusive OR gate is supplied via a branch node and a local clock driver.