JPH084185B2 - Method of manufacturing embedded semiconductor laser device - Google Patents

Method of manufacturing embedded semiconductor laser device

Info

Publication number
JPH084185B2
JPH084185B2 JP25219387A JP25219387A JPH084185B2 JP H084185 B2 JPH084185 B2 JP H084185B2 JP 25219387 A JP25219387 A JP 25219387A JP 25219387 A JP25219387 A JP 25219387A JP H084185 B2 JPH084185 B2 JP H084185B2
Authority
JP
Japan
Prior art keywords
layer
active layer
burying
laser device
semiconductor laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25219387A
Other languages
Japanese (ja)
Other versions
JPH0194688A (en
Inventor
秋彦 粕川
正幸 岩瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
THE FURUKAW ELECTRIC CO., LTD.
Original Assignee
THE FURUKAW ELECTRIC CO., LTD.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by THE FURUKAW ELECTRIC CO., LTD. filed Critical THE FURUKAW ELECTRIC CO., LTD.
Priority to JP25219387A priority Critical patent/JPH084185B2/en
Publication of JPH0194688A publication Critical patent/JPH0194688A/en
Publication of JPH084185B2 publication Critical patent/JPH084185B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、埋め込み型半導体レーザ素子の製造方法に
関するものである。
The present invention relates to a method for manufacturing an embedded semiconductor laser device.

〔従来の技術〕[Conventional technology]

埋め込み型半導体レーザ素子に必要なダブルヘテロ接
合の結晶成長方法としては、液相成長(LPE)法、気相
成長(VPE)法および分子線成長(MBE)法がある。これ
らの方法のなかで、有機金属気相成長(MOCVD)法は量
産性に優れ、膜厚および組成の制御性に優れているため
注目されている結晶成長法である。このMOCVD法を用い
た埋め込み型半導体レーザ素子の製造工程は、例えば第
2図(a)〜(c)に示すように、n型InP基板(1)
上にn型InPクラッド層(2)を形成し、該クラッド層
の上にノンドープGaInAsP活性層(3)を形成し、該活
性層上にP型InPクラッド層(4)層を形成する。次に
前記p型InPクラッド層上にSiO2膜(5)を形成した
後、ウエットエッチング法によりメサエッチングを行い
ストライプ領域以外を除去し、その部分に再度p型InP
電流阻止層(6)とn型InP電流阻止層(7)を形成
し、最後にp型GaInAsPコンタクト層(8)を形成す
る。この構造では、活性層(3)は活性層よりも屈折率
の小さなInP層(6)、(7)により埋め込まれている
ため、横モードの制御が可能であり、電流の閉じ込めは
InP層(6)、(7)のpn接合の逆バイアス特性を利用
して実現しており、低閾値電流が可能になっている。
Liquid-phase epitaxy (LPE), vapor-phase epitaxy (VPE), and molecular beam epitaxy (MBE) are available as double-heterojunction crystal growth methods required for embedded semiconductor laser devices. Among these methods, the metal organic chemical vapor deposition (MOCVD) method is a crystal growth method that is attracting attention because it has excellent mass productivity and excellent controllability of film thickness and composition. The manufacturing process of the buried type semiconductor laser device using this MOCVD method is, for example, as shown in FIGS. 2 (a) to 2 (c), an n-type InP substrate (1).
An n-type InP clad layer (2) is formed thereon, a non-doped GaInAsP active layer (3) is formed on the clad layer, and a P-type InP clad layer (4) layer is formed on the active layer. Next, after forming a SiO 2 film (5) on the p-type InP clad layer, mesa etching is performed by a wet etching method to remove portions other than the stripe region, and p-type InP is again formed on the portion.
A current blocking layer (6) and an n-type InP current blocking layer (7) are formed, and finally a p-type GaInAsP contact layer (8) is formed. In this structure, the active layer (3) is filled with InP layers (6) and (7) having a smaller refractive index than the active layer, so that the transverse mode can be controlled and the current can be confined.
This is realized by utilizing the reverse bias characteristic of the pn junction of the InP layers (6) and (7), and low threshold current is possible.

〔従来技術の問題点〕[Problems of conventional technology]

しかしながら、ウエットエッチング法によりメサエッ
チングを行っているため、次のような問題点がある。即
ち、活性層の巾を再現性よく制御することが困難である
こと、選択エッチングを行う際に特定の結晶面にエッチ
ングが進むため、メサ脇に凹凸を生じ活性層付近の結晶
性の悪化を招くこと、更に、SiO2膜と半導体層との密着
性が悪い場合、サイドエッチングが生じ、埋め込み層を
成長する際に問題を生ずる。
However, since the mesa etching is performed by the wet etching method, there are the following problems. That is, it is difficult to control the width of the active layer with good reproducibility, and since etching progresses to a specific crystal plane when performing selective etching, unevenness is generated on the side of the mesa and deterioration of crystallinity near the active layer occurs. In addition, when the adhesion between the SiO 2 film and the semiconductor layer is poor, side etching occurs, which causes a problem when growing the buried layer.

〔問題点を解決するための手段とその作用〕[Means to solve the problem and its action]

発明は以上のような点にかんがみてなされたもので、
その目的とするところは、狭い活性層巾を再現性よく実
現し、良好な埋め込み層を有する埋め込み型半導体レー
ザ素子を提供することにあり、その要旨は活性層を含む
ダブルヘテロ接合部をメサ形状にし、該ダブルヘテロ接
合部を前記活性層よりも屈折率の小さな半導体の埋め込
み層で埋め込む埋め込み型半導体レーザ素子の製造方法
において、前記メサ形状をドライエッチングにより形成
し、次にドライエッチングされた活性層の側面を選択的
にウエットエッチングし、次に前記ウエットエッチング
によりエッチングされた活性層を元通りに修正するよう
な物質輸送法を用いて活性層の側面に予備埋め込み層を
埋め込み、次に該活性層よりも屈折率が小さく、かつ高
抵抗な半導体の埋め込み層で埋め込むことを特徴とする
埋め込み型半導体レーザ素子の製造方法である。
The invention was made in light of the above points.
The purpose is to provide a buried semiconductor laser device having a narrow active layer width with good reproducibility and a good buried layer, and the gist thereof is to form a double heterojunction portion including the active layer in a mesa shape. In the method for manufacturing an embedded semiconductor laser device in which the double heterojunction portion is embedded with an embedded layer of a semiconductor having a smaller refractive index than the active layer, the mesa shape is formed by dry etching, and then the dry-etched active layer is formed. A side surface of the layer is selectively wet-etched, and then a preliminary burying layer is embedded on the side surface of the active layer by using a mass transport method such that the active layer etched by the wet etching is restored to its original state. An embedded semiconductor characterized by being embedded in a semiconductor embedded layer having a refractive index smaller than that of the active layer and a high resistance. It is a manufacturing method of over laser device.

ドライエッチングでは、活性層の巾を精度よく制御す
ることが可能である。ウエットエッチングでは、エッチ
ングが等方的であれば、深さと同じ寸法だけレジスト膜
の下側にもエッチングが進むサイドエッチングが生じ、
また薬品による材料や結晶面の選択性も高い、しかしな
がら、ドライエッチングを用いると、選択性がなくな
り、InPおよびGaInAsPについて等速エッチングが可能と
なり、ヘテロ界面において段差のない垂直側壁が得られ
る。なお、ドライエッチングの問題点の一つであるイオ
ン照射損傷の影響を除くために、ウエットエッチングに
よりプラズマにさらされた活性層を選択的にエッチング
する。
With dry etching, the width of the active layer can be accurately controlled. In wet etching, if the etching is isotropic, side etching occurs under the resist film by the same dimension as the depth.
In addition, the selectivity of materials and crystal planes due to chemicals is also high. However, when dry etching is used, the selectivity is lost, and InP and GaInAsP can be etched at a constant rate, and vertical sidewalls without steps at the hetero interface can be obtained. In order to eliminate the influence of ion irradiation damage, which is one of the problems of dry etching, the active layer exposed to plasma is selectively etched by wet etching.

次に、埋め込み層により電流阻止層を形成しなければ
ない。電流阻止層としてはpn接合の逆バイアスを利用す
ることができるが、この方法は高周波特性に劣るため、
本発明では半導体の高抵抗層で埋め込み層を形成する。
半導体の高抵抗層は不純物を含んでおり、この不純物が
活性層に悪影響を及ぼすのを避けるため、活性層の側面
を物質輸送法により予め被覆しておく必要がある。
Next, the current blocking layer must be formed by the buried layer. A reverse bias of a pn junction can be used as the current blocking layer, but this method is inferior in high frequency characteristics, so
In the present invention, the buried layer is formed of a high resistance layer of semiconductor.
The high resistance layer of the semiconductor contains impurities, and it is necessary to cover the side surfaces of the active layer in advance by a mass transport method in order to prevent the impurities from adversely affecting the active layer.

〔実施例〕〔Example〕

以下図面に示した実施例に基づいて本発明を説明す
る。
The present invention will be described below based on embodiments shown in the drawings.

第1図(a)〜(e)は本発明にかかる製造方法によ
る埋め込み型半導体レーザ素子の要部断面を工程順に示
した図である。
FIGS. 1 (a) to 1 (e) are sectional views showing, in order of steps, a main part of an embedded semiconductor laser device manufactured by the manufacturing method according to the present invention.

次に、この製造方法を図面に従い工程順に説明する
と、 (1)n型InP基板(11)上に、第1図のMOCVD法による
結晶成長により、n型InPクラッド層(12)、波長1.3μ
mの発光に相当する組成のGaInAsP活性層(13)、p型I
nPクラッド層(14)、p型GaInAsPコンタクト層(15)
を連続成長させる。(第1図(a)) (2)ホトリソグラフィおよびCF4ガスによる反応性イ
オンエッチング(RIE)により、巾1.5μm程度の2層レ
ジスト(ホトレジスト(17))、SiO2膜(16)パターン
を形成する。(第1図(b) (3)Cl2ガスを用いた反応性イオンビームエッチング
(RIBE)により、2層レジストマスクとして、n型InP
クラッド層(12)までエッチングする。このとき、ウェ
ハをイオンビームに対して21゜の傾斜角を持つように設
置し、ウェハを回転させながらエッチングするとによ
り、略垂直なエッチング面を得ることができる。(第1
図(c)) (4)エッチングを終えたウェハをアッシングすること
により、最上層のホトレジスト(17)を剥離する。
Next, this manufacturing method will be described in order of steps with reference to the drawings. (1) An n-type InP clad layer (12) and a wavelength of 1.3 μm are formed on the n-type InP substrate (11) by the crystal growth by the MOCVD method of FIG.
GaInAsP active layer (13), p-type I with a composition corresponding to the emission of m
nP clad layer (14), p-type GaInAsP contact layer (15)
Grow continuously. (Fig. 1 (a)) (2) A two-layer resist (photoresist (17)) and a SiO 2 film (16) pattern with a width of about 1.5 μm were formed by photolithography and reactive ion etching (RIE) with CF 4 gas. Form. (Fig. 1 (b) (3) n-type InP was used as a two-layer resist mask by reactive ion beam etching (RIBE) using Cl 2 gas.
Etch to the cladding layer (12). At this time, the wafer is installed so as to have an inclination angle of 21 ° with respect to the ion beam, and etching is performed while rotating the wafer, whereby a substantially vertical etching surface can be obtained. (First
(C)) (4) The uppermost photoresist (17) is removed by ashing the wafer after etching.

(5)3H2SO4:H2O:H2O2の混合液を用い、活性層(13)
を選択的にエッチングする。(第1図(d)) (6)ウェハを洗浄した後、PH3ガスを用いて物質輸送
法により、前記選択エッチングした活性層の両側面を元
通りに修正するようその両側面にInP層(18)の予備埋
め込み層を埋め込む。次いで、SiO2膜(16)を選択成長
用のマスクとして減圧MOCVD法によりFeを添加した高抵
抗InP層(19)を成長させる。このとき、SiO2膜(16)
のメサストライプ上には結晶が成長しない。(第1図
(e)) (7)SiO2膜を剥離した後、電極を形成し、チップに切
断する。なお、本発明による埋め込み型半導体レーザ素
子の製造方法は上記実施例に限定されることなく、RIBE
法のかわりにRIEI法によりメサエッチングを行ってもよ
く、エッチングガスとしてCl2ガスのかわりに、Cl2ガス
にAr等のガスを添加したものを用いてもよく、またエッ
チングマスクとしてホトレジスト/SiO2の組み合せのか
わりにTiO2/SiO2の組み合せを用いてもよい。活性層の
発光波長についても1.3μmに限定することなく、1.1〜
1.6μmの所望の発光波長を選択することができる。
(5) Using a mixed solution of 3H 2 SO 4 : H 2 O: H 2 O 2 , the active layer (13)
Are selectively etched. (FIG. 1 (d)) (6) After cleaning the wafer, the InP layer is formed on both side surfaces of the selectively etched active layer so as to restore them by the mass transport method using PH 3 gas. (18) Embed the preliminary embedding layer. Then, using the SiO 2 film (16) as a mask for selective growth, a high-resistance InP layer (19) containing Fe is grown by the low pressure MOCVD method. At this time, SiO 2 film (16)
No crystals grow on the mesa stripes. (FIG. 1 (e)) (7) After peeling off the SiO 2 film, electrodes are formed and cut into chips. The manufacturing method of the embedded semiconductor laser device according to the present invention is not limited to the above-mentioned embodiment, and the RIBE
May be carried out mesa etching by RIEI method instead of the law, instead of the Cl 2 gas as the etching gas, it may be used after addition of a gas such as Ar Cl 2 gas and the photoresist / SiO as an etch mask Instead of the combination of 2, the combination of TiO 2 / SiO 2 may be used. The emission wavelength of the active layer is not limited to 1.3 μm,
The desired emission wavelength of 1.6 μm can be selected.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明によれば、メサ形状をドラ
イエッチングにより形成しているため、活性層巾を精度
よく制御することができ、また、埋め込み層が高抵抗な
半導体層であるため良好な高周波特性が得られるという
優れた効果がある。
As described above, according to the present invention, since the mesa shape is formed by dry etching, the width of the active layer can be accurately controlled, and the buried layer is a semiconductor layer having high resistance, which is favorable. There is an excellent effect that high frequency characteristics can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(e)は本発明にかかる製造法による埋
め込み型半導体レーザ素子の要部断面を工程順に示した
図であり、第2図(a)〜(c)は従来の製造法による
埋め込み型半導体レーザ素子の要部断面を工程順に示し
た図である。 1,11……n型InP基板、2,12……n型InPクラッド層、3,
13……GaInAsP活性層、4,14……p型InPクラッド層、5,
16……SiO2膜、6……p型InP電流阻止層、7……n型I
nP電流阻止層、8,15……p型GaInAsPコンタクト層、17
……ホトレジスト、18……InP層の予備埋め込み層、19
……高抵抗InP層。
1 (a) to 1 (e) are cross-sectional views showing the main part of an embedded semiconductor laser device manufactured by the manufacturing method according to the present invention in the order of steps, and FIGS. 2 (a) to 2 (c) are conventional manufacturing processes. FIG. 6 is a diagram showing a cross-section of a main part of an embedded semiconductor laser device by the method in the order of steps. 1,11 …… n-type InP substrate, 2,12 …… n-type InP clad layer, 3,
13 …… GaInAsP active layer, 4,14 …… p-type InP clad layer, 5,
16 …… SiO 2 film, 6 …… p type InP current blocking layer, 7 …… n type I
nP current blocking layer, 8,15 ... p-type GaInAsP contact layer, 17
...... Photoresist, 18 …… InP pre-filling layer, 19
...... High resistance InP layer.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭54−154984(JP,A) 特開 昭58−143596(JP,A) 特開 昭60−163489(JP,A) 特開 昭61−288481(JP,A) 特開 昭61−147592(JP,A) 特開 昭62−84581(JP,A) 特開 昭64−66988(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-54-154984 (JP, A) JP-A-58-143596 (JP, A) JP-A-60-163489 (JP, A) JP-A-61- 288481 (JP, A) JP 61-147592 (JP, A) JP 62-84581 (JP, A) JP 64-66988 (JP, A)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】活性層を含むダブルヘテロ接合部をメサ形
状にし、該ダブルヘテロ接合部を前記活性層よりも屈折
率の小さな半導体の埋め込み層で埋め込む埋め込み型半
導体レーザ素子の製造方法において、前記メサ形状をド
ライエッチングにより形成し、次にドライエッチングさ
れた活性層の側面を選択的にウエットエッチングし、次
に前記ウエットエッチングによりエッチングされた活性
層を元通りに修正するよう物質輸送法を用いて活性層の
側面に予備埋め込み層を埋め込み、次に該活性層よりも
屈折率が小さく、かつ高抵抗な半導体の埋め込み層で埋
め込むことを特徴とする埋め込み型半導体レーザ素子の
製造方法。
1. A method of manufacturing an embedded semiconductor laser device, wherein a double heterojunction portion including an active layer is formed into a mesa shape, and the double heterojunction portion is embedded with a semiconductor burying layer having a refractive index smaller than that of the active layer. The mesa shape is formed by dry etching, then the side surfaces of the dry-etched active layer are selectively wet-etched, and then the mass-transport method is used to restore the active layer etched by the wet-etching to the original state. A method of manufacturing an embedded semiconductor laser device, comprising: burying a preliminary burying layer on a side surface of the active layer, and then burying a semiconductor burying layer having a refractive index smaller than that of the active layer and a high resistance.
【請求項2】前記物質輸送法による埋め込みおよび高抵
抗な半導体の埋め込み層による埋め込みを有機金属気相
成長法により行うことを特徴とする特許請求の範囲第1
項記載の埋め込み型半導体レーザ素子の製造方法。
2. The burying by the mass transport method and the burying by a burying layer of a semiconductor having a high resistance are performed by a metal organic chemical vapor deposition method.
6. A method for manufacturing an embedded semiconductor laser device according to the item.
JP25219387A 1987-10-06 1987-10-06 Method of manufacturing embedded semiconductor laser device Expired - Lifetime JPH084185B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25219387A JPH084185B2 (en) 1987-10-06 1987-10-06 Method of manufacturing embedded semiconductor laser device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25219387A JPH084185B2 (en) 1987-10-06 1987-10-06 Method of manufacturing embedded semiconductor laser device

Publications (2)

Publication Number Publication Date
JPH0194688A JPH0194688A (en) 1989-04-13
JPH084185B2 true JPH084185B2 (en) 1996-01-17

Family

ID=17233795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25219387A Expired - Lifetime JPH084185B2 (en) 1987-10-06 1987-10-06 Method of manufacturing embedded semiconductor laser device

Country Status (1)

Country Link
JP (1) JPH084185B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968845A (en) * 1996-02-13 1999-10-19 Matsushita Electric Industrial Co., Ltd. Method for etching a compound semiconductor, a semi-conductor laser device and method for producing the same

Also Published As

Publication number Publication date
JPH0194688A (en) 1989-04-13

Similar Documents

Publication Publication Date Title
JPH06291416A (en) Semiconductor laser and manufacture thereof
JP2827326B2 (en) Manufacturing method of semiconductor laser
US4599787A (en) Method of manufacturing a light emitting semiconductor device
JP2525788B2 (en) Method for manufacturing semiconductor laser device
JPH084185B2 (en) Method of manufacturing embedded semiconductor laser device
JPH0194690A (en) Manufacture of buried type semiconductor laser device
JP3047049B2 (en) Method of manufacturing buried semiconductor laser
JP2669142B2 (en) Method for manufacturing window structure semiconductor laser
JP2911270B2 (en) Visible light laser diode and method of manufacturing the same
JPH0824208B2 (en) Manufacturing method of semiconductor laser
JP2528877B2 (en) Semiconductor laser
JPH05275797A (en) Manufacture of semiconductor laser
JPH07131110A (en) Manufacture of semiconductor laser device
JPH05226774A (en) Semiconductor laser element and its production
JP3132054B2 (en) Method of manufacturing buried semiconductor laser
JPH11354880A (en) Semiconductor laser element and its manufacturing method
KR100261243B1 (en) Laser diode and its manufacturing method
JP2547459B2 (en) Semiconductor laser device and manufacturing method thereof
JPH0710019B2 (en) Embedded structure semiconductor laser manufacturing method
JP2860207B2 (en) Semiconductor laser device and method of manufacturing the same
JP2525776B2 (en) Method for manufacturing semiconductor device
JPH06350188A (en) Semiconductor laser element
JPH09148670A (en) Semiconductor laser and its manufacture
JPH0680861B2 (en) Method for manufacturing semiconductor light emitting device
JPH0715090A (en) Fabrication of semiconductor optical device having embedded structure

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080117

Year of fee payment: 12