JPH0837652A - Identification signal demodulator - Google Patents

Abstract

PURPOSE:To promptly detect identification signals since cumulative data up to a field are present even when no more identification signals are present in the middle of broadcasting by performing the intra-field accumulation of confirmation signals after detecting and confirming the NRZ signals of television identification signals. CONSTITUTION:Digital video signals sampled by 4fsc are inputted from an input terminal 1, fsc and 4/7fsc components are removed by a low-pass filter 2, the 4/7fsc components are extracted by a band-pass filter 3 and control signals and gate signals are generated by a control signal generation circuit 4. When respective identification control signals B1 to B5 are inputted from the input terminal of an intra-bit accumulation means 5, a DFF is reset by CLR signals, accumulation for each clock is performed by the DFF latched by the clock signals of 4fsc and an adder, cumulative output 102 is outputted from an output terminal and output is performed from a synthesis circuit 12 and inter-field accumulation circuits 24 and 25 as signals for which the NRZ signals are confirmed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an identification signal demodulation device, and more particularly to an identification signal demodulation device for demodulating an identification control signal in television broadcasting such as second generation EDTV.

[0002]

2. Description of the Related Art Conventionally, in order to identify a second generation EDTV broadcast, it has been proposed to insert an identification control signal into the 22nd and 285th lines of a video signal. As shown in FIG. 5, the identification control signal is composed of 27 bits, and one bit period is 7 cycles (about 1.95 μs) of the color width carrier wave fsc of 3.58 MHz. The first bit (B1) to the fifth bit (B5) are NRZ waveforms, and B6 to B1
7 is a signal phase-modulated by fsc, and B25 to B27 are 4/7 fsc sine waves for confirmation. In consideration of application to VTR and the like, the reference signal indicating the position of the video signal and the identification signal indicating the letterbox are in the NRZ format, and the other identification signals are modulated by fsc to reduce the influence of the ghost on the confirmation signal. There is. NRZ (Non Return t
o Zero) waveform is a signal waveform in which a bit signal of 0 or 1 is represented by a high level or a low level for one bit period.

In normal broadcasting, the 22nd line, the 285th line
Since the line is a video signal, it is necessary to detect whether or not the identification control signal is inserted by the identification signal detection device.

As shown in FIG. 6, the conventional identification signal detecting apparatus has an input terminal 1 for inputting a digital video signal 100 sampled at a frequency 4fsc which is four times as wide as a color width carrier, and fsc and a digital video signal 100fsc. 4/7
The low-pass filter 2 for removing the fsc component, the band-pass filter 3 for extracting the 4/7 fsc component from the digital video signal 100, the control signal generating circuit 4 for generating the control signal and the gate signal for controlling each part of the device, and the low-pass filter 2 B1 to the signal 101 that passed through
An intra-bit accumulating means 5 for accumulating every one clock when B5 to B5 are inputted, and an NRZ decoding circuit 6 for discriminating whether the signal 102 accumulated for each bit is High (1) or Low (0). , An NRZ confirmation circuit 7 for determining whether or not the NRZ signal 103 is in a predetermined state,
B24 to B2 of the signal 101 that has passed through the low-pass filter
7. The in-line accumulating circuit 8 which accumulates the confirmation signals of No. 7 to calculate and output the low frequency component, and High when the difference between the low frequency component of the input signal 104 and the pedestal level is small.
(1) output low frequency discrimination circuit 9, 7-clock accumulating circuit 10 for accumulating 4/7 fsc component 105 extracted by band-pass filter 3 every 7 clocks, and accumulating result 106 for detecting and confirming signal 4 / 7fsc component detection circuit 11 that outputs High (1) when a sine wave of 4 / 7fsc component exists above a predetermined level, NRZ confirmation circuit 7, low frequency band discrimination circuit 9 and 4 / 7fsc component When all the outputs from the detection circuit 11 are High (1), it is determined that the identification signal is confirmed, and the output terminal 13 outputs High.
And a synthesizing circuit 12 for outputting (1).

The in-bit accumulating means 5 and the in-line accumulating circuit 8 are, as shown in FIG. 7A, an input terminal 14, an adder 15, two D flip-flops 16 and 17, and an output terminal 18. It consists of and.

The 7-clock accumulating circuit 10 shown in FIG.
As shown in (b), the input terminal 19, the adder 20, and
It is composed of eight D flip-flops 21a to 21g, 22 and an output terminal 23.

Next, the operation of this conventional example will be described.

The digital video signal 100 sampled at 4 fsc is input from the input terminal 1, the low-pass filter 2 removes the fsc and 4/7 fsc components from the digital video signal 100, and the band-pass filter 3 removes the digital video signal 100-4. The / 7fsc component is extracted, and the control signal generation circuit 4 generates a control signal and a gate signal for controlling each part of the device. When each of the identification control signals B1 to B5 is input from the input terminal 14 of the intra-bit accumulating unit 5, CL
The R signal resets the D flip-flop 16,
The D flip-flop 17 latched by the adder 15 and the clock signal of 4 fsc accumulates every clock. When each bit is completed, D by CLK signal
Latched by the flip-flop 17 and accumulated output 10
2 is output from the output terminal 18. The signal 102 accumulated for each bit is High by the NRZ decoding circuit 6.
It is determined whether it is (1) or Low (0).

Then, the NRZ confirmation circuit 7 determines whether or not the NRZ signal 103 is in a predetermined state. For example, B1 is 1, B2 is 0, B4 is B3 and B5.
If it is even parity, the High (1) signal is output to the synthesizing circuit 12 as the NRZ signal is confirmed.

Further, the in-line accumulating circuit 8 causes B24-
B24 to strengthen against confirmation signal or noise of B27
The confirmation signals of the previous fsc modulation portion and B24 to B27 are accumulated, and the low frequency component thereof is calculated. When the difference between the low frequency component input by the low frequency component discrimination circuit 9 and the pedestal level is small, a High (1) signal is output. On the other hand, 4 / 7fs extracted by the bandpass filter 3
The c component 105 is supplied to the 7-clock accumulator circuit 10
When the confirmation signal portion of 25 is supplied, the seven D flip-flops 21a to 21g are reset by the CLR signal, and the adder 20 and the D flip-flop are input while the signals are input from the input terminal 19 to B25 to B27. 21a-
The input signal is accumulated every 7 clocks using 21 g.
When accumulated up to B27, the accumulated result 106 is latched by the D flip-flop 22 with the CLK signal and output from the output terminal 23. The accumulated signal is detected by the 4/7 fsc component detection circuit 11, and when the sine wave of the 4/7 fsc component is present at a predetermined level or higher, High (1) is output to the synthesis circuit 12. NRZ by combining circuit 12
When the outputs from the confirmation circuit 7, the low frequency band discrimination circuit 9 and the 4/7 fsc component detection circuit 11 are all High (1),
Assuming that the identification signal has been confirmed, High is output from the output terminal 13.
(1) A signal is output.

[0011]

In the conventional identification signal demodulation device, it is necessary to determine whether or not the identification signal is inserted in the 22nd line and the 285th line of the video signal, and the NRZ of B1 to B5. Since the signal and the signal of the 4/7 fsc component of the confirmation signal of B25 to B27 have a large amplitude to some extent, it is difficult to detect due to noise, that is, it is difficult to determine that the identification signal is not inserted even though the identification signal is inserted. , In order to confirm that the low-frequency component is smaller than the set value that is different from the pedestal level, it is often erroneously detected when the set value is increased, that is, it is determined that the identification signal is inserted even though it is not inserted. Therefore, there is no choice but to reduce the set value, and when the set value becomes small, it becomes vulnerable to noise, and many detection omissions occur when the S / N of the received signal is poor. Ukoto has been confirmed by experiment.

[0012] Further, when the difference between the low frequency component and the pedestal level is large without the identification signal being inserted, and when the difference between the low frequency component and the pedestal level is small because the identification signal is inserted, there is an intermediate point. Considering the case of switching,
If low-frequency components are simply accumulated for each field in order to increase the noise level, the case where the level difference is large is also accumulated, so in order to keep the set value small, signals with large level differences are As long as there is an influence, it will be missed in detection and must be accumulated until the influence disappears, the detection time for switching is delayed, and erroneous detection is likely to occur.

The present invention has been made in order to solve the above problems. Even if the S / N of the received signal is poor, the identification signal can be detected without making an erroneous determination by detecting the confirmation signal. It is an object of the present invention to provide an identification signal demodulation device that does not cause erroneous detection even when it is inserted and when it is not inserted.

[0014]

According to the present invention, the above-mentioned object is to confirm the decoding means for decoding the NRZ signal of the television identification control signal and to confirm whether the NRZ signal has a prescribed value. Confirming means to perform and NRZ by confirming means
The identification signal according to claim 1, further comprising accumulating means for accumulating the identification control signal for each field only when the signal is confirmed as specified, and detecting means for determining the confirmation signal and obtaining reference phase information from the accumulation result. Achieved by demodulator.

According to the present invention, the above-mentioned object holds the identification control signal confirmation means for confirming the confirmation signal of the accumulated identification control signal, the accumulation function for accumulating the identification control signal for each field, and the accumulation result. It has a holding function and holds the accumulated result when the confirmation signal is confirmed by the identification control signal confirmation means, and when it is not confirmed, the accumulated result in which the confirmation signal before that is confirmed is used. 3. An inter-field accumulating means for accumulating with a field.
This is achieved by the identification signal demodulating device described in 1.

[0016]

In the identification signal demodulating device according to the first aspect, the NRZ of the television identification control signal is performed by the decoding means.
The signal is decoded, and the confirmation means confirms whether or not the NRZ signal has a prescribed value, and the confirmation means outputs N.
Only when the RZ signal is confirmed as specified, the accumulating means accumulates the identification control signal for each field, and the detecting means detects the confirmation signal and the reference phase information from the accumulation result. As a result, even if the S / N of the received signal is poor, it is possible to prevent erroneous determination by detecting the confirmation signal, and erroneous detection is performed even when the identification signal is inserted and not inserted. There is nothing to do.

In the identification signal demodulating device according to the second aspect of the invention, the identification control signal confirmation means confirms the confirmation signal of the accumulated identification control signal, and the inter-field accumulation means confirms the confirmation signal by the identification control signal confirmation means. If confirmed, the cumulative result is retained, if not confirmed,
Accumulation with the next field is performed using the accumulation result in which the confirmation signal before that is confirmed. As a result, even if the S / N of the received signal is poor, it is possible to prevent erroneous determination by detecting the confirmation signal, and erroneous detection is performed even when the identification signal is inserted and not inserted. There is nothing to do.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of an identification signal demodulating device of the present invention will be described below with reference to FIG. The same components as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted.

In the identification signal demodulation device of this embodiment, N arranged between the in-line accumulating circuit 8 and the low frequency band discriminating circuit 9.
An inter-field accumulating circuit 24 as accumulating means for accumulating the identification control signal for each field only when the NRZ signal is confirmed by the RZ confirming circuit 7 according to the regulation, a 7-clock accumulating circuit 10 and a 4/7 fsc component detecting circuit 11. Inter-field accumulating circuit 25 as accumulating means arranged between
Is provided.

The inter-field accumulator circuits 24 and 25, as shown in FIG.
The output signal of the multiplier 27 for multiplying by / 4, the adder 28, the D flip-flop 29, and the D flip-flop 29 is set to 3
It is composed of a multiplier 30 for multiplying / 4 and an output terminal 18.

Next, the operation of this embodiment will be described.

The digital video signal 100 sampled at 4 fsc is input from the input terminal 1, the fsc and 4/7 fsc components are removed by the low pass filter 2, the 4/7 fsc component is extracted by the band pass filter 3, and the control signal is generated. The circuit 4 generates a control signal and a gate signal for controlling each part of the device.
When each of the identification control signals B1 to B5 is input from the input terminal 14 of the intra-bit accumulating means 5, the D flip-flop 16 is reset by the CLR signal and is latched by the adder 15 and the clock signal of 4fsc. The flip-flop 17 accumulates every clock.
When each bit is completed, it is latched by the D flip-flop 17 with the CLK signal, and the cumulative output 102 is output from the output terminal 18. The NRZ decoding circuit 6 determines whether the signal 102 accumulated for each bit is High (1) or Low (0).

Then, the NRZ confirmation circuit 7 determines whether or not the NRZ signal 103 is in a predetermined state. For example, B1 is 1, B2 is 0, B4 is B3 and B5.
If the parity is even, the High (1) signal is output to the synthesizing circuit 12 and the inter-field accumulating circuits 24 and 25 because the NRZ signal is confirmed.

The low frequency components calculated by the in-line accumulating circuit 8 are input to the inter-field accumulating circuit 24.
When the power is turned on or the channel is switched, the CLR signal is input and the D flip-flop 29 is reset. The signal input from the input terminal 26 is 1/4 by the multiplier 27.
The multiplied output is multiplied by the adder 28, and the accumulated output up to the previous field, which is the output of the D flip-flop 29, is multiplied by 3/4 by the multiplier 30 and added. The addition result is input to the D flip-flop 29, but is not accumulated if the NRZ signal is not confirmed. Then, the latch output is output from the output terminal 31. The noise components are reduced by accumulating the low frequency components in the inter-field accumulation circuit 24, the difference between the low frequency components and the pedestal level input by the reduction amount determination circuit 9 is determined, and the difference between the low frequency components and the pedestal level is determined. Is small, the High (1) signal is output.

On the other hand, the 4/7 fsc component 105 extracted by the bandpass filter 3 is the 7-clock accumulator circuit 10.
And the confirmation signal portion of B25 is supplied to the seven D flip-flops 21a to 2a by the CLR signal.
1g is reset and B25 to B27 from the input terminal 19
While the signal is being input to the input terminal, the input signal is accumulated every 7 clocks using the adder 20 and the D flip-flops 21a to 21g. Accumulation result 1 when accumulated up to B27
06 is latched by the D flip-flop 22 by the CLK signal and output from the output terminal 23. 4 of confirmation signals accumulated every 7 clocks by the 7-clock accumulation circuit 10.
The / 7fsc component is NR by the inter-field accumulation circuit 25.
Inter-field accumulation is performed when the Z signal is High (1), and inter-field accumulation is not performed when the Z signal is Low (0), and the accumulated output is supplied to the 4/7 fsc component detection circuit 11 and 4/7 fsc. When the sine wave of the 4/7 fsc component is detected by the component detection circuit 11 and has a predetermined level or more, High (1) is output to the synthesis circuit 12.
When all the outputs from the NRZ confirmation circuit 7, the low frequency band discrimination circuit 9 and the 4/7 fsc component detection circuit 11 are High (1) by the synthesizing circuit 12, it is determined that the identification signal is confirmed to be High (1) from the output terminal 13. ) A signal is output.

Further, the inter-field accumulator circuits 24, 25
2B, the input terminal 32, the four D flip-flops 33, 34, 35 and 36, the three adders 37, 38 and 39, and the output terminal 40 are configured as shown in FIG. Good.

In this case, when the power is turned on or the channel is switched, the CLR signal is input and the D flip-flops 33 to 36 are reset. The signal input from the input terminal 32 is supplied to the D flip-flop 33 and the three adders 37, 38 and 39. NRZ signal is Hi
In the case of gh (1), the CLK signal is input every field. That is, the D flip-flop 34 outputs the accumulation result of 2 fields, the D flip-flop 35 outputs the accumulation result of 3 fields, and the D flip-flop 36 outputs the accumulation result of 4 fields. In addition, the NRZ signal is Low
In the case of (0), the CLK signal is not input, so NR
The Z signal is not confirmed and no field accumulation will occur.

Next, a second embodiment of the identification signal demodulating device of the present invention will be described with reference to FIG. The same components as those in FIGS. 1 and 6 are designated by the same reference numerals and the description thereof will be omitted. The identification signal demodulating device according to the present embodiment is characterized in that the output 107 of the low frequency band discriminating circuit 9 is fed back to the inter-field accumulating circuit 24 and the 4/7 fsc component detecting circuit 1 is provided.
The output 108 of 1 is fed back to the inter-field accumulator circuit 25.

As shown in FIG. 4A, the inter-field accumulator circuits 24 and 25 input the input terminal 41 and the input signal to 1
/ 4 times the multiplier 42, the adder 43, the D flip-flop 44, and the output signal of the D flip-flop 44 by 3
It is composed of a multiplier 45 for multiplying by / 4 and an output terminal 46.

Next, the operation of this embodiment will be described.

The digital video signal 100 sampled at 4 fsc is input from the input terminal 1, the low-pass filter 2 removes the fsc and 4/7 fsc components, and the band-pass filter 3 extracts the 4/7 fsc component to generate a control signal. The circuit 4 generates a control signal and a gate signal for controlling each part of the device.
When each of the identification control signals B1 to B5 is input from the input terminal 14 of the intra-bit accumulating means 5, the D flip-flop 16 is reset by the CLR signal and is latched by the adder 15 and the clock signal of 4fsc. The flip-flop 17 accumulates every clock.
When each bit is completed, it is latched by the D flip-flop 17 with the CLK signal, and the cumulative output 102 is output from the output terminal 18. The NRZ decoding circuit 6 determines whether the signal 102 accumulated for each bit is High (1) or Low (0).

Then, the NRZ confirmation circuit 7 determines whether or not the NRZ signal 103 is in a predetermined state. For example, B1 is 1, B2 is 0, B4 is B3 and B5.
If it is even parity, the High (1) signal is output to the synthesizing circuit 12 as the NRZ signal is confirmed.

Further, the low frequency components calculated by the in-line accumulating circuit 8 are input to the inter-field accumulating circuit 24.
When the power is turned on or the channel is switched, the CLR signal is input and the D flip-flop 44 is reset. The signal input from the input terminal 41 is 1/4 by the multiplier 42.
The output of the D flip-flop 44, which is the accumulated output up to the previous field, is multiplied by 3/4 and added by the adder 43. The addition result is output from the output terminal 46. Then, the reduction amount discrimination circuit 9 discriminates the difference between the low frequency component accumulated between the fields and the pedestal level, and when the difference between the low frequency component and the pedestal level is small, the High (1) signal is output to the synthesis circuit 12 and the inter-field accumulation. It is output to the circuit 24. When the low frequency band discrimination signal becomes High (1), the CLK signal is input to the D flip-flop 44 and the accumulated result is latched. Further, when the low frequency band discrimination signal becomes Low (0), the CLK signal is not input, so that the accumulated result of the current field is not latched and the accumulated result of the previous field is held.

On the other hand, the 4 / 7fsc component 105 extracted by the bandpass filter 3 is the 7-clock accumulator circuit 10.
And the confirmation signal portion of B25 is supplied to the seven D flip-flops 21a to 2a by the CLR signal.
1g is reset and B25 to B27 from the input terminal 19
While the signal is being input to the input terminal, the input signal is accumulated every 7 clocks using the adder 20 and the D flip-flops 21a to 21g. Accumulation result 1 when accumulated up to B27
06 is latched by the D flip-flop 22 by the CLK signal and output from the output terminal 23. 4 of confirmation signals accumulated every 7 clocks by the 7-clock accumulation circuit 10.
The / 7fsc component is input to the inter-field accumulating circuit 25. When the power is turned on or the channel is switched, the CLR signal is input and the D flip-flop 44 is reset.
The signal input from the input terminal 41 is set to 1 by the multiplier 42.
/ 4 multiplied by the adder 43 and the D flip-flop 44
The cumulative output up to the previous field, which is the output of
Therefore, it is added with 3/4 times. The addition result is output from the output terminal 46. The 4/7 fsc component detection circuit 11 detects the 4/7 fsc component accumulated between the fields, and when the sine wave of the 4/7 fsc component exists at a predetermined level or more, High (1) is output to the synthesis circuit 12. When all the outputs from the NRZ confirmation circuit 7, the low frequency band discrimination circuit 9 and the 4/7 fsc component detection circuit 11 are High (1) by the synthesizing circuit 12, it is determined that the identification signal is confirmed to be High (1) from the output terminal 13. ) A signal is output.

Further, the inter-field accumulator circuits 24, 25
May be configured by an input terminal 47, three D flip-flops 48, 49 and 50, three adders 51, 52 and 53, and an output terminal 54, as shown in FIG. .

In this case, when the power is turned on or the channel is switched, the CLR signal is input and the D flip-flops 48 to 50 are reset. The signal input from the input terminal 47 is supplied to the D flip-flop 48 and the three adders 51, 52 and 53. In the adder 53, the output from the D flip-flop 50, that is, the cumulative result of three fields and the reduction amount of the current field are added, and the result is output from the output terminal 54. Similarly, when the determination signal in the low frequency band determination circuit 9 becomes High (1), the CLK signal is input to the D flip-flops 48 to 50 and the accumulated result is latched. When the determination signal becomes Low (0), the CLK signal is not input, so that the accumulated result of the current field is not latched and the accumulated result of the previous field is held.

In the above embodiment, FIG. 2 (a)
Alternatively, as shown in FIG. 4A, the coefficients of the multipliers of the inter-field accumulating circuits 24 and 25 are 1/4 and 3/4, but the present invention is not limited to this, and other coefficients may be used. Well, the invention is not limited to coefficient values.

Further, in the above embodiment, FIG.
Alternatively, as shown in FIG. 4B, the number of D flip-flops in the inter-field accumulating circuits 24 and 25 is three or four.
However, the present invention is not limited to the number of D flip-flops. Furthermore, in order to change the accumulation characteristics of the inter-field accumulation circuits 24 and 25, or to leave the influence of not so long ago,
The CLR signal may be supplied periodically.

In the above-described embodiment, the field-wise accumulation is performed after the in-line accumulation is performed. However, the present invention is not limited to this, and the line-wise accumulation may be performed after the field-wise accumulation is performed. Good. In this case, the number of flip-flops corresponding to the accumulated field increases, and the device scale increases.

In the above embodiment, the sampling is performed at 4 fsc, but the present invention is not limited to this, and sampling may be performed at frequencies other than 4 fsc.
Further, the calculation may be performed with the analog signal as it is.

The NRZ signal, the low frequency band, and 4 / 7f
The result of the combination of confirmation of the sc component may be used for controlling the inter-field accumulation. When only the confirmation result of the NRZ signal is used, even if the identification signal is not inserted, the video signal happens to be a signal that matches the confirmation function of the NRZ and may be erroneously detected. By combining and using the confirmation result of the NRZ signal, the confirmation result of the 4/7 fsc component, and the determination result of the low frequency range, the possibility of erroneous detection is reduced. When this is applied to the first embodiment shown in FIG. 1, the confirmation result of the NRZ signal resistant to noise and 4/7
A signal obtained by ANDing the detection signal of the fsc component is supplied to the inter-field accumulating circuits 24 and 25, and the product signal becomes High.
At that time, accumulation is performed. The same applies when applied to the second embodiment.

Note that the confirmation signal is not discriminated, but 4 / 7f
Even when the peak point or zero-cross point of the sc sine wave, the trailing edge of B1 and the like are detected and used as the phase reference, the signal portion to be used is controlled in the same manner as in the above-mentioned method to accumulate the fields.

The identification signal is also used to detect the phase reference, and as a method thereof, the peak point or zero cross point of the 4/7 fsc sine wave and the falling position of B1 are detected and used. If the peak position or the like is used as it is, it will change due to noise. Therefore, it is necessary to reduce noise by accumulating between fields. The confirmation signal is used for controlling the inter-field accumulating circuit as in the above-described embodiment.

[0044]

According to the identification signal demodulating device of the first aspect,
After detecting and confirming the NRZ signal, since the confirmation signal is accumulated between fields, even if the identification signal disappears during broadcasting, the accumulation is stopped at that point and the accumulated data up to the field in which the identification signal is inserted. Therefore, even if the identification signal is multiplexed again, it can be accumulated with the previous data, so that the identification signal can be detected quickly.

According to the identification signal demodulating device of the present invention, the presence of the confirmation signal is confirmed from the result of accumulating the confirmation signals even when the video signal is regarded as an NRZ signal and is erroneously detected when there is no identification signal. In this case, the accumulated result is latched and the accumulated result is held, so that false detection is further suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an identification signal demodulation device of the present invention.

FIG. 2 is a block diagram showing a configuration of an inter-field accumulating circuit of the identification signal demodulating device of FIG.

FIG. 3 is a block diagram showing a second embodiment of the identification signal demodulation device of the present invention.

4 is a block diagram showing a configuration of an inter-field accumulating circuit of the identification signal demodulating device of FIG.

FIG. 5 is a diagram showing a waveform of an identification signal.

FIG. 6 is a block diagram showing a configuration of a conventional identification signal demodulation device.

FIG. 7 is a block diagram showing configurations of an in-bit accumulating unit and an in-line accumulating circuit.

[Explanation of symbols]

 6 NRZ decoding circuit 7 NRZ confirmation circuit 9 Low frequency band discrimination means 11 4 / 7fsc component detection circuit 24,25 inter-field accumulation circuit

Claims (2)

[Claims] 1. A decoding means for decoding an NRZ signal of a television identification control signal, a confirmation means for confirming whether or not the NRZ signal has a prescribed value, and a confirmation means for confirming the NRZ signal as prescribed. An identification signal demodulation device comprising: an accumulating means for accumulating the identification control signal for each field only in the case of being performed, and a detecting means for determining a confirmation signal and obtaining reference phase information from the accumulation result. 2. An identification control signal having an identification control signal confirmation means for confirming the confirmation signal of the accumulated identification control signal, an accumulation function for accumulating the identification control signal for each field, and a holding function for retaining an accumulation result. If the confirmation signal is confirmed by the confirmation means, the accumulated result is held, and if it is not confirmed, the accumulation result with the confirmation signal before that is used to accumulate with the next field. An identification signal demodulating device comprising: