JP2002044174A - Digital pll circuit and phase synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital PLL circuit and a phase synchronization method that can obtain a recovered carrier signal with high accuracy even under a deteriorated crosstalk environment. SOLUTION: The PLL circuit and the phase synchronization method of this invention are configured such that when a crosstalk wave exists in the vicinity of a frequency of an extracted complex carrier signal, 4-input selector circuits 60a, 60b discriminate whether or not a lock state is finished according to data from a mean value discrimination circuit or a fluctuation value averaging circuit, and select a state of the digital PLL circuit so that a storage coefficient is multiplied with a phase error when the lock state is finished and the result is outputted or a lock coefficient is multiplied with the phase error when the lock state is not finished and the result is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier synchronization circuit, a quadrature demodulation circuit, and an interference wave removing device used in a television receiver and a relay broadcasting device, and more particularly to a method for generating a stable and accurate reproduced carrier signal. The present invention relates to a carrier synchronization circuit, a quadrature demodulation circuit, and an interference wave removing device that can accurately remove an interference wave.

[0002]

2. Description of the Related Art In Japan, a television broadcast signal has a frequency of 90 MHz to 108 MHz and 1 MHz in a very high frequency band (VHF).
It is transmitted at 70 MHz to 222 MHz. On the other hand, as an ionosphere suddenly appearing at about the same altitude as the ionosphere (E layer) generated at an altitude of about 100 km, there is a so-called sporadic E layer (hereinafter abbreviated as "Espo"). It occurs frequently from April to August, and V
It has been known that abnormal propagation of HF radio waves is generated and causes interference with foreign FM audio broadcast waves in domestic TV broadcast signals.

[0003] Therefore, various devices (interference wave removing devices) are conventionally incorporated in some television broadcast relay devices in order to eliminate the influence of interference waves caused by E-spots. In recent years, especially with the development of digital signal processing technology,
For example, Japanese Patent Application Laid-Open No.
The circuit is integrated into a television receiver by converting the circuit into an LSI using digital processing as described in, for example, "Spot interference interference removal circuit" and "Digital processing of television signals" in JP-A-10-294901. Interference cancellers have been devised that can do this.

A quadrature demodulation circuit used in a conventional interference wave removing apparatus using digital processing for removing the interference wave caused by the E-spot will be described with reference to FIG. FIG. 3 is a configuration block diagram illustrating an example of a conventional quadrature demodulation circuit.

In a conventional quadrature demodulation circuit, as shown in FIG. 3, a received television broadcast signal is generally converted by an analog circuit into an intermediate frequency signal (IF signal) having a frequency １ ／ of the sampling frequency in a digital circuit at a subsequent stage. Signal conversion means 1 for converting the IF signal directly, A / D conversion means 2 for directly A / D converting the IF signal, and a station as a means for generating a local oscillation signal (hereinafter abbreviated as "local oscillation signal"). Quasi-synchronous detection means 4 for quasi-synchronous detection of an A / D-converted signal using a local oscillation signal to generate a complex baseband signal, a complex limiter and a narrow-band low-pass Complex carrier signal extraction means 5 for extracting a complex carrier signal using a filter (LPF);
The correction means 6 corrects the frequency and phase of the complex baseband signal using the complex carrier signal, and outputs a complex baseband signal subjected to perfect orthogonal synchronous detection.

Further, the local oscillation signal generating means 3 outputs "1, 1" at regular time intervals according to the sign of the cosine of each π / 2 radian.
, 0, -1, 0, 1... ”, Which is a data series that changes as follows (hereinafter referred to as“ COS signal ”).
And a data sequence that changes like “0, −1, 0, 1, 0,...” At regular time intervals according to the inverse of the sign of the sine every π / 2 radians. A certain quadrature local oscillation signal (hereinafter referred to as "-SIN signal")
-SIN signal generating means for outputting the SIN signal.

Next, the operation of the quadrature demodulation circuit of the conventional interference wave removing apparatus shown in FIG. 3 will be described.
The signal conversion means 1 converts the received signal to 1 /
A / D converter 2 converts the IF signal into an IF signal having a frequency of 4 and outputs the converted IF signal.

On the other hand, the COS signal generating means of the local oscillation signal generating means 3 and the -SIN signal generating means
The quasi-synchronous detection means 4 outputs the signal and the -SIN signal as a local oscillation signal, and
Performs a quasi-synchronous detection on the signal output by the controller to generate and output a complex baseband signal.

Then, the complex carrier signal extracting means 5
A complex carrier signal is extracted and output using a complex limiter and a narrow-band LPF, and the correcting unit 6 uses the complex carrier signal input from the complex carrier signal extracting unit 5
The frequency and phase of the complex baseband signal input from the quasi-synchronous detection means 4 are corrected, and a complex baseband signal subjected to perfect orthogonal synchronous detection is output.

[0010]

However, in the above-mentioned conventional quadrature demodulation circuit, the IF signal conversion means is an analog circuit, and the frequency of the IF signal fluctuates due to the influence of interference waves, The frequency may shift. Therefore, when trying to narrow the bandwidth of the narrow band LPF in order to increase the accuracy of the complex carrier signal extracting means, the signal of the frequency to be passed is shifted from the original position due to fluctuation or the like, so that the image to be passed is Since the carrier signal is attenuated without passing through and the demodulated video signal is distorted, the bandwidth of the narrow band LPF cannot be narrowed. Also, when an LPF having an extremely narrow passband is used, the scale of the hardware of the narrowband LPF becomes large, and it becomes impossible to reduce the circuit size, which is an advantage of the interference wave removing apparatus by digital processing. Anyway, it is difficult to extremely narrow the bandwidth of the narrow-band LPF.

Therefore, when an interference wave having a frequency close to the video carrier frequency arrives, the interference wave is mixed into the reproduced carrier signal, and there has been a problem that the carrier signal cannot be reproduced with high accuracy.

Further, when a modulated wave modulated by a video signal of a picture including a white portion having a large area is received, the carrier component disappears or the intensity of the carrier component decreases due to overmodulation, multipath distortion, or the like. For example, there is a problem that the accuracy of the reproduced carrier signal is deteriorated.

As described above, in the conventional interference wave removing apparatus using the quadrature demodulation circuit, the accuracy of the reproduced carrier signal cannot be increased. Is detected and removed, so that interference waves cannot be accurately removed and, at the same time, the output video signal is distorted.

As a method for explaining the problem that the accuracy of the reproduced carrier signal cannot be improved in the conventional quadrature demodulation circuit and the interference wave removing apparatus using the same, Japanese Patent Application No. 10-342843 discloses “Carrier Synchronization”. Circuit, quadrature demodulation circuit, and interference wave canceller "have been proposed. A carrier synchronization circuit, a quadrature demodulation circuit, and an interference wave removal device proposed in Japanese Patent Application No. 10-342843 reproduce a complex carrier signal having an in-phase component and a quadrature component (hereinafter, abbreviated as a “carrier signal”). In this case, the amplitude of a complex baseband signal obtained by quasi-synchronous detection is made constant by a complex limiter circuit, a carrier signal component is extracted by a narrow band low-pass filter circuit,
By reproducing the carrier signal locked to the phase of the carrier signal by the L circuit, the accuracy of the carrier signal is improved, and even if the level of the extracted carrier signal is attenuated or lost, the carrier signal is not removed due to the characteristics of the PLL circuit. Can be output continuously and stably, a stable complex baseband signal can be output based on the carrier signal obtained more stably, and interference waves can be detected and removed based on the more stable complex baseband signal. In addition, it is possible to accurately remove the interference wave and obtain a demodulated signal with less distortion.

However, in the digital PLL circuit using the above proposed technique, when the interference wave is generated at a frequency distant from the video carrier frequency (hereinafter, abbreviated as Fv), for example, Fv + 100 KHz or more, Since the interference wave component is completely removed in the LPF circuit, the interference wave component is not input to the PLL circuit, and there is no problem.
v, for example, at Fv + 50 KHz, the interference component is not completely removed by the LPF circuit.
When the interference wave component is input to the LL circuit and erroneously follows the interference wave component, an accurate reproduced carrier signal cannot be obtained, which causes a problem that the phase correction in the phase rotation circuit is not performed correctly.

The larger the erroneous tracking of the interference wave component, the greater the degradation of the image quality after the interference wave removal. A method of reducing the values of the direct term coefficient at the time of holding and the integral term coefficient at the time of holding (hereinafter, these two coefficients are abbreviated as the number of holding coefficients) of the circuit can be considered. However, if the holding coefficient is reduced, the tracking of the input interference wave component cannot be reduced, but the fluctuation of the subtractor output, which is the phase error between the received signal component and the reproduced carrier signal component, increases. At this time, as the power level of the interference wave component increases, the fluctuation of the subtractor also increases, and there is a possibility that the subtraction coefficient is switched. It becomes smaller again and switches to the holding coefficient again. That is, when the state where the power level of the interference wave component is large continues, the pull-in coefficient and the holding coefficient are frequently switched, so that the image quality after the interference wave removal frequently switches between a good state and a bad state. As a result, subjective image quality is degraded.

Another method is to forcibly switch to the holding coefficient when an interference wave is detected in the vicinity of Fv and continue to select the holding coefficient until the interference wave disappears. When Fv becomes discontinuous due to switching (switching the transmission source of the video signal, and when switching from the central station to the local station, instantaneous interruption of the broadcast signal or discontinuity of the carrier signal may occur) If the digital PLL circuit is out of phase due to some problem, it is necessary to quickly switch to the pull-in coefficient, so this method is not preferable. That is, in the digital PLL circuit proposed above, two factors of the pull-in coefficient and the holding coefficient are used.
Although there are two coefficients, there is a problem that they cannot be effectively switched only when a specific interference wave occurs.

The present invention has been made in view of the above circumstances, and provides a carrier synchronization circuit and a quadrature demodulation circuit capable of obtaining a highly accurate reproduced carrier signal even in a poor interference environment. The purpose is to provide.

[0019]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art is provided in a digital PLL circuit.
Determine the phase error between the extracted complex carrier signal and the reproduced complex carrier signal, and if there is an interference wave near the frequency of the extracted complex carrier signal, determine whether the lock state has been completed, If the lock state is completed, the phase error is multiplied by the holding coefficient and output. If the lock state is not completed, the phase error is switched by multiplying by the pull-in coefficient and output. Since the complex carrier signal is reproduced and output from the phase error after multiplication, the lock state is completed instead of switching between holding and pulling based on the extracted complex carrier signal that has deteriorated due to interference waves. By switching between the holding and the pulling in according to the determination, it is possible to stably generate a highly accurate reproduced carrier signal.

The present invention for solving the above-mentioned problems of the prior art is directed to a digital PLL circuit, wherein an integrating means for outputting a frequency error signal from a phase error and a control signal for generating a reproduced carrier signal has a phase error. First to fourth fixed value multiplication circuits for multiplying the signal by a direct term coefficient at the time of pull-in, a direct term coefficient at the time of holding, an integral term coefficient at the time of pull-in, and an integral term coefficient at the time of holding, respectively; Calculates the average value of the signal obtained by multiplying the phase error signal by the direct term coefficient at the time of pull-in or the direct term coefficient at the time of holding, calculates the absolute value of the average value, and determines whether the locked state is completed from the absolute value. An average value determination circuit that determines whether or not the phase error signal is multiplied by the integral term coefficient at the time of pull-in or the integral term coefficient at the time of holding, and calculates a fluctuation value of the integrated signal over a certain period of time. Complete A fluctuation value determination circuit that determines whether or not the detection signal input from the outside indicates that an interference wave is detected in the vicinity of the video carrier frequency; When the locked state is completed according to the determination result of the fluctuation value determining circuit or both, the signal from the second fixed value multiplying circuit is selected and output as the holding operation, and the locked state is completed. If not, a first selector circuit for selecting and outputting a signal from the first fixed value multiplication circuit as a pull-in operation, and an interference wave is detected near the video carrier frequency in a detection signal input from the outside. If the lock state is completed according to the determination result of the average value determination circuit or the determination result of the variation value determination circuit, or both, the fourth holding operation is performed. Selects and outputs the signal from the value multiplier circuit, when the locked state has not been completed, a second selector circuit for selectively outputting a signal from the second fixed value multiplier circuit as pull-in operation,
An integration circuit for integrating a signal output from the second selector circuit, a second adder for adding a signal output from the first selector circuit and a signal integrated by the integration circuit, and outputting the added signal as a control signal; Therefore, instead of switching between holding and pull-in based on the extracted complex carrier signal deteriorated by including the interference wave, it is based on the judgment result of the average value judgment circuit or the judgment result of the fluctuation value judgment circuit, or both. By switching between holding and pulling in according to whether or not the lock state has been completed, a stable and accurate reproduced carrier signal can be generated.

[0021]

Embodiments of the present invention will be described with reference to the drawings. Note that the function realizing means described below may be any circuit or device as long as the function can be realized, and some or all of the functions may be realized by software. is there. Further, the function realizing means may be realized by a plurality of circuits, or the plurality of function realizing means may be realized by a single circuit.

In a general concept, a digital PLL circuit and a phase synchronization method according to the present invention determine a phase error between an extracted complex carrier signal and a reproduced complex carrier signal, and calculate the phase error of the extracted complex carrier signal. If there is an interference wave near the frequency, it is determined whether or not the locked state is completed. If the locked state is completed, the phase error is multiplied by the holding coefficient and output, and the locked state is completed. If not, switch to output by multiplying the phase error by the pull-in coefficient, and output the complex carrier signal by reproducing it from the output phase error after coefficient multiplication.
Rather than switching between holding and pull-in based on the extracted complex carrier signal that contains interference waves and degraded, by switching between holding and pull-in according to whether the lock state has been completed, a stable and accurate reproduced carrier signal Can be generated.

Explained in terms of function realizing means, the digital PLL circuit according to the present invention calculates a phase error between an input complex carrier signal and a reproduced complex carrier signal and outputs the result as a detected phase error signal. When the amplitude of the input complex carrier signal becomes smaller than a predetermined value, the detected phase error signal is forcibly output as a zero data indicating that there is no phase difference. Integral means determines whether the locked state is completed when an interference wave exists near the frequency of the extracted complex carrier signal, and holds the phase error when the locked state is completed. A holding operation of multiplying and outputting a coefficient is performed. If the lock state is not completed, a pull-in operation of multiplying the phase error by a pull-in coefficient and outputting the result is performed. An integrating means for outputting a frequency error signal and a control signal for generating a reproduced carrier signal from the phase error after the coefficient multiplication outputted, and a complex carrier signal based on the control signal output by the integrating means. Oscillating means for generating a phase, reproducing and outputting the complex carrier signal from the phase, and returning the phase of the reproduced complex carrier signal to the phase comparing means for output, wherein the interference wave is included. Instead of switching between holding and pulling in based on the deteriorated extracted complex carrier signal, switching between holding and pulling in according to whether or not the lock state has been completed can generate a stable and accurate reproduced carrier signal. .

Incidentally, the correspondence between each means in the embodiment of the present invention and each part in FIG. 2 is shown. The phase comparing means corresponds to the phase comparing means 71, the integrating means corresponds to the integrating means 72, The oscillating means corresponds to the NCO circuit 73.

First, a quadrature demodulation circuit according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of a quadrature demodulation circuit according to an embodiment of the present invention. As shown in FIG. 1, a quadrature demodulation circuit according to an embodiment of the present invention multiplies a local oscillation signal by an RF signal input from a TV tuner or the like to perform frequency conversion.
A BPF circuit 12 as a means for removing unnecessary components such as an image signal generated by frequency conversion, and an A / D as a means for converting an analog IF signal into a digital IF signal.
Conversion circuit 13 and step Nyquist filter circuit 14
And a quasi-synchronous detection circuit 15 as means for outputting a complex baseband signal by performing quasi-synchronous detection using the COS signal and the -SIN signal as local oscillation signals, dividing the in-phase component and the quadrature component into respective components. Two first LPFs are provided corresponding to the in-phase component and the quadrature component of the baseband signal, and serve as means for removing an image component generated by the quasi-synchronous detection from the complex baseband signal of the corresponding component.
Circuits 16a, 16b and first LPF circuits 16a, 16
b, a first down-sampling circuit 17a, 17b as means for converting the sampling frequency of each signal, and a first down-sampling circuit 17a, 17b,
17b, delay circuits 18a and 18b as means for delaying each signal for a fixed time, and means for receiving the input of each signal, correcting the frequency / phase error, and outputting a signal which is completely synchronously detected. And a carrier as means for reproducing a carrier signal, dividing the reproduced carrier signal into an in-phase component and a quadrature component, and outputting a local oscillation signal for generating an IF signal. It basically comprises a synchronous circuit 20.

Further, as shown in FIG. 1, when the carrier synchronization circuit 20 converts the sampling frequency later,
Second LPF circuits 21a and 21b, which are provided corresponding to the signals of the in-phase component and the quadrature component, and perform band limitation so that aliasing distortion does not occur in the corresponding signals;
Provided corresponding to the second LPF circuits 21a and 21b,
A second down-sampling circuit 22 as means for converting the sampling frequency to the color subcarrier frequency of the NTSC signal
a, 22b and second down-sampling circuits 22a, 22
b, a complex limiter circuit 23 as means for processing so that the amplitude, that is, the absolute value of the complex baseband signal output from b, is provided corresponding to each of the in-phase component and quadrature component signals output by the complex limiter circuit 23. And a third LPF circuit (narrow band low-pass filter circuit) as means for removing components other than the video carrier component of each corresponding signal
24a, 24b and the phases of the signals (complex carrier signals) output from the third LPF circuits 24a, 24b are locked,
In this phase, by continuously reproducing and outputting the complex carrier signal, the accuracy of the carrier signal is enhanced, and even when the amplitude of the complex carrier signal is small, the stable complex carrier signal is free-running and reproduced, and the output is performed. A digital PLL circuit 25 for outputting a signal representing a difference between the video carrier frequency of the IF signal and twice the frequency of the color subcarrier frequency of the NTSC signal as a frequency error signal.
And up-sampling circuits 26a and 26b that increase the sampling frequency by interpolating a signal of “0” into each of the in-phase component and quadrature component signals input from the digital PLL circuit 25.
And a fourth LPF circuit 2 provided as a means for outputting a carrier signal obtained by interpolating and reproducing each signal, the signal being provided corresponding to each signal whose sampling frequency has been increased by interpolation.
7a, 27b, a loop filter circuit 28 for removing high frequency components from the frequency error signal output from the digital PLL circuit 25, and the multiplier 11 generates an IF signal based on the signal output from the loop filter circuit 28. As a means for outputting a local oscillation signal used for
29.

Note that, at the subsequent stage of the digital quadrature demodulation circuit according to the embodiment of the present invention, a signal of each component of the in-phase component and the quadrature component of the perfect synchronous detection signal output by the digital quadrature demodulation circuit is subjected to complex FFT processing. If a cancel circuit 10 (shown by a broken line in FIG. 1) for detecting the frequency and level of the interference wave and adaptively canceling the interference wave component by a Hilbert transform / adaptive filter circuit or the like is provided, the interference wave removing device You can also. As a characteristic part of the present invention, the cancel circuit 10 outputs a detection signal indicating whether or not an interference wave is detected in the vicinity of a video carrier frequency (hereinafter simply referred to as Fv). Supplying.

Hereinafter, each part will be described in detail. Multiplier 1
1 multiplies a local oscillation signal input from the carrier synchronization circuit 20 by an RF signal input from a TV tuner or the like (a signal obtained by amplifying a signal including an interference wave input from an antenna to a predetermined level). The frequency conversion of the RF signal is performed. For example, ideally, the RF signal is converted to the sampling frequency 2
7.15 which is 1/4 frequency of 8.63636 MHz
It is converted into an 809 MHz IF signal and output. Here, 28.63636 MHz is a frequency eight times the chrominance subcarrier frequency of the NTSC signal.
7.15809 MHz is twice the frequency of the color subcarrier frequency of the NTSC signal.

The BPF circuit 12 removes an image component and an unnecessary band component generated by the frequency conversion from the IF signal input from the multiplier 11 and outputs the result. The A / D conversion circuit 13 converts the signal input from the BPF circuit 12 into a digital signal at a clock frequency of, for example, 28.63636 MHz (eight times the color subcarrier frequency of the NTSC signal), and converts the signal into a digital IF signal. Output.

The step Nyquist filter circuit 14
Since the NTSC signal is a vestigial sideband signal, if the detection is performed as it is, the frequency (± 1.25 M) near the video carrier frequency is considered in consideration of the occurrence of distortion in the video signal.
Hz), that is, Double Side Ban (DSB)
d) The signal in the area is attenuated by about 6 dB compared to the signal component in the SSB (Single Side Band) area.

The quasi-synchronous detection circuit 15 outputs the COS signal and-
The signal output from the step Nyquist filter 14 is quasi-synchronously detected using the SIN signal as a local oscillation signal, and a complex baseband signal having each of an in-phase component and a quadrature component is output.

The first LPF circuit 16a removes an image component generated with the quasi-synchronous detection from the in-phase component of the complex baseband signal output from the quasi-synchronous detection circuit 15, and the first LPF circuit 16b Is to remove an image component generated due to the quasi-synchronous detection from the quadrature component of the complex baseband signal output from the quasi-synchronous detection circuit 15.

The first down-sampling circuit 17a and the first
Of the first LP
The signal input from the F circuit 16a and the first LPF circuit 1
6b is thinned out at a ratio of 2: 1 with the signal input from
The sampling frequency is converted from 28.63636 MHz to 14.31818 MHz (four times the color subcarrier frequency of the NTSC signal), which is half of that.

The delay circuits 18a and 18b respectively delay the signals input from the first down-sampling circuit 17a and the first down-sampling circuit 17b for a certain period of time, and perform a carrier synchronization circuit 20 described later. Is output to the phase rotation circuit 19 in such a manner that the timing is the same as the timing at which the carrier signal is reproduced and output to the phase rotation circuit 19.

The phase rotation circuit 19 includes the carrier synchronization circuit 2
0 corrects the frequency phase error of the complex baseband signal having in-phase and quadrature components input from the delay circuits 18a and 18b based on the complex carrier signal having in-phase and quadrature components reproduced and output. , Are output as the in-phase component and the quadrature component of the complete synchronous detection output.

The second LP of the carrier synchronization circuit 20
The F circuit 21a and the second LPF circuit 21b respectively take out only components near the video carrier frequency from the signals input from the first down sampling circuit 17a and the first down sampling circuit 17b, respectively. Thereafter, the band is limited by the down-sampling circuit 22 so that aliasing distortion does not occur, and then output.

The second down sampling circuit 22a and the second down sampling circuit 22a
Of the down-sampling circuit 22b is the second L
Signals output from the PF circuit 21a and the second LPF circuit 21b are thinned out, for example, to 4: 1, and the sampling frequency is converted to 3.57954 MHz (the color subcarrier frequency of the NTSC signal) and output.

The complex limiter circuit 23 processes the complex signals output from the second down-sampling circuits 22a and 22b so that the amplitude, that is, the absolute value, becomes constant, and outputs a complex baseband signal having a constant amplitude. is there. A specific configuration of the complex limiter circuit 23 is disclosed in
A circuit as shown in “Complex carrier carrier limiter circuit” in JP-A-03999 can be considered.

The third LPF circuit 24a and the third LPF circuit 24b are narrow-band low-pass filter circuits, and are provided corresponding to signals of the in-phase component and the quadrature component output from the complex limiter circuit 23, respectively. Then, components other than the video carrier component of each corresponding signal are removed and output.

The digital PLL circuit 25 includes a third LPF
The accuracy of the in-phase component and quadrature component signals (complex carrier signal) output from the circuit 24a and the third LPF circuit 24b is increased, and a stable carrier signal is reproduced even when the amplitude of the complex carrier signal is small. And a signal representing the difference between the video carrier frequency of the IF signal and twice the frequency of the color subcarrier frequency of the NTSC signal is output as a frequency error signal.

That is, the digital PLL circuit 25
Instead of narrowing the pass band of the LPF circuit 24,
According to the characteristics of the circuit, the accuracy of the complex carrier signal output from the third LPF circuit 24 is increased. Similarly, as a characteristic of the PLL circuit, the self-propelled operation is performed for a certain period without a signal input. Because of the flywheel effect,
Even if the complex carrier signal is lost or attenuated due to overmodulation, multipath distortion, or the like, a stable carrier signal is reproduced. Digital PLL
The specific configuration of the circuit 25 will be described later.

The up-sampling circuit 26a and the up-sampling circuit 26b are respectively provided with a digital PLL circuit 25.
The signal of "0" is interpolated into each signal of the in-phase component and the quadrature component input from to increase the sampling frequency, for example,
It is converted to a frequency of 14.31818 MHz which is four times as high. Fourth LPF circuit 27a and fourth LPF circuit 2
7b is obtained by interpolating signals input from the up-sampling circuit 26a and the up-sampling circuit 26b, respectively.
It is output as a reproduced carrier signal.

The loop filter circuit 28 has a digital PL
It removes high frequency components from the frequency error signal output from the L circuit 25. The VCO 29 is a voltage-controlled oscillator and outputs a local signal used to generate an IF signal based on a signal input from the loop filter 28. The VCO 29 is controlled by a digital PL
It is preferable that the response speed is sufficiently slower than the response speed of the L circuit 25 so that the feedback control does not compete with each other. Otherwise, the digital PLL circuit 2
This is because the VCO 29 is controlled before 5 does not respond, and accurate control cannot be performed.

Here, the configuration of the digital PLL circuit 25 will be described with reference to FIG. FIG. 2 is a configuration block diagram illustrating an example of the digital PLL circuit 25. P
The LL circuit generally includes a phase comparing unit, an integrating unit, and an oscillating unit.
Referring to FIG. 2, a digital signal processing type second-order Tan-DPL using an NCO (Numerically Controlled Oscillator) as an oscillation means.
The L circuit will be described. The digital PLL circuit 25
Other circuit configurations may be used.

The digital PLL circuit shown in FIG. 2 outputs the phase error between the input complex carrier signal and the reproduced complex carrier signal as a phase error signal, and the amplitude of the input complex carrier signal becomes smaller than a constant value. A phase comparing means 71 for forcibly outputting the phase error signal as zero when the signal becomes smaller, and a video carrier frequency of an IF signal and an NTSC signal from the phase error signal based on the input complex carrier signal. A frequency error signal representing a difference from a frequency twice as high as the color subcarrier frequency of
Integrating means 72 for generating an NCO control signal as a signal for controlling the oscillation frequency of the NCO necessary for reproducing the carrier signal; and a phase value of the carrier signal based on the NCO control signal output from the integrating means 72. The carrier signal reproduced and reproduced from the value is output as an in-phase component and a quadrature component separately, and the phase value of the reproduced carrier signal is fed back to the phase comparing means 71 for output.
And a CO circuit (numerically controlled oscillator circuit) 73.

The phase comparing means 71, as shown in FIG.
An arctangent circuit 41 as means for calculating the phase of the complex carrier signal from the input complex carrier signals of the in-phase component and the quadrature component, a phase of the complex carrier signal reproduced by the NCO circuit 73, A subtracter 42 as means for calculating a difference (phase error signal) from the calculated phase.
And the phase error signal θ is θ = θ0 + 2πn (where n is
A first ± π conversion circuit 43 as a means for converting into a value of θ0 (−π <θ0 <π) which becomes an integer, and a means for outputting zero data as a signal representing a value of “0”. A zero data circuit 44, an absolute value circuit 45 as a means for calculating and outputting the absolute value of the input complex carrier signal having the in-phase component and the quadrature component, and an absolute value output by the absolute value circuit 45, It is determined whether or not a threshold value set as a level for discriminating whether or not the carrier signal has disappeared is determined in advance, and whether or not the level of the carrier signal is sufficient is determined. When the first threshold circuit 46 as means and the first threshold circuit 46 determine that the carrier signal is at a sufficient level, the phase error signal output from the first ± π conversion circuit 43 θ0 is integrated by Output to 2, otherwise, first as a means for selectively outputting a signal representing "0" output from the zero data circuit 44 to the integrating means 72
And a selector circuit 47.

The integrating means 72 is provided with a phase comparing means 71.
Output the direct term coefficient α1 at the time of pull-in, the direct term coefficient α2 at the time of holding, and the integral term coefficient β1 at the time of pull-in.
And first to fourth fixed value multiplying circuits 48a to 48d as means for multiplying each by the integral term coefficient β2 at the time of holding, and the phase error output from the first ± π converting circuit 43 of the phase comparing means 71. As a means for judging whether or not the pull-in is completed by judging whether or not the signal θ0 has exceeded the threshold set as an error for which the pull-in is completed in advance and performing the holding operation, A second threshold circuit 49 and a determination result or an average value determination circuit 62 in the second threshold circuit 49 according to a detection signal from a carrier circuit indicating whether or not an interference wave is detected near the video carrier frequency. The second fixed value multiplying circuit 4 corresponds to the judgment result of
A four-input selector circuit 61a (referred to as a "first selector circuit" in the claims) as means for selectively outputting a signal output by the first fixed value multiplication circuit 48a or a signal output by the first fixed value multiplication circuit 48a; According to the detection signal from the circuit, the fourth fixed value multiplying circuit 48d responds to the judgment result in the second threshold circuit 49 or the judgment result in the average value judgment circuit 62 and the judgment result in the fluctuation value judgment circuit 63. Output signal or third fixed value multiplying circuit 48c
And a four-input selector circuit 61b (referred to as a "second selector circuit" in the claims) as means for selectively outputting a signal output by the four-input selector circuit 61b.
Adder 5 as means for integrating the signal output by
1 and a clip circuit 52 and a latch circuit 53 (in the claims, the first adder 51, the clip circuit 52 and the latch circuit 53 are collectively referred to as an "integration circuit"), and a 4-input selector circuit 61a outputs. A second adder 54 as a means for adding the signal and the signal output from the latch circuit 53 and outputting as a signal (NCO control signal) necessary for reproducing the carrier signal, and a signal output from the latch circuit 53 Is converted into an analog signal, and the D / A conversion circuit 55 outputs the signal as a frequency error signal.

Further, the NCO circuit 73 includes an integrating means 72
(NCO control signal) output from the second adder 54
Adder 56, a second ± π conversion circuit 57, and a second latch circuit as means for performing integration while maintaining the range of -π to π and outputting a signal corresponding to the phase of the carrier signal. 58, and a COS circuit 59 that reproduces and outputs an in-phase component of the carrier signal from a signal output from the latch circuit 58 and corresponding to the phase of the carrier signal. And a SIN circuit 60 for reproducing and outputting the orthogonal component of the signal.

The respective components will be specifically described below. The arctangent circuit 41 of the phase comparing means 71 calculates the arctangent of the complex carrier signal from the input complex carrier signal having the in-phase component and the quadrature component. , And phase signals. The arc tangent circuit 41 includes, for example, an RO in which an arc tangent value corresponding to each component of the complex carrier signal is stored in advance.
This can be realized by using M (read only memory).

The subtracter 42 calculates the difference between the phase signal output from the arctangent circuit 41 and the signal representing the phase of the reproduced carrier signal input from the NCO circuit 73, and outputs the result as a phase error signal. Things.

The first ± π conversion circuit 43 converts the phase error signal θ output from the subtractor 42 into θ0 (−π <θ0 <π) such that θ = θ0 + 2πn (where n is an integer). It is something to convert. For example, the value of the tangent is a value that periodically repeats a value corresponding to -π to π, and thus utilizes such a property.

The zero data circuit 44 outputs a value (zero data) to be output by the first ± π converting circuit 43 when θ 0 = 0. That is, the zero data is a phase error signal indicating that the phase error is “0”.

The absolute value circuit 45 multiplies the absolute value of the amplitude of the carrier signal, that is, the carrier signal, by the complex conjugate, from the signals of the in-phase component and the quadrature component of the input complex carrier signal. It outputs a signal indicating the result of finding the square root.

The first threshold circuit 46 previously holds a threshold value for determining whether or not the carrier signal has a sufficient amplitude, and the amplitude absolute value calculated by the absolute value circuit 45 Is to determine whether or not the stored threshold value is exceeded, and to output a signal indicating the result of the determination.

When the first selector circuit 47 determines that the carrier signal has a sufficient amplitude in accordance with the signal input from the first threshold circuit 46,
The signal output from the first ± π conversion circuit 43 is selectively output to the integrator 72. Otherwise, the zero data circuit 44
Are selectively output to the integration means 72.

That is, the phase comparing means 71 distributes and inputs the in-phase component and the quadrature component of the input complex carrier signal to the arctangent circuit 41 and the absolute value circuit 45, and the arctangent circuit 41 converts the phase signal. The absolute value circuit 45 outputs a signal representing the absolute value of the amplitude of the complex carrier signal, and the subtracter 42 outputs
The difference between the phase signal of the reproduced carrier signal and the phase signal of the reproduced carrier signal output from the circuit 73 is calculated as a phase error signal.
3 outputs the phase error signal (referred to as “detected phase error signal” in the claims) as a value between −π and π.

On the other hand, according to the signal representing the amplitude absolute value output from the absolute value circuit 45, the first threshold circuit 46
However, it is determined whether or not the amplitude of the input complex carrier signal is sufficient. If it is determined that the amplitude is sufficient, the first selector circuit 47 receives the input from the first ± π conversion circuit 43. When the first threshold circuit 46 determines that the amplitude of the input complex carrier signal is not sufficient, the first selector circuit 47
Output the zero data (the phase error signal indicating that the phase error is “0”) output from the zero data circuit 44.

If the amplitude absolute value of the input complex carrier signal becomes extremely small, the accuracy of the phase signal obtained from the complex carrier signal may deteriorate and the accuracy of the reproduced complex carrier signal may deteriorate. If the input complex carrier signal disappears for a certain time due to overmodulation or the like, a normal complex carrier signal may not be able to be continuously reproduced. According to this, when the amplitude absolute value of the input complex carrier signal becomes smaller than a preset value, the phase error signal is forcibly set to zero and the digital PL
There is an effect that the state of the L circuit can be maintained and the NCO can be continuously oscillated.

The components of the integration means 72 will be described. First to fourth fixed value multiplication circuits 48a to 48d are:
The phase error output by the selector circuit 47 of the phase comparing means 71 is directly added to the direct term coefficient α1 at the time of pull-in, the direct term coefficient α2 at the time of holding, and the integral term coefficient β1 at the time of pull-in.
And the integral term coefficient β2 at the time of holding.

Thus, a formula such as γi = αxi + βΣxi (where x is a signal output from the selector circuit 47) is operated to generate a frequency error signal (βΣxi portion) and a reproduced carrier signal. The required NCO control signal γ is obtained. Note that Σ is an addition for i.

The second threshold circuit 49 is connected to the first ±
It is determined whether or not the pull-in operation has been completed from the phase error signal output from the π-forming circuit 43, and the result of the determination is output as a first coefficient selection signal. Specifically, the second threshold circuit 49 previously holds a threshold value for determining whether or not the pull-in operation has been completed, and outputs the phase error signal output from the first ± π conversion circuit 43. When the phase error signal exceeds the threshold value, it is determined that the pull-in operation has not been completed. When the phase error signal does not exceed the threshold value, the pull-in operation is not performed. It is determined that the operation has been completed, and a signal (first coefficient selection signal) indicating whether or not the pull-in operation has been completed is output to the four-input selector circuit 61a and the four-input selector circuit 61b. Here, the first coefficient selection signal may indicate whether or not the pull-in operation has been completed by turning the signal on / off.

Here, the second threshold circuit 49
In order to prevent so-called hunting, which continuously outputs electric vibration, it is preferable to compare and determine the absolute value of the input signal with a value obtained by averaging for a certain period of time. As another method for preventing hunting, a threshold value a and a threshold value b are used to provide a hysteresis characteristic so that the threshold value a is exceeded. After a transition to a state not exceeding a and a holding operation, it is preferable to transition to a pull-in operation when a threshold value b having a value larger than the threshold value a is exceeded.

A four-input selector circuit 61a (referred to as "first selector circuit" in claims) and a four-input selector circuit 61b (referred to as "second selector circuit" in claims) are shown in FIG. The detection signal from the cancel circuit 10, the first coefficient selection signal from the second threshold circuit 49, the second coefficient selection signal from the average value determination circuit 62 described later, or the fluctuation value determination circuit 6 described later.
The selector circuit selectively outputs one of two fixed-value multiplication circuit outputs according to the states of four signals of the third coefficient selection signal from the third coefficient selection signal.

Specifically, the four-input selector circuits 61a and 61
The input selector circuit 61b detects the interference wave in the vicinity of Fv according to whether or not the interference wave is detected in the vicinity of the video carrier frequency (hereinafter simply referred to as Fv) indicated by the detection signal from the cancel circuit 10. If not,
The same operation as the above-mentioned proposed technology is performed, and when an interference wave is detected near Fv, the characteristic operation of the present invention is performed.

First, a specific operation in the case where no interference wave is detected near Fv will be described. When the detection signal from the carrier circuit 10 indicates that no interference wave is detected near Fv, the operation of the proposed technique does not cause any inconvenience, and therefore the first operation from the second threshold circuit 49 is not performed. The fixed value multiplication circuit is selected according to the coefficient selection signal.
That is, in the 4-input selector circuit 61a, when the first coefficient selection signal from the second threshold circuit 49 indicates that the pull-in operation is completed, the second fixed value multiplication circuit 4a
8b is selectively output to the adder 54. If the first coefficient selection signal does not indicate the completion of the pull-in operation, the signal output from the first fixed value multiplication circuit 48a is selectively output. This is output to the adder 54. On the other hand, in the four-input selector circuit 61b, the second threshold circuit 4
9 indicates that the pull-in operation has been completed, the signal output from the fourth fixed value multiplying circuit 48d is selectively output to the adder 51, and the first coefficient selection signal is output. If does not indicate completion of the retraction operation, the third
Of the fixed value multiplying circuit 48c is selectively output to the adder 51.

Next, a specific operation in the case where no interference wave is detected near Fv will be described. When the detection signal from the carrier circuit 10 indicates that the interference wave is detected near Fv, the configuration of the proposed technique causes a problem because the second threshold circuit 49 malfunctions. Therefore, as a feature of the present invention, regardless of the first coefficient selection signal from the second threshold circuit 49, the second coefficient selection signal from the average value determination circuit 62 described later and the variation value determination circuit 63 described later The fixed value multiplication circuit is selected in accordance with the third coefficient selection signal from.

That is, in the 4-input selector circuit 61a,
When both the second coefficient selection signal from the average value determination circuit 62 and the third coefficient selection signal from the variation value determination circuit 63 indicate that the pull-in operation (lock state) is completed. , A signal from the second fixed-value multiplying circuit 48b having a holding coefficient is selected, and if one or both of them does not mean that the pull-in operation (locked state) has been completed, This is to select a signal from the first fixed value multiplication circuit 48a having a pull-in coefficient.

On the other hand, in the four-input selector circuit 61b, the second coefficient selection signal from the average value judgment circuit 62 and the third coefficient selection signal from the fluctuation value judgment circuit 63 are both pulled in (locked). In the case of completion of (state), a signal from the fourth fixed-value multiplication circuit 48d having a holding coefficient is selected, and either one or both of them is used to complete the pull-in operation (lock state). If it is not, the signal from the third fixed-value multiplying circuit 48c having a pull-in coefficient is selected.

The average value judging circuit 62 receives the signal output from the four-input selector circuit 61a, calculates the average value for a certain period, obtains the absolute value of the average value, and performs a pull-in operation (A) held in advance. A second value indicating whether the pull-in operation (locked state) has been completed is compared with a threshold value for determining whether the locked state has been completed and the absolute value of the calculated average value. It outputs a coefficient selection signal.

When the phase pull-in operation (locked state) is completed, the input to the average value determination circuit 62 slowly and temporarily follows random external noise generated temporarily and instantaneously on the reference signal side. Since the average value is calculated, the average value is close to zero. Since the original frequency error signal is stored in the integrating circuit, the phase advance (for example, a signal having a positive value) and the phase delay (for example, a signal having a negative value) from the selector circuit 47 are substantially equal. Is likely to be output to If the pull-in (locked state) is not completed, the correct frequency error signal is not stored in the integration circuit, so that the average value determination circuit 6
The average value of the inputs to 2 is indeterminate. Therefore, it is possible to determine whether or not the pull-in operation has been completed by calculating the average value for a certain period by the average value determination circuit 62 and comparing the absolute value with a predetermined threshold value. the above,
For a certain period, if the period is too short, an appropriate average value may not be obtained, and if the period is too long, a delay time until completion of the pull-in operation becomes large. It is desirable to set an appropriate value in consideration of the specifications and operation form of the system that uses.
As for the threshold value, any value may be used as long as it can distinguish between a state where the pull-in operation is completed and a state where the pull-in operation is not completed.

The first adder 51 adds the signal input from the four-input selector circuit 61b and the signal input from the latch circuit 53 by feedback, and outputs the result to the clip circuit 52. The clipping circuit 52 performs so-called overflow processing and underflow processing so that a signal input from the first adder 51 does not exceed a size that can be held by the first latch circuit 53. is there.

The first latch circuit 53 includes a clip circuit 5
2 to temporarily store (latch) the signal input from
The signal is fed back to the first adder 51 and output, is output to the second adder 54, and is also output to the D / A conversion circuit 55. Therefore, the first adder 51, the clipping circuit 52, and the first latch circuit 53 perform the addition by performing the addition cyclically as a whole, and execute the integration. It is called.

The fluctuation value judgment circuit 63 outputs a signal output from the latch circuit 53, that is, a four-input selector circuit 61b.
Calculates a fluctuation value of the integration result of the signal output from the controller for a certain period of time, and determines a threshold value for judging whether or not the pull-in operation (locked state) held in advance has been completed and the calculated fluctuation value. In comparison, a third coefficient selection signal indicating whether or not the pull-in operation (locked state) has been completed is output from the comparison result. The fluctuation value here is the difference between the maximum value and the minimum value in a certain period (maximum value-minimum value).
Is the value obtained in

Here, the signal corresponding to the frequency error signal is output from the integration circuit when the pull-in operation (lock state) is completed, as described above. The frequency error signal includes a reference signal (received signal) f1 and a reproduced signal f2.
And the frequency difference Δf (Δf = f1−f2),
When Δf is ± 0, ± 0 is obtained from the integration circuit. Similarly, when f1> f2 (f1 = f2 + Δf), the integration circuit outputs a positive or negative DC value corresponding to + Δf, and when f1 <f2 (f1 = f2-Δf), the integration circuit outputs − △. A negative or positive DC value corresponding to f is obtained. At this time, these two
The two DC values are constant when Δf does not fluctuate with time. Naturally, when △ f changes slowly, the output of the integration circuit also changes slowly, so that the frequency stability of f1 and f2 may change greatly in the long term, but in a short-term fixed period, An almost constant value should be obtained.

When the pull-in operation is not completed, since the correct frequency error is not accumulated in the integration circuit, the signal output from the integration circuit is undefined, and a constant value may be obtained over a certain period. Will be lower. As described above, the output of the integration circuit is monitored for a certain period,
If the fluctuation is small, it can be determined that the pull-in operation has been completed, and if the fluctuation is large, it can be determined that the pull-in operation has not been completed. As a means for obtaining the variation, a method of calculating a difference between the maximum value and the minimum value of the integration circuit in a certain period (a value obtained by a maximum value−a minimum value) may be used.

The second adder 54 adds the signal input from the four-input selector circuit 61a and the signal input from the latch circuit 53, and outputs the result to the NCO circuit 73 as an NCO control signal. Further, in a state where the digital PLL circuit is sufficiently synchronized (a state in which the pull-in is completed), the value held by the first latch circuit 53 and the output value are based on the base of the complex carrier signal input to the digital PLL circuit. Is proportional to the frequency error of the IF signal. Therefore, the D / A conversion circuit 55 is connected to the first latch circuit 53
Is converted into an analog signal and output as a frequency error signal.

Next, the operation of the integrating means 72 will be described. In the integrating means 72, the first-to-fourth fixed value multiplying circuits 48 a to 48 d respectively add, to the phase error signal output by the first selector circuit 47 of the phase comparing means 71, The direct term coefficient α2 at the time, the integral term coefficient β1 at the time of pull-in, and the integral term coefficient β2 at the time of holding are multiplied, and the output of the first fixed-value multiplication circuit 48a and the output of the second fixed-value multiplication circuit 48b are multiplied. The output is input to the four-input selector circuit 61a, and the output of the third fixed-value multiplication circuit 48c and the output of the fourth fixed-value multiplication circuit 48d are input to the four-input selector circuit 61b.

On the other hand, based on the phase error signal input from the first ± π converting circuit 43 of the phase comparing means 71, it is determined whether or not the second threshold circuit 49 has completed the pull-in operation. The first coefficient selection signal indicating the determination result is a four-input selector circuit 61a and a four-input selector circuit 61.
b.

At this time, in the 4-input selector circuit 61a,
A detection signal from the cancellation circuit 10 indicating whether or not an interference wave is detected near the video carrier frequency Fv is input, and when it is determined from the detection signal that no interference wave is detected near Fv, the second signal is output. It is determined based on the first coefficient selection signal from the threshold circuit 49 whether or not the pull-in operation has been completed. If the pull-in operation has been completed, the signal output from the second fixed-value multiplying circuit 48b is selected. When the first coefficient selection signal does not indicate the completion of the pull-in operation,
A signal output from the first fixed value multiplication circuit 48 a is selected and output to the second adder 54.

On the other hand, if it is determined from the detection signal that the interference wave is detected in the vicinity of Fv, the second coefficient selection signal from the average value determination circuit 62 and the third coefficient selection signal from the variation value determination circuit 63 It is determined whether or not the pull-in operation has been completed based on the selection signal. If the pull-in operation has been completed, the signal output from the second fixed value multiplying circuit 48b is selected and output to the second adder 54. If the completion of the pull-in operation is not indicated, the first fixed value multiplication circuit 48
The signal output by a is selected and output to the second adder 54.

Similarly, in the 4-input selector circuit 61b,
A detection signal from the cancellation circuit 10 indicating whether or not an interference wave is detected in the vicinity of the video carrier frequency Fv is input, and if it is determined from the detection signal that no interference wave is detected in the vicinity of Fv, the second It is determined whether or not the pull-in operation has been completed based on the first coefficient selection signal from the threshold circuit 49. If the pull-in operation has been completed, the signal output from the fourth fixed value multiplication circuit 48d is selected. When the first coefficient selection signal does not indicate the completion of the pull-in operation,
A signal output from the third fixed value multiplication circuit 48 c is selected and output to the first adder 51.

On the other hand, if it is determined from the detection signal that the interference wave is detected in the vicinity of Fv, the second coefficient selection signal from the average value determination circuit 62 and the third coefficient selection signal from the variation value determination circuit 63 It is determined whether or not the pull-in operation has been completed based on the selection signal. If the pull-in operation has been completed, the signal output from the fourth fixed value multiplication circuit 48 d is selected and output to the first adder 51. If the completion of the pull-in operation is not indicated, the third fixed value multiplication circuit 48
The signal output by c is selected and output to the first adder 51.

The signal selected by the four-input selector circuit 61b is integrated by the first adder 51, the clip circuit 52, and the first latch circuit 53, and is converted into an analog signal by the D / A conversion circuit 55. And output as a frequency error signal. At this time, the frequency error signal output from the first latch circuit 53 and resulting from the integration is input to the fluctuation value determination circuit 63, and it is determined whether or not the pull-in operation has been completed. The coefficient selection signal is output to the four-input selector circuit 61a and the four-input selector circuit 61b, and is used as a reference for coefficient selection.

On the other hand, the signal output from the four-input selector circuit 61a is supplied to the first latch circuit 5 by the second adder 54.
3 is added to the frequency error signal of the integration result output from 3 and output to the NCO circuit 73 as an NCO control signal. At this time, the signal output from the four-input selector circuit 61a is input to the average value determination circuit 62, and it is determined whether or not the pull-in operation has been completed. The signals are output to the input selector circuit 61a and the four-input selector circuit 61b, and are used as criteria for coefficient selection.

According to such an integrating means 72, a signal output from the D / A conversion circuit 55 is used as a signal for controlling the frequency of a local oscillation signal used when frequency-converting an RF signal into an IF signal. Therefore, the video carrier frequency of the IF signal can be accurately synchronized with an integer fraction of the sampling frequency, and the return of the high-frequency component caused by the quantization can be made to match the video carrier frequency, thereby preventing the occurrence of flicker and beat. effective.

When no interference wave is generated near the video carrier frequency Fv, the second threshold circuit 49 determines whether or not the pull-in has been completed with the phase error signal. Since the fixed value multiplication circuit is selected according to the signal to determine whether the signal is to be pulled in or held, the frequency error signal and the NCO control signal can be stably supplied in accordance with the highly accurate phase error signal.

On the other hand, when an interference wave is generated in the vicinity of Fv, whether or not the pull-in is completed in the average value determination circuit 62 is not performed according to the first coefficient selection signal from the second threshold circuit 49. Both the coefficient selection signals complete the pull-in operation in accordance with the second coefficient selection signal which is the result of the determination and the third coefficient selection signal which is the result of the determination as to whether or not the pull-in is completed in the fluctuation value determination circuit 63. The fixed multiplier 48b48d having the holding coefficient
And if one or both of them has not completed the pull-in operation, the signals from the fixed-value multiplication circuits 48a and 48c having the pull-in coefficients are selected. When the interference wave is generated in the vicinity and the accuracy of the phase error signal is lowered, the determination based on the phase error signal is not performed, and the pull-in is performed by the fluctuation of the average value of the phase error signal or the integrated value of the phase error signal. Since the switching is performed by judging whether or not the lock state is completed, the frequency error signal and the NCO control signal can be stably supplied.

The switching from the holding coefficient to the pull-in coefficient must be always provided as a recovery measure when the digital PLL circuit is out of phase. If no interference wave is detected in the vicinity of Fv, it is possible to determine whether the pull-in operation has been completed by the second threshold circuit 49. Therefore, the first coefficient selection signal from the second threshold circuit 49 determines the holding coefficient from the holding coefficient. Switching the coefficient to the pull-in coefficient does not cause any inconvenience, but when the interference wave is detected in the vicinity of Fv, the threshold circuit 49 malfunctions. Therefore, means for switching the two coefficients without using this is necessary. . The two determination circuits, the average value determination circuit 62 and the fluctuation value determination circuit 63, detect interference waves near Fv and operate with the holding coefficient. Is provided to switch to the pull-in coefficient.

FIG. 2 shows a four-input selector circuit 61.
a, 61b, an average value judgment circuit 62, and a fluctuation value judgment circuit 63 are shown, but a combination of only the four-input selector circuits 61a, 61b and the average value judgment circuit 62, or a four-input selector circuit 61a, 61b,
It is also possible to configure as a combination of only the fluctuation value determination circuit 63. In this case, the 4-input selector circuit 61
a, 61b, when selecting a signal from the fixed-value multiplication circuit, a first coefficient selection signal from the second threshold circuit 49 indicating whether or not the pull-in operation has been completed; And a detection signal from the carrier circuit 10 indicating whether or not the signal has been detected, and a second or third coefficient selection signal output from the average value determination circuit 62 or the variation value determination circuit 63. It becomes a three-input selector circuit that operates.

As shown in FIG. 2, four-input selector circuits 61a and 61b and average value determination circuit 62
In the configuration in which the variation value determination circuit 63 is provided, the four-input selector circuits 61a and 61b may perform the selection operation by using either the output of the average value determination circuit 62 or the output of the variation value determination circuit 63. .

Next, the respective parts of the NCO circuit 73 will be described. They are added and output. The second ± π
The conversion circuit 57 converts the signal φ output from the third adder 56 into
φ such that φ = φ0 + 2πn (where n is an integer)
0 (-π <φ0 <π) and output.

The second latch circuit 58 latches the signal output from the second ± π conversion circuit 57, feeds it back to the third adder 56 and outputs it, and subtracts the phase It is also output to the unit 42. Further, the second latch circuit 58 uses the latched signal as a phase value,
This is output to the COS circuit 59 and the SIN circuit 60.

The COS circuit 59 includes a second latch circuit 58
And generates a signal corresponding to the cosine of the phase value input from the controller, and outputs the signal as an in-phase component of the reproduced carrier signal. Further, the SIN circuit 60 includes a second latch circuit 58
And generates a signal corresponding to the sine of the phase value input from, and outputs it as a quadrature component of the reproduced carrier signal. The COS circuit 59 and the SIN circuit 60 can be realized by a ROM or the like, similarly to the arc tangent circuit 41.

That is, the NCO circuit 73 includes the integrating means 72
The NCO control signal output by the second adder 54 is integrated by the third adder 56, the second ± π conversion circuit 58, and the second latch circuit 58, and the phase error output by the phase comparison means 71 A feedback operation is performed so that the signal converges to zero. Also, based on the result of the integration, the COS circuit 59
And the SIN circuit 60 output the in-phase component and the quadrature component of the reproduced carrier signal, respectively.

The feedback operation of the NCO circuit 73 has an effect that a reproduced carrier signal can be generated stably.

As a whole, according to the digital PLL circuit as shown in FIG. 2, the accuracy of the carrier signal to be reproduced can be improved, and the amplitude of the input carrier signal decreases or disappears. Also, there is an effect that the reproduced carrier signal can be continuously output. When an interference wave is detected in the vicinity of Fv according to a detection signal indicating whether or not an interference wave is detected in the vicinity of the video carrier frequency Fv,
Since it is determined whether the signal is to be pulled in or held in accordance with the state of the signal before it without following the interference wave, there is an effect that the reproduced carrier signal can be stably output. Therefore, according to the carrier synchronization circuit 20 having such a digital PLL circuit shown in FIG. 1, there is an effect that a highly accurate reproduced carrier signal can be continuously output.

Next, the operation of the digital quadrature demodulation circuit shown in FIG. 1 will be described. Input from the antenna,
The received signal including the interference wave is amplified to an appropriate level, and R
The signal is input to the multiplier 11 as an F signal. Then, the multiplier 11 multiplies the RF signal by the local oscillation signal input from the VCO 29 of the carrier synchronization circuit 20, and outputs the product.
The circuit 12 removes an image component and an unnecessary band component generated by the frequency conversion in the multiplier 11 and
Output as a signal.

If the sampling frequency of the IF signal is 28.63636 MHz (eight times the color subcarrier frequency of the NTSC signal), for example, the video carrier frequency is 7.1580, which is 1/4 of the sampling frequency.
An IF signal of 9 MHz (twice the color subcarrier frequency of the NTSC signal) is obtained.

Then, the A / D conversion circuit 13
At a clock frequency of 8.63636 MHz, the IF signal as an analog signal is converted into a digital IF signal, and the step Nyquist filter circuit 14 generates a video carrier frequency ± 1.25 corresponding to a double sideband signal of the NTSC modulated wave.
The signal component in the MHz frequency domain is reduced by 6 dB as compared with the signal component in the SSB domain.

Then, the quasi-synchronous detection circuit 15 converts the signal input from the step Nyquist
The S signal and the -SIN signal are subjected to quadrature demodulation as local oscillation signals to generate a complex baseband signal, which is separated into an in-phase component and a quadrature component and output. Each component of the complex baseband signal is a corresponding first L
The PF circuit 16 removes an image component generated due to the quadrature demodulation, and the corresponding first down-sampling circuit 1
7, the sampling frequency is set to 14.318, for example.
18 MHz (four times the color subcarrier frequency of the NTSC signal)
The carrier signal is then delayed by the corresponding delay circuit 18 by the delay generated by the carrier synchronization circuit 20 to generate the reproduced carrier signal, and output to the phase rotation circuit 19.

On the other hand, each component of the signal output from the down-sampling circuit 17 is assigned to the corresponding second LPF circuit 2.
1, only the components in the vicinity of the video carrier frequency are taken out, the band is limited so that aliasing distortion does not occur in the next down-sampling process, and the complex limiter circuit 2
3 converts the signal into a complex baseband signal having a constant amplitude.

Then, the components of the complex baseband signal, which have been converted into the constant amplitude, are further removed by the corresponding third LPF circuit 24 from the components other than the video carrier component, and are output as carrier signals. The carrier signal is output as a continuous and stable reproduced carrier signal by the operation of the digital PLL circuit 25. The signal of each component of the in-phase component and the quadrature component of the reproduced carrier signal is converted into a corresponding up-sampled signal. The signal of “0” is interpolated by the circuit 26, for example,
The signal is converted into a four-fold sampling frequency of 14.31818 MHz, output, and further interpolated by the corresponding fourth LPF circuit 27, and output to the phase rotation circuit 19 as a reproduced carrier signal.

Then, the phase rotation circuit 19
8 corrects the frequency phase error of each component of the in-phase component and the quadrature component of the complex baseband signal using the signal of each component of the in-phase component and the quadrature component of the reproduced carrier signal, and generates a completely synchronous detection signal. The in-phase component and the quadrature component of the complex baseband signal are output.

On the other hand, the frequency error signal (the video carrier frequency of the IF signal,
After the high frequency is removed by the loop filter circuit 28 from the frequency of the difference from 7.15809 MHz (twice the NTSC signal color subcarrier frequency), the VCO 29
As a control signal, and adjusts the local oscillation signal output from the VCO 29 so that the frequency of the IF signal is accurately 7.158.
09 MHz (twice the color subcarrier frequency of the NTSC signal)
So that

Digital PLL according to an embodiment of the present invention
If the circuit 25 is used for a digital quadrature demodulation circuit, even if a radio wave or the like is mixed in the RF signal and the carrier signal extracted from the RF signal is deteriorated or lost, the digital PLL circuit 2
5 and the function of the carrier synchronizing circuit 20 using the same, it is possible to continuously obtain a high-precision and stable reproduced carrier signal, correct the frequency phase error of the quasi-synchronous detected signal, and obtain a stable perfect synchronization. There is an effect that a detection signal can be output.

Further, as shown by a broken line in FIG. 1, a completely synchronous detection signal output by the digital quadrature demodulation circuit is provided at a stage subsequent to the digital quadrature demodulation circuit using the digital PLL circuit 25 according to the embodiment of the present invention. A complex circuit performs complex FFT processing on the signals of the in-phase component and the quadrature component, detects the frequency and level of the interference wave, and adaptively cancels the interference wave component by a Hilbert transform / adaptive filter circuit or the like. If provided, an interference wave removing device can be provided. According to such an interference wave removing device,
Since the interference wave is detected and removed based on the perfect synchronous detection signal generated based on the highly accurate reproduced carrier signal, the interference wave can be accurately removed and an output video signal with less image quality deterioration can be obtained. There is.

In the digital quadrature demodulation circuit according to the embodiment of the present invention, the case where the carrier signal is a complex carrier signal having an in-phase component and a quadrature component has been described. Can be similarly performed.

In particular, according to the digital PLL circuit 25 of the present invention, when the interference wave component which cannot be completely removed by the LPF circuits 24a and 24b is unavoidably input to the digital PLL circuit 25, that is, when it is in the vicinity of the video carrier frequency Fv, When the interference wave is generated, the holding coefficient is selected, so that the tracking of the interference wave component can be reduced.
Also, in the present invention, Fv
Is automatically switched to the pull-in coefficient automatically even if the phase is discontinuous or the digital PLL circuit is out of phase due to some problem. Therefore, it is necessary to input a stable reproduced carrier signal to the phase rotation circuit 19. Is possible, and there is an effect of preventing deterioration of video quality.

[0109]

According to the present invention, the phase error between the extracted complex carrier signal and the reproduced complex carrier signal is determined, and when the interference wave exists near the frequency of the extracted complex carrier signal, the locked state is determined. Judge whether or not the lock is completed.If the lock state is completed, multiply the phase error by the holding coefficient and output.If the lock state is not completed, multiply the phase error by the pull-in coefficient. And output it, and from the output phase error after coefficient multiplication,
Since the digital PLL circuit and the phase synchronization method for reproducing and outputting the complex carrier signal are used, whether the locked state is completed instead of switching between holding and pulling based on the extracted complex carrier signal that has deteriorated due to the inclusion of the interference wave By switching between holding and pulling in according to whether or not, it is possible to stably generate a highly accurate reproduced carrier signal.

The present invention for solving the above-mentioned problems of the prior art is characterized in that an integrating means for outputting a frequency error signal and a control signal for generating a reproduced carrier signal from a phase error includes first to fourth fixed signals. The value multiplication circuit multiplies the phase error signal by the direct term coefficient at the time of pull-in, the direct term coefficient at the time of holding, the integral term coefficient at the time of pull-in, and the integral term coefficient at the time of holding, respectively. Calculate the average value of the signal obtained by multiplying the phase error signal by the direct term coefficient at the time of pull-in or the direct term coefficient at the time of holding, and calculate the absolute value of the average value for a certain period,
Determine whether the locked state is completed from the absolute value,
A fluctuation value judgment circuit calculates a fluctuation value of the integrated signal of the signal obtained by multiplying the phase error signal by the integration term coefficient at the time of pull-in or the integration term coefficient at the time of holding, and determines whether the lock state is completed from the fluctuation value. When the first selector circuit determines that the interference signal is detected near the video carrier frequency by the first selector circuit, the determination result of the average value determination circuit or the fluctuation When the locked state is completed according to the determination result of the value determination circuit or both, the signal from the second fixed value multiplication circuit is selected and output as the holding operation, and the locked state is not completed. In this case, a signal from the first fixed value multiplying circuit is selected and output as a pull-in operation, and a detection signal input from the outside is detected by the second selector circuit as an interference wave near the video carrier frequency. If the meaning that is, the determination of the determination result or variation value judgment circuit of the average value judgment circuit results,
Alternatively, in accordance with both, when the lock state is completed, the signal from the fourth fixed value multiplication circuit is selected and output as the holding operation, and when the lock state is not completed, it is determined as the pull-in operation. A signal from the second fixed value multiplication circuit is selected and output, an integration circuit integrates a signal output from the second selector circuit, and a second adder integrates with a signal output from the first selector circuit. The signal integrated by the circuit is added and the result is output as a control signal.Therefore, instead of switching between holding and pulling based on the extracted complex carrier signal that has deteriorated due to interference waves, the result of the judgment by the average value judgment circuit Alternatively, by switching between holding and pulling in based on whether or not the lock state has been completed, based on the determination result of the fluctuation value determination circuit or both, a stable and highly accurate reproduced carrier is obtained. No. it can generate.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a quadrature demodulation circuit according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram illustrating an example of a digital PLL circuit.

FIG. 3 is a configuration block diagram illustrating an example of a conventional orthogonal demodulation circuit.

[Explanation of symbols]

1. IF signal conversion means 2. A / D conversion means 3.
Local oscillation signal generation means, 4 ... quasi-synchronous detection means, 5 ... complex carrier signal extraction means, 6 ... correction means, 11 ... multiplier, 12 ... BPF circuit, 13 ... A / D conversion circuit,
14: step Nyquist filter circuit, 15: quasi-synchronous detection circuit, 16: first LPF circuit, 17: first
18: delay circuit, 19: phase rotation circuit, 20: carrier synchronization circuit, 21: second
LPF circuit of 22 ... second down-sampling circuit,
23: complex limiter circuit, 24: third LPF circuit,
25: Digital PLL circuit, 26: Up sampling circuit, 27: Fourth LPF circuit, 28: Loop filter circuit, 29: VCO circuit, 41: Arc tangent circuit,
42: subtracter, 43: first ± π conversion circuit, 44: zero data circuit, 45: absolute value circuit, 46: first threshold circuit, 47: first selector circuit, 48 ...
A fixed value multiplication circuit, 49 ... a second threshold circuit,
51: first adder, 52: clipping circuit, 53:
A first latch circuit, 54... A second adder, 55.
/ A conversion circuit, 56: third adder, 57: second ± π conversion circuit, 58: second latch circuit, 59: CO
S circuit, 60 SIN circuit, 61a 4-input selector circuit, 61b 4-input selector circuit, 62 average value judgment circuit, 63 fluctuation value judgment circuit, 71 phase comparison means, 72 integration means, 73 NCO circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 27/38 H03L 7/08 B H04N 5/455 H04L 27/00 HF Term (Reference) 5C025 AA14 AA16 AA17 AA18 5J106 AA05 BB04 CC01 CC21 CC41 CC58 DD02 DD04 DD09 DD12 DD13 DD35 DD42 EE10 GG07 HH08 JJ04 KK05 5K004 AA05 AA08 FG02 FJ17 FK09 FK14 FK16 JG01 JJ13 5K047 AA03 AA13 CC08 DD02 EE02 MM02 MM02 EE02

Claims (6)

[Claims] 1. A digital PLL circuit that locks to a phase of a complex carrier signal extracted from a complex baseband signal and continuously reproduces and outputs the complex carrier signal at the locked phase. The phase error between the complex carrier signal and the reproduced complex carrier signal is obtained, and if an interference wave exists near the frequency of the extracted complex carrier signal, it is determined whether or not the locked state is completed. If the phase error is completed, the phase error is multiplied by a holding coefficient and output. If the lock state is not completed, the phase error is switched by multiplying by a pull-in coefficient and output. Digital PLL for reproducing and outputting a complex carrier signal from a phase error after coefficient multiplication
circuit. 2. A digital PLL circuit that locks to a phase of a complex carrier signal extracted from a complex baseband signal, and continuously reproduces and outputs a complex carrier signal at the locked phase. A complex carrier signal, phase comparing means for outputting a phase error between the reproduced complex carrier signal, and an integrating means for outputting a frequency error signal and a control signal for generating a reproduced carrier signal from the phase error; The phase of the complex carrier signal is generated based on the control signal output by the integration means, and the complex carrier signal is reproduced and output from the phase, and the phase of the reproduced complex carrier signal is fed back to the phase comparison means. Oscillating means for outputting, wherein the phase comparing means is an input complex carrier signal;
A phase error with the reproduced complex carrier signal is calculated and output as a detected phase error signal. When the amplitude of the input complex carrier signal becomes smaller than a predetermined value, the detected phase error signal is forcibly applied. Phase comparing means for outputting a phase error signal as zero data indicating that there is no phase difference, wherein the integrating means is configured to lock the lock state when an interference wave exists near the frequency of the extracted complex carrier signal. It is determined whether or not the phase error has been completed. If the locked state has been completed, a holding operation of multiplying the phase error by a holding coefficient and outputting the result is performed. Is switched to perform a pull-in operation of multiplying by a pull-in coefficient and outputting a frequency error signal and a reproduced carrier signal from the output phase error after coefficient multiplication. A digital PLL circuit, which is an integrating means for outputting a control signal for performing the operation. 3. The integration means includes: a phase error signal output from the phase comparison means, a direct term coefficient during pull-in, a direct term coefficient during hold, an integral term coefficient during pull-in, and an integral term coefficient during hold. The first to multiply by
To a fourth fixed value multiplying circuit, calculating an average value of a signal obtained by multiplying the phase error signal by a direct term coefficient at the time of pull-in or a direct term coefficient at the time of holding, and calculating an absolute value of the average value, An average value determination circuit for determining whether or not the lock state is completed from the absolute value, and when a detection signal input from the outside means that an interference wave is detected in the vicinity of the video carrier frequency, According to the determination result of the average value determination circuit, when the lock state is completed, the signal from the second fixed value multiplication circuit is selected and output as the holding operation, and when the lock state is not completed. The first selector circuit selects and outputs a signal from the first fixed-value multiplication circuit as a pull-in operation, and the detection signal input from the outside has an interference wave detected near the video carrier frequency. In the meaning, when the locked state is completed according to the determination result of the average value determining circuit, the signal from the fourth fixed value multiplying circuit is selected and output as the holding operation, and the locked state is completed. If not, a second selector circuit that selects and outputs a signal from the second fixed value multiplication circuit as a pull-in operation, an integration circuit that integrates a signal output by the second selector circuit, 3. An integrating means comprising a second adder for adding a signal output from the first selector circuit and a signal integrated by the integrating circuit and outputting the added signal as a control signal. Digital PLL circuit. 4. The integration means includes: a phase error signal output from the phase comparison means, a direct term coefficient during pull-in, a direct term coefficient during hold, an integral term coefficient during pull-in, and an integral term coefficient during hold. The first to multiply by
To a fourth fixed value multiplying circuit, and calculates a fluctuation value of an integrated signal of a signal obtained by multiplying the phase error signal by an integration term coefficient at the time of pull-in or an integration term coefficient at the time of holding, and locks from the fluctuation value A fluctuation value determining circuit for determining whether or not the state is completed; and a fluctuation value determining circuit when a detection signal input from the outside means that an interference wave is detected near a video carrier frequency. According to the judgment result, when the lock state is completed, the signal from the second fixed value multiplication circuit is selected and output as the holding operation, and when the lock state is not completed, it is determined as the pull-in operation. A first selector circuit for selecting and outputting a signal from the first fixed-value multiplication circuit; and a first selector circuit for detecting that an interference signal is detected near an image carrier frequency when a detection signal input from the outside is detected. According to the determination result of the fluctuation value determination circuit, when the lock state is completed, a signal from the fourth fixed value multiplication circuit is selected and output as a holding operation, and the lock state is not completed. In this case, as a pull-in operation, a second selector circuit that selects and outputs a signal from a second fixed value multiplication circuit, an integration circuit that integrates a signal output by the second selector circuit, 3. A digital PLL according to claim 2, further comprising a second adder for adding a signal output from said selector circuit and a signal integrated by said integration circuit, and outputting the added signal as a control signal. circuit. 5. The integrating means includes: a phase error signal output by the phase comparing means, a direct term coefficient at the time of pull-in, a direct term coefficient at the time of holding, an integral term coefficient at the time of pull-in, and an integral term coefficient at the time of holding The first to multiply by
To a fourth fixed value multiplying circuit, calculating an average value of a signal obtained by multiplying the phase error signal by a direct term coefficient at the time of pull-in or a direct term coefficient at the time of holding, and calculating an absolute value of the average value, An average value determination circuit that determines whether or not the locked state is completed based on the absolute value; and a fixed time period related to an integrated signal of a signal obtained by multiplying the phase error signal by an integration term coefficient during pull-in or an integration term coefficient during holding. And a fluctuation value determination circuit that determines whether or not the lock state is completed based on the fluctuation value, and a detection signal input from the outside detects an interference wave near the video carrier frequency. If the lock state is completed according to the determination result of the average value determination circuit or the determination result of the fluctuation value determination circuit, or both, the second fixed value A first selector circuit for selecting and outputting a signal from the arithmetic circuit and, when the lock state is not completed, selecting and outputting a signal from the first fixed value multiplication circuit as a pull-in operation; When the detection signal input from means that the interference wave is detected in the vicinity of the video carrier frequency, according to the determination result of the average value determination circuit or the determination result of the fluctuation value determination circuit, or both, When the lock state is completed, the signal from the fourth fixed value multiplication circuit is selected and output as the holding operation, and when the lock state is not completed, the second fixed value is processed as the pull-in operation. A second selector circuit for selecting and outputting a signal from a multiplying circuit; an integrating circuit for integrating a signal output from the second selector circuit; a signal output from the first selector circuit and the product Digital PLL circuit according to claim 2, wherein the adding the signals integrated by the circuit is the integral means and a second adder for outputting as a control signal. 6. A phase error between an extracted complex carrier signal and a reproduced complex carrier signal is obtained, and when there is no interference wave near the frequency of the extracted complex carrier signal, a direct error when pulling in the phase error is obtained. The absolute value of the average value of the signal obtained by multiplying the term coefficient or the direct term coefficient at the holding time during a certain period, or the absolute value of the integrated value of the signal obtained by multiplying the phase error by the integration coefficient at the time of attraction or the integration coefficient at the holding time It is determined whether or not the locked state is completed based on the fluctuation value or both, and if the result of the determination is that the locked state is completed, the phase error is multiplied by a holding coefficient and output by holding. Perform the operation, if the lock state is not completed, switch to perform a pull-in operation of multiplying the phase error by a pull-in coefficient and output, and check whether the output phase error after the coefficient multiplication. A phase synchronization method characterized by continuously reproducing a complex carrier signal.