KR100463507B1 - HDIVETI's Timing Northern Equipment - Google Patents

Abstract

An HDC apparatus includes an interpolator for interpolating and outputting demodulated data according to correction information, and a quad filter for sampling and outputting a signal output from the interpolator with an enable signal according to the synchronization signal. And a sampler for outputting a timing error signal with the symmetry of the signal output from the quad filter, a loop filter for loop filtering the error signal output from the sampler, and outputting a timing error feedback signal, and a timing output from the loop filter. It is composed of a numerically controlled oscillator that outputs interpolation correction information of the interpolator according to the error trace signal, so that the performance of both functions can be reliably separated while performing both demodulation and timing restoration of signals in the digital domain. This has an easy effect.

Description

HDIVETI's Timing Recovery Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to HTV receiver systems, and more particularly, to an apparatus for recovering timing of digital signals.

VSB (Vestigial SideBand) transmission technology, determined by the US DTV standard, is currently developed using an analog demodulation circuit.

The configuration of a receiver that demodulates a VSB signal by adopting such an analog circuit will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a reception system of a digital broadcast signal according to an embodiment of the prior art. The reception system for demodulating a VSB in analog mode includes a tuner 11 and a surface acoustic wave (SAW) filter ( 12), an IF (Intermediate Frequency) amplifier 13, an analog VSB demodulator 14 comprising a multiplier, a filter, a limiter, etc., an A / D (Analog / Digital) converter 15, and a timing recovery device ( 10) and a synchronization signal recovery unit 15.

The timing recovery apparatus 10 includes a quad filter 17, a sampler 18, a loop filter 19, and a voltage controlled crystal oscillator (VCXO) 20.

The conventional digital broadcasting signal receiving system configured as described above receives the signal received through the antenna to the tuner 11, filters the SAW filter 12, and then converts the IF amplifier 13 into an intermediate frequency.

The analog VSB demodulator 14 demodulates this intermediate frequency, outputs it to the A / D converter 15, and converts it into a digital signal through the A / D converter 15. FIG.

The synchronizing signal recovery unit 16 detects the position of the segment synchronizing signal from the digital signal output from the A / D converter 15 and outputs it to the timing recovery apparatus 10.

The quad filter 17 of the timing restoring apparatus 10 receives the enable signal from the sync signal recovery unit 15 in the position period of the segment sync signal, and samples the signal output from the A / D converter 15. Output to the sampler 10.

The sampler 10 receives the enable signal from the sync signal recovery unit 15 in the position period of the segment sync signal, detects the phase of the signal output from the quad filter 17, detects the symmetry, and outputs an error signal.

The loop filter 19 loop-filters the error signal, obtains an average, and outputs the corresponding voltage to the VCXO 20. The VCXO 20 converts the frequency corresponding to the voltage output from the loop filter 19 into A / D conversion. Output to section 15.

When demodulating a VSB signal in a receiving system that demodulates a VSB with such an analog, it is difficult to generate a carrier that maintains an exact 90 ° phase at a receiving end, and the analog VSB demodulator 14 and subsequent digital signals at the receiving end have high density. There is a problem that a high cost is required to integrate a single IC into an integrated circuit.

Therefore, as a solution to this, the intermediate frequency signal is lowered to a frequency where a commercial A / D converter can be used, and then digitalized to demodulate in the digital domain.

The receiving end thereof includes a tuner 21, a SAW filter 22, an IF amplifier 23, an A / D converter 25, a quad filter 28, a sampler 29, and a loop filter ( 30 and the synchronization signal recovery unit 27 and the VCXO 24, which are the same as those in FIG. 1, except that the digital demodulation unit 26 is placed behind the A / D conversion unit 25.

The digital demodulator 26 demodulates the signal at the timing of conversion by the A / D converter 25.

In addition, since the timing signal for A / D conversion is detected from the demodulated signal, the timing recovery and the VSB signal demodulation are entangled with each other to influence each other.

Therefore, since the timing recovery loop surrounds the digital demodulator 26, a large amount of time is required to detect and converge the signal, and thus, both the signal demodulation and the timing recovery are performed in the digital domain, resulting in unstable signal detection. do.

Disclosure of Invention The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide an HTI-based timing recovery apparatus that can stably detect signals while performing both demodulation and timing restoration of signals in a digital region.

In order to achieve the above object, a characteristic of an HTV-based timing recovery apparatus is to extract interpolation correction information according to a timing error feedback signal to perform timing shift of an input signal.

Hereinafter, an HTI timing recovery apparatus according to the present invention will be described with reference to the restored drawings.

3 is a block diagram for explaining the configuration of a timing recovery apparatus in a digital broadcast signal receiving system according to the present invention. The tuner 21, the SAW filter 22, the IF amplifier 23, and the mixer 24 are shown in FIG. And the A / D converter 25 and the digital demodulator 26 are the same as in the prior art, and the timing recovery apparatus of the digital broadcast signal reception system according to the present invention is a digital demodulator 26 according to the corrected new information. The interpolator 301 interpolates and demodulates the demodulated data, and the quad filter 302 samples and outputs the signal output from the interpolator 301 according to the enable signal output from the synchronization signal recovery unit 27. And a sampler 303 for outputting a timing error signal with the symmetry of the signal output from the quad filter 302, and a loop error filtering of the error signal output from the sampler 303 to output a timing error feedback signal ε _R. Loop filter 304 and loop filter 304 NCO (Numerically Controlled Oscillator) 305 for outputting interpolation correction information (μ _R ) of the interpolator 301 according to the timing error feedback signal (ε _R ) output from 306.

Referring to the accompanying drawings, the operation of the timing recovery apparatus of the HTV is configured as follows.

4 is a view for explaining the configuration of the NCO of Figure 3, Figure 5 is a view for explaining the operation of the interpolator of Figure 3, Figure 6 is a waveform diagram for explaining the operation of the NCO of FIG.

First, the A / D converter 25 converts an analog signal output from the mixer 24 into a digital signal according to a predetermined frequency of the clock oscillator 306 and outputs the digital signal to the digital demodulator 26.

The digital demodulator 26 outputs the input digital signal to the interpolator 301 to demodulate the input digital signal, and the interpolated signal from the interpolator 301 is input to the quad filter 302 and sampled.

The sampler 303 outputs a timing error signal to the loop filter 304 with the symmetry of the sampled signal input from the fraud quad filter 302, and the loop filter 304 outputs the error signal output from the sampler 303. Loop filtering to output a timing error feedback signal ε _R to the NCO 305.

The loop filter 304 and the sampler 303 are enabled at the position of the segment sync signal detected by the sync signal recovery unit 27.

4, the first multiplier 351 determines the gain control constant K _N of the NCO 305 and the timing error feedback signal ε _R output from the loop filter 304. Then multiply this by the result and add it to the center frequency of the NCO in the first adder 352.

The second adder 352 adds this result and the result fed back from the modular N 354 and outputs the result to the modular N 354 again, and the signal output from the modular N 354 is quantized to fit the interpolator 301. To output the interpolator correction information (μ _R ).

The interpolator 301 receiving the interpolation correction information μ _R operates as shown in FIG. 5.

That is, the filter coefficients C ₀ to C _n corresponding to the interpolation correction information μ _R are output by the look-up table LUT, and the respective coefficients and delayed data output from the digital demodulator 26 are output. Multiply them and add them all.

If the timing error feedback signal output from the loop filter 304 is 0, the interpolation correction information μ _R becomes 0 as shown in FIG.

In other words, there is no timing shift in the result of the interpolation.

If the timing error feedback signal output from the loop filter 304 is not 0, as shown in FIG. 6 (b), the interpolation correction information μ _R is not 0, and the timing shift of the input signal occurs due to interpolation to restore timing. Perform.

The interpolation correction information μ _R may be a continuous value. In this case, the resolution is adjusted by the quantizer 355 of FIG.

The HDT timing recovery apparatus according to the present invention can reliably separate the performance of the two functions while performing both demodulation and timing restoration of the signal in the digital domain, thereby making it easy to detect a stable signal.

1 is a block diagram illustrating a configuration of a system for receiving a digital broadcast signal according to an embodiment of the prior art.

2 is a block diagram illustrating a configuration of a system for receiving a digital broadcast signal in another embodiment according to the prior art;

3 is a block diagram illustrating a configuration of a timing recovery apparatus in a system for receiving a digital broadcast signal according to the present invention.

4 is a view for explaining the configuration of the NCO of FIG.

5 is a view for explaining the operation of the interpolator of FIG.

6 is a waveform diagram illustrating the operation of the NCO of FIG. 3.

* Explanation of symbols for main parts of the drawings

21: tuner 22: SAW filter

23: IF amplifier 24: blender

25: A / D conversion section 26: digital demodulation section

27: synchronization signal recovery unit 301: interpolator

302: quad filter 303: sampler

304: loop filter 305: NCO

306: clock oscillator

Claims (1)

An interpolator for interpolating and outputting the demodulated data received according to the correction information; A quad filter configured to sample and output a signal output from the interpolator as an enable signal according to the synchronization signal; A sampler for outputting a timing error signal with symmetry of the signal output from the quad filter; A loop filter for loop filtering the error signal output from the sampler and outputting a timing error feedback signal; And a numerically controlled oscillator for outputting interpolation correction information of the interpolator according to the timing error trace signal output from the loop filter.

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