KR960010494B1 - Hdtv receiver - Google Patents

Abstract

a decoder for decoding a difference signal between a predetermined frequency signal and the first medium frequency signal of a local oscillator through the first medium frequency amplifier, an SAW filter, and the second medium frequency amplifier, and converting the decoded signal into digital signal via an A/D converter; the first sampling means; and the second sampling means.

Description

HDTV receiver

1 is a schematic block diagram showing a conventional HDTV receiver.

2 is a detailed block diagram showing a conventional HDTV receiver.

Figure 3 is a detailed block diagram showing an embodiment of the present invention.

4 is a detailed block diagram showing another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

20,60: Local Oscillator 21,61: Mixer

22,24,62,64: Medium frequency amplifier 23,63: SAW filter

33: Data segment sync signal detector 34: Confidence counter

36: AGC generator 40,65: A / D converter

41,66: NCO 42,47,50,67,72,75: Multiplier

43,45,48,51,68,70,73,76: Low pass filter 44,49,69,74: Sampler

46,71: limiter 52,77: PLL

53: clock generator 78: divider

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to HDTV (High Definition TV), and more particularly, to a receiver for digitally processing demodulation of a TV signal received through an antenna and a frequency phase locked loop (FPLL).

1 is a schematic block diagram showing a conventional HDTV receiver, which will be described below.

First, the TV signal received through the antenna (1) occupies a frequency band of 54MHz to 800MHz according to the channel, which is demodulated by the demodulator 2 and converted to a primary intermediate frequency of 920MHz.

The demodulator 3 automatically amplifies the 920 MHz signal with an AGC (Automatic Gain Control) signal, adjusts the frequency with an AFC (Automatic Frequency Control) signal, and then converts it into a second intermediate frequency of 44 MHz. The SAM (Surface Acoustic Wave) filter 4 having a passband of 5.38 MHz receives the 44 MHz signal of the demodulator 3 and band-filters the passband of 5.38 MHz around 44 MHz, and the demodulator 5 This is demodulated to a base band and output.

The FPLL unit 6 receives the output of the demodulator 5, transmits an AFC signal to the demodulator 3 according to the frequency and phase, and an A / D (Analog / Digital) converter 7 converts the FPLL ( The output signal of 6) is converted to digital output and the data segment clock recovery (8) outputs the data segment synchronization signal (corresponding to the horizontal synchronization signal in NTSC) to the output of the A / D converter 7. By detecting and adjusting the sampling time of the A / D converter 7 to the position of the segment synchronization signal, the AGC control signal is generated to the demodulation unit 3 and 5 by generating the AGC control signal with the size of the segment synchronization signal.

When the data segment synchronization signal is found, the data field synchronization signal recovery 9 detects the data field synchronization signal (corresponding to the vertical synchronization signal in NTSC), and also searches whether the signal has NTSC interference.

If there is NTSC interference, operate the NTSC interference canceling Post Combfilter 10, post coder 14 bypasses, and if no NTSC interference postcom filter 10 bypasses. And the post coder 14 is operated.

The output of the post comb filter 10 removes ghosts caused by multipaths occurring on the channel with the help of the controller 12 in the channel equalizer 11.

A slice demapper 13 detects 4-level and 2-level signals, which are the original signal levels, at the output of the channel equalizer 11, and the post coder 14 performs the coding performed at the transmitting end of the HDTV. The deinterleaver 15 performs the reverse coding, that is, decoding on the HDTV, and the deinterleaver 15 releases the interference performed by the transmitting end of the HDTV and restores the original signal format. The error correction unit 16 also corrects the error by R-S decoding the output of the deinterleaver 15.

FIG. 2 is a detailed block diagram showing the HDTV receiver of FIG. 1 in detail.

First, the mixer 21 receives a signal loaded on the primary intermediate frequency of 920 MHz and a signal of 876 ± 0.3 MHz output from the local oscillator 20 and outputs a second intermediate frequency of 44 MHz, which is the difference between the two frequencies. The amplification part 22 amplifies, and the SAW filter 23 passes only the residual sideband modulation (VSB) signal centered at 44 MHz.

The intermediate frequency amplifier 24 amplifies to compensate for in-section loss occurring during the filtering of the SAW filter 23 while receiving an AGC signal to perform automatic gain adjustment.

In FIG. 2, the multiplier 25, the AFC low pass filter 26, the limiter 27, the multiplier 28, the automatic phase control low pass filter 29, and the local oscillator 20 are shown. Is a configuration for automatic frequency adjustment, the multiplier 30, the multiplexer 28 and the APC low pass filter 29 and the local oscillator 20 is configured for automatic phase adjustment, the multiplier 25 and the multiplexer 30 Is to synchronize the frequency and phase of the reference local oscillator 31 with the input frequency and phase. At this time, the AFC low pass filter 26 has a characteristic that the phase is close to -90 ° if the frequency of the input signal is shifted by -Δf, and the phase is close to -90 ° if the frequency is shifted by + △ f. The limiter 27 has a characteristic that the signal is +1 when the signal is greater than 0 and -1 when the signal is smaller than 0.

Therefore, if the frequency of the input signal is shifted in the positive direction, the output of the limiter 27 is 90 ° -90 ° = 0, compared to the output of the multiplier 30, resulting in a phase difference of the multiplier 28. The output is always positive.

When this is passed through the APC low pass filter 29, a positive large voltage is output to adjust the frequency of the local oscillator 20 so that the frequencies of the two signals input to the multipliers 25 and 30 coincide.

In addition, when the frequency of the input signal is lower than the frequency of the reference local oscillator 31, the output of the limiter 27 generates a phase difference of 90 ° + 90 ° = 180 ° so that the output of the multiplier 28 is always negative (−). )

Therefore, the APC low pass filter 29 outputs a large negative voltage to adjust the frequency of the local oscillator 20 in the opposite direction so that the two input frequencies of the mixers 25 and 30 coincide.

As a result, if the frequencies coincide, only the multiplexers 30 and 28, the APC low pass filter 29 and the local oscillator 20 operate, which is the same as the PLL role.

The signal whose frequency and phase are locked is digitally converted by the A / D converter 32 having a sampling frequency of 10.76 MHz and transmitted to the post comb filter 20 (FIG. 1), and the data segment synchronization signal detector ( 33 detects a data segment synchronization signal from the output of the A / D converter 32, and a confidence counter 34 is a data segment synchronization signal occupying the first four symbols of every transmission line. Is detected in the line direction and the PLL unit 35 is operated based on the detected synchronization signal after detecting a data segment synchronization signal having a good S / N ratio, thereby generating a 75 MHz clock and detecting the detected data. The AGC generator 36 generates an AGC control signal using the magnitude of the segment synchronization signal.

At this time, a sampling frequency of 10.76 MHz of the A / D converter 32 is generated by dividing the output of the PLL unit 35 by the divider 37.

However, in the conventional HDTV receiver, the video signal is pulled down to the baseband and then sampled. Therefore, during demodulation, an error due to the nonlinearity of the mixer and the inaccuracy of the phase occurs, and the DC offset generated during the baseband signal processing ( off-set), power and low frequency noise are easy to occur, and it is difficult to ideally implement an analog low pass filter. The present invention has been made to solve the above problems, by digitally sampling the second intermediate frequency, digitally demodulating and FPLL to remove DC offset power and low frequency noise, resulting in nonlinearity and phase inaccuracy of the mixer It is an object of the present invention to provide an HDTV receiver that eliminates errors and improves S / N ratio by digital filtering.

A feature of an HTV receiver according to the present invention for achieving the above object is a first intermediate frequency amplifier, a SAW filter, and a second intermediate signal of a difference signal between a constant frequency signal and a first intermediate frequency signal of a local oscillator. Demodulation means for outputting the modulated signal of the current sideband through the frequency amplifier, and then converting the signal into a digital signal by the A / D converter; and another signal wave having a 90 ° phase difference provided from the output signal of the demodulation means and the NCO. After multiplying by low pass filtering, first sampling means for outputting the down-sampled signal, and sampling the output of the first sampling means according to a predetermined frequency clock of the PLL, and then down-sampling with the output signal of the demodulation means It is a point comprised by the 2nd sampling means to output.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

Figure 3 is a block diagram showing an embodiment of the present invention, the A / D converter 40 for sampling the output of the intermediate frequency amplifier 24 at 107.6MHz and digitally converted to a cosine wave of 44MHz and NCO (Numerically Controlled Oscillator) 41 for generating a sine wave, a multiplier 42 for multiplying the output of the A / D converter 40 and the cosine wave of the NCO 41, the multiplier 42 A low pass filter 43 for low pass filtering the output, a sampler 44 for down sampling the output of the low pass filter 43 to 10.76 MHz, and an output of the sampler 44 AFC low-pass filter 45 for low-pass filtering, +1 when the output of the low-pass filter 45 is (+), the limiter 46 for outputting -1 when (-), A A multiplier 47 for multiplying the output of the / D converter 40 by the sine wave output of the NCO 41, and a low pass filter for lowpass filtering the output of the multiplier 47 (48), a sampler 49 for downsampling the output of the low pass filter 48 to 10.76 MHz, a multiplier 50 for multiplying the output of the sampler 49 and the output of the multiplier 47, APC low pass filter 51 for low pass filtering the output of multiplier 50 and transmitting to local oscillator 20, PLL 52 for locking the output phase of sampler 44, PLL A clock generator 53 for generating clocks of 107.6 MHz, 10.76 MHz, and 75 MHz as the output of 52 is configured.

Operation of an embodiment of the present invention configured as described above is as follows.

First, the 44 MHz second intermediate frequency video signal output from the intermediate frequency amplifier 24 is received by the A / D converter 40 and sampled using a clock of 107.6 MHz output from the clock generator 51. The 107.6MHz clock, which is converted to digital output, is more than twice the maximum frequency centered on 44MHz and an integer multiple of 10.76MHz, the symbol ratio.

The multiplier 42 multiplies and outputs the 44 MHz cosine wave output from the NCO 41 and the output of the A / D converter 40, and the low pass filter 43 filters the sample to filter the sample. The output of the low pass filter 43 is downsampled to 10: 1 and lowered to a symbol ratio of 10.76 MHz. When the AFC low pass filter 45 receives the low pass filter and outputs the low pass filter, the limiter 46 receives and inputs it. If the signal is positive, it outputs 1;

On the other hand, the output of the A / D converter 40 and the sine wave output of the NCO 41 are multiplied in the multiplier 47, low pass filtered in the low pass filter 48 and 10.76 in the sampler 44. It is sampled at MHz and applied to the multiplier 50.

At this time, the phase difference between the output signal of the limiter 46 and the output signal of the sampler 49 is as follows.

First, the output of the multiplexer 42 outputs the frequency difference Δf between the A / D converter 40 and the output of the NCO 41, and this signal outputs the AFC low pass filter 45. As it passes, it is shifted by a certain phase by the frequency difference Δf.

That is, if the frequency difference Δf is very less than zero, the signal input by the characteristic of the AFC low pass filter 45 is shifted closer to + 90 °, and if it is larger than 0, it is shifted closer to -90 °. .

In addition, since the output of the multiplexer 42 is 90 ° ahead of the output of the multiplier 47, when the frequency difference Δf is less than 0, the output of the AFC low pass filter 45 is determined by the sampler ( When the phase difference of 90 ° + 90 ° = 180 ° occurs with respect to the output of 49) and the frequency difference Δf is very large than 0, the output of the AFC low pass filter 45 is There is no phase difference, that is, phase difference of 90 ° -90 ° = 0 ° relative to the output.

Accordingly, the output of the limiter 46 and the output of the sampler 49 are multiplied by the multiplier 50 and a negative voltage or a positive voltage is generated. When f) is less than zero, the multiplier 50 outputs a negative voltage, and as the frequency difference Δf becomes less than zero, the output of the multiplier 50 also has a larger negative voltage. As the frequency difference Δf is greater than 0, the output of the multiplier 50 also outputs a larger positive voltage.

The output of the multiplier 50 is filtered by the APC low pass filter 51 and then applied to the local oscillator 20 to adjust the frequency of the local oscillator 20.

When the output frequency of the A / D converter 40 and the output frequency of the NCO 41 coincide with each other by controlling the local oscillator 20 (Δf = 0), a signal input to the AFC low pass filter 45 Since the AFC low pass filter 45 does not shift the phase of the input signal because the frequency difference Δf is not included, the phase difference between the output of the low pass filter 45 and the output of the sampler 49 is not included. Only differs by 90 °.

In addition, the output signal of the multiplier 42 is a phase difference (ψ ₁ -ψ ₀ = ψ) between the output phase ψ ₁ of the A / D converter 40 and the output phase ψ ₀ of the NCO 41. As such, the output of the AFC low pass filter 45 has only a positive value and the limiter 46 outputs only a value of +1.

Therefore, since the multiplier 50 multiplies the output of the limiter 46 by the output of the sampling 49, it can be seen that the output value of the sampling 49 is actually applied to the APC low pass filter 51. The output of the APC low pass filter 51 is applied to the local oscillator 20 to adjust the phase of the local oscillator 20.

The PLL 52 generates a clock of 75 MHz at the output of the sampler 44, and the clock generator 53 generates a clock of 107.6 MHz, 10.76 MHz, and 75 MHz at the output of the PLL 52, respectively. A / D converter 40 and the samples 44, 49 and video decoder (not shown).

4 is another embodiment of the present invention for lowering the sampling rate of the A / D converter by lowering the secondary intermediate frequency. The local oscillator 60 outputs a signal of 890 ± 0.3 MHz, and the first intermediate frequency of 920 MHz is shown in FIG. A mixer 61 for outputting a 30 MHz signal that is a difference between the loaded signal and the 890 MHz signal of the local oscillator 60, an intermediate frequency amplifier 62 for amplifying the 30 MHz signal of the mixer 61, and the intermediate frequency amplifier 62 SAW filter 63 which passes only the residual sideband modulated signal of the 30MHz signal center outputted from the NMR, and compensates the insertion loss occurring during the filtering of the SAW filter 63, and receives the AGC signal to automatically adjust the gain. A / D converter 65 for sampling the output of the frequency amplifier 64, the intermediate frequency amplifier 64 at 75 MHz and converting it to digital, an NCO 66 for outputting a cosine wave and a sine wave of 30 MHz, and the A / D converter. The output of 65 and the cosine wave output of NCO 66 A multiplier 67, a low pass filter 68 for low pass filtering the output of the multiplier 67, and an output of the low pass filter 68 down to 7: 1 to obtain a signal having a symbol rate of 10.76 MHz. The output of the sampler 69 to output, the AFC low pass filter 70 for low pass filtering the output of the sampler 69, +1, negative (if the output of the AFC low pass filter 70 is positive) -) Low pass filtering of the output of the multiplier 72, the multiplier 72 to multiply the limiter 71 outputting -1, the output of the A / D converter 65 and the sine wave output of the NCO 66 A low pass filter 73, a sampler 74 outputting a signal having a symbol rate of 10.76 MHz by down sampling the output of the low pass filter 73 to 7: 1, the limiter 71 and the sampler ( A multiplier 75 multiplying the output of 74, an APC low pass filter 76 for outputting the output of the multiplier 75 to the local oscillator 60, and A PLL 77 that generates a 75 MHz clock as the output of the pre-sampling 69 and applies it to the A / D converter 65, and divides the output of the PLL 77 by 7 and applies it to the sampling 69 and 74. The frequency divider 78 is configured.

Operation of another embodiment of the present invention configured as described above is as follows.

First, the mixer 61 receives a 890 MHz signal output from the local oscillator 60, such as a signal loaded at the primary intermediate frequency 920 MHz, and outputs a secondary intermediate frequency of 30 MHz, which is the difference between two frequencies, and an intermediate frequency amplifier 62 Amplification, and the SAW filter 63 passes only the residual sideband modulation (USB) signal centered at 30 MHz.

The intermediate frequency amplifier 64 amplifies to compensate for the section loss occurring during the filtering of the SAW filter 63 while receiving an AGC signal to perform automatic gain adjustment.

The A / D converter 65 receives the 30 MHz second intermediate frequency video signal output from the intermediate frequency amplifier 64, samples it with a 75 MHz clock, converts it to digital, and outputs the multiplier 67. The 30MHz cosine wave output from the NCO 66 is multiplied by the output signal of the A / D converter 65, and the low pass filter 68 outputs it by low pass filtering.

The sampler 69 downsamples the output of the low pass filter 68 to 7: 1 to output a signal having a symbol rate of 10.76 MHz, and the AFC low pass filtering 70 receives the sampler 69. The output of the low-pass filter and the limiter 71 outputs a +1 value if the output of the AFC low pass filter 70 is a (+) signal, and a -1 value if the (-) signal.

On the other hand, the output of the A / D converter 65 and the sine wave output of the NCO 66 are multiplied in the multiplier 72, low pass filtered in the low pass filter 73, and 7: in the sampler 74: Downsampled to 1 and input to the multiplier 75 with a signal of 10.76 MHz.

Accordingly, the output of the limiter 71 and the output of the sampler 74 are multiplied by the multiplier 75, and the APC low pass filter 76 low pass filters it and transmits it to the local oscillator 60. To adjust the frequency and phase of the oscillator 60.

The PLL 77 generates a clock of 75 MHz at the output of the sampler 69, and the divider 78 divides the output of the PLL 77 by 7 to generate a clock of 10.76 MHz, and then the sampler 69 generates the clock. Is applied to (69, 74).

As described above, the present invention has an effect of improving the performance and the S / N ratio of the receiver by reducing the noise and preventing the signal distortion by digitally processing the signal of the secondary intermediate frequency.

Claims (6)

After outputting the difference signal between the constant frequency signal of the local oscillator and the first intermediate frequency signal through the first intermediate frequency amplifier, the SAW filter, and the second intermediate frequency amplifier as the modulated signal of the residual side band, the A / D converter Demodulation means for converting and outputting the digital signal; First sampling means for multiplying the output signal of the demodulation means by another signal wave having a 90 [deg.] Phase difference provided from the NCO, and performing low pass filtering, and outputting the down sampled signal; And second sampling means for sampling the output of the first sampling means according to a predetermined frequency clock of the PLL, and then down sampling and outputting the output signal of the demodulation means. The receiver of claim 1, wherein the A / D converter performs sampling conversion at 107.6 MHz. 2. The apparatus of claim 1, wherein said first and second sampling means sample at 10.76 MHz. After outputting the difference signal between the constant frequency signal of the local oscillator and the first intermediate frequency signal through the first intermediate frequency amplifier, the SAW filter, and the second intermediate frequency amplifier as the modulated signal of the residual side band, the A / D converter Demodulation means for converting and outputting the digital signal; First sampling means for multiplying the output signal of the demodulation means and the 90 [deg.] Phase difference provided by the NCO by multiplying the other signal wave having low pass filtering, and outputting the down sampled signal; And second sampling means for down-sampling the output of the first sampling means according to a predetermined frequency clock of the PLL, and then down-sampling the output signal of the demodulation means. The receiver of claim 4, wherein the A / D converter performs sampling conversion at 75 MHz according to a predetermined frequency clock of the PLL. 5. The apparatus of claim 4, wherein said first and second sampling means sample at 10.76 MHz.