JPH0836483A - Division device - Google Patents

Abstract

PURPOSE:To provide a division device which is capable of reducing the number of times of calculation, performing an arithmetic processing at high speed and is excellent in workability by performing a division by the multiplier of 2 which is larger than a divisor and is the closest to the divisor and determining a value which is close to a quotient by one time calculation. CONSTITUTION:This device has a constitution provided with an input port 1 inputting a dividend and a divisor, a switch circuit 2 performing a switching as to whether a calculation is performed for the inputted dividend or the calculation is performed by defining a feedbacked error value as the dividend, a latch circuit 3 preserving the value outputted from the switch circuit 2, synchronizing the value with a clock, an approximate quotient output circuit 4 outputting the approximate value of the quotient of the dividend and the devisor, a dividend error output circuit 5 calculating the error of the approximate value and the dividend, a data addition circuit 6 adding the approximate quotient, synchronizing the quotient with the clock, a data correction circuit 7 performing a data correction for the error value and the addition value and outputting the remainder and the quotient and a control circuit 8 controlling the whole of the device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dividing device in a digital circuit.

[0002]

2. Description of the Related Art In recent years, with the technical development of digital circuits, in order to improve the performance of various devices, the operation processing speed of circuits mounted in various devices has been increased.

A conventional dividing device will be described below with reference to the drawings. FIG. 3 is a diagram showing an example of a division method in a conventional division device. First, the recovery type division method will be described. First, the value of the dividend D and the value of the divisor d are compared, and when the divisor d is larger, the quotient causes an overflow so that the calculation is not possible. When the dividend D is larger, the dividend D The partial remainder R is obtained by subtracting the divisor d. Here, if the dividend D and the divisor d are both positive numbers, it means that the subtraction can be performed if the partial remainder R is a positive number, so the quotient q is incremented by 1, and if R is a negative number, the subtraction cannot be performed. Since this is the case, the value is restored by adding d to R with q = 0. Then, R is shifted to the left by one digit, d is subtracted from the obtained partial remainder 2R, and the next quotient is similarly obtained from the new partial remainder. This operation is repeated until the quotient has the required number of digits. This relationship is generally expressed as follows. (Equation 1) R _{i + 1} = 2R−q _{i + 1} × d Here, if 2R _i −d ≧ 0, then q _{i + 1} = 1 and if 2R _i −d <0, then q _{i + 1} = 0. . When all quotients are obtained, the partial remainder at that time becomes the lower part of the remainder. In the case of the sign and the absolute value expression, the sign of the quotient is determined and the division is completed.

Next, a non-recovery type division method will be described. In the above-mentioned recovery type division method, since addition for recovery and subtraction at the next digit are continuously performed, it becomes the same as addition at the next digit as shown in the following equation. (Equation 2) {(2R _i −d) + d} × 2-d = 2 (2R _i
The left side of −d) + d indicates that d is added to the partial remainder (2R _i −d) and then left-shifted by 1 bit to double and subtract the divisor d. On the other hand, the right side determines the sign of the partial remainder, and if the number is positive, the next digit is calculated by subtracting the divisor d, and if the number is negative, the next digit is added by the divisor d. This operation is repeated in the same manner. Only when the last digit is calculated, if the partial remainder is a negative number, the divisor d is added to make a correction, and the corrected value is taken as the remainder. If it is a positive number, no correction is made. To the remainder.

In the conventional division device, in the case of the restoration type division method, when performing n-bit division, n times of subtraction and n / 2 times of addition on average are required. In the case of the non-restoration type division method, n / th
Although addition is required twice, addition for restoration can be omitted, and the calculation time can be shortened as compared with the restoration type division method.

[0006]

However, in the above-mentioned conventional configuration, since the restoration type division method needs to perform addition for restoration, n number of subtractions and an average of n / 2 times are performed in the division of n bits. Must be added. In addition, in the non-restoration type division method, in n-bit division, n times of subtraction and an average of n / 2 times of addition are required, and a solution for only one digit of the quotient can be obtained by one operation. There is a problem in that workability is lacking because the calculation processing speed decreases.

The present invention solves the above-mentioned conventional problems by dividing by a multiplier of 2 which is larger than the divisor and closest to the divisor, and obtains a value close to the quotient in one operation.
It is an object of the present invention to provide a dividing device with excellent workability that can reduce the number of calculations and perform calculation processing at high speed.

[0008]

In order to achieve this object, a dividing apparatus according to the present invention is provided with an input port for inputting a dividend and a divisor, and performing an operation on a dividend input from the input port or outputting a dividend error. A switching circuit that performs calculation or switching using the error value fed back from the circuit as the dividend, a latch circuit that stores the value output from the switching circuit in synchronization with the clock, and the dividend and divisor that are stored in the latch circuit. Approximate quotient output circuit that outputs an approximate value of the quotient, and a dividend error output circuit that calculates the error between the dividend input from the input port based on the approximate quotient output from the approximate quotient output circuit, and the approximate quotient output From the data addition circuit that adds the approximate quotient output from the circuit in synchronization with the clock, and the error value and data addition circuit output from the dividend error output circuit Has a data correction output circuit for outputting the remainder and quotient performs data correction on the sum of the approximate quotient being force, the arrangement being and a control circuit for controlling the entire apparatus.

[0009]

With this configuration, the input port inputs the dividend and the divisor, and the switching circuit operates on the dividend input from the input port or calculates the error value fed back from the dividend error output circuit described later as the dividend. The latch circuit stores the value output from the switching circuit in synchronization with the clock, and the approximate quotient output circuit outputs an approximate value of the quotient of the dividend and the divisor stored in the latch circuit, The dividend error output circuit calculates the error with the dividend input from the input port based on the approximate quotient output from the approximate quotient output circuit, and the data addition circuit uses the approximate quotient output from the approximate quotient output circuit as a clock. The data correction output circuit adds the data while synchronizing, and the data correction output circuit outputs a deduction for the error value output from the dividend error output circuit and the addition value of the approximate quotient output from the data addition circuit. Outputs the remainder and quotient performs data correction, in order to control circuit controls the entire apparatus,
Since division is performed by a power of 2 that is larger than the divisor and is closest to the divisor, by obtaining a value close to the quotient with one operation,
The number of calculations can be reduced and the processing speed can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A divider according to an embodiment of the present invention will be described below with reference to the drawings. 1 is a circuit block diagram of a divider according to an embodiment of the present invention.
3 is a flowchart of a dividing device according to an embodiment of the present invention. 1 is an input port for inputting the dividend D and the divisor d, 2 is a switch for performing calculation with the dividend D input from the input port 1 or an error value fed back from a dividend error output circuit 5 described later as a dividend A switching circuit 3 is a latch circuit for storing the value output from the switching circuit 2 in synchronization with a clock, and 4 is an approximate quotient output circuit for outputting an approximate value of a quotient of a dividend and a divisor stored in the latch circuit 3, 5 is a dividend error output circuit for calculating an error from the dividend input from the input port 1 based on the approximate quotient output circuit 4; 6 is the approximate quotient output circuit 4
A data adder circuit for adding the approximate quotient output from the data adder in synchronization with a clock, and 7 for data correction with respect to the error value output from the dividend error output circuit 5 and the added value output from the data adder circuit 6. A data correction circuit 8 outputs a remainder and a quotient, and a control circuit 8 controls the entire apparatus.

The operation of the dividing apparatus of the present invention constructed as above will be described below. First, 146363/93 will be described as an example of decimal division.
First, in this division, when the divisor 93 is approximated and an operation is performed by 100, the quotient can be obtained as 1463 by only the bit shift with respect to the multiplier of 10, and the quotient of 146363 ÷ 93 becomes 1463 or more. . Next, based on the approximated quotient, the error value with the dividend is 10304 (= 1463).
63-1463 × 93). Next, the error value is similarly divided using the approximate value. Here, 103
04 ÷ 93 is approximated by a divisor 93 and divided by 100 to calculate a quotient 103, and an error value 725 (= 10304
−103 × 93) is calculated. Next, the error value is similarly divided using the approximate value. Here, 725/93
To the divisor 93 and divide by 100 to obtain the quotient 7
Is calculated to obtain an error value 74 (= 1034-103 × 93). As described above, if calculation is performed until the quotient becomes 0, (Mathematical formula 3) 146363 = 74 + 0 × 93 + 7 × 93 + 103 × 93 + 1463 × 93 = (1463 + 103 + 7) × 93 + 74 = 1573 × 93 + 74 (Mathematical formula 3) can be derived. And the quotient is 157
3, the surplus can be derived as 74.

When the above-mentioned method is used in binary, the dividend is D, the divisor is d, the quotient is P, the remainder is Q, the smallest power of 2 larger than the divisor d is divided by A, and the dividend D is divided by A. The resulting quotient is p (0), the remainder is qa (0), and the dividends D and p
Assuming that the error when q is (0) is q (0), (Equation 4) D ÷ d = P ... remainder Q D = d × P + Q Further, it is larger than divisor d and most divisor d. By setting the multiplier of 2 that is close to to A, (Equation 5) A = 2 ^m (where 2 ^m−1 <d ≦ 2 ^m ), where the dividend is D and the divisor is A, the quotient is p (0) From remainder qa (0) (Equation 6) D / A = p (0) ... remainder qa (0) D = A × p (0) + qa (0) When dividend D and p (0) are quotients Error of q (0) (Equation 7) q (0) = D−d × p (0) D = d × p (0) + q (0) Below, similarly, the dividend is q (0), the divisor When p is A, the quotient is p (1) and the remainder is qa (1). (Equation 8) q (0) = A × p (1) + qa (1) Similarly, the error q (1) is ) Q (1) = q (0) -d * p (1) q (0) = d × p (1) + q (1) Therefore, in the general formula, if the dividend is q (n) and the divisor is A, the quotient is p (n + 1) and the remainder is qa (n + 1). (N) = A × p (n + 1) + qa (n + 1) Further, the error q (n + 1) is (Equation 11) q (n + 1) = q (n) −d × p (n + 1) q (n) = d × p The formula (n + 1) + q (n + 1) can be derived.

From (Equation 11), q (n) -q (n + 1) = d * p (n + 1), but since d and p (n + 1) are both positive integers, the left side ≤0 can be derived. However, since the equal sign holds only when p (n + 1) = 0, in this case, q
(N) -q (n + 1) = 0 holds, and p (n + 1) ≠ 0
In this case, q (0) -q (n + 1)> 0. here,
p (n) is the quotient when q (n-1) is divided by A,
Since p (n + 1) is the quotient when q (n) is divided by A, the relationship between p (n) and p (n + 1) becomes smaller as n becomes larger, and p (n) becomes smaller than A. When it becomes p (n) = 0, it is possible to guide the convergence. From the above (Equation 7) and (Equation 9) (Equation 12) D = d × p (0) + d × p (1) + q (1) = d × (p (0) + p (1)) + q (1 ). Similarly, in (Equation 11) and (Equation 12), when n is incremented by 1 and substituted until n = k, (Equation 13) D = d × (p (0) + p (1) + p (2) +
p (3) + ... + p (k + 1)) + q (k + 1).

Here, p (n) decreases as the value of n increases and converges to 0. Therefore, if the value of n at the time of convergence is h, then (Equation 13) becomes (Equation 14) D = d × (p (0) + p (1) + p (2) +
p (3) + ... + p (h)) + q (h).

From (Equation 10), p (n) is q (n-1).
Is the value of the quotient when A is divided by A, but when n = h, p
Since (h) has converged to 0, q (h-1) is smaller than A, and therefore (Equation 15) q (h-1) <A can be derived.

At this time, q (h) becomes (Equation 16) q (h-1) = d * p (h) + q (h) q (h-1) = q (h) from (Equation 11). . Therefore, from (Equation 15) and (Equation 16), (Equation 17) q (h) <A (= 2 ^m ) Here, from (Equation 5), the value of d is 2 ^m-1 <d ≦ 2 ^m, so There are cases shown in.

(1) When q (h) <d, (Equation 4),
From (Equation 14) (Equation 18) P = p (0) + p (1) + p (2) + p
(3) + ... + p (h) Q = q (h) (2) If q (h) ≧ d, then q (h) is larger than d, so (Equation 19) q (h) = a × d + b Here, assuming that a is a number of 2 or more, 2 ^m−1 <q (h)
In the case of ≤2 ^m , d <2 ^m-1 and 2 ^m-1 <d≤q
Since (h) ≦ 2 ^m is not satisfied, a = 1 can be derived. Therefore, (Equation 14) is (Equation 20) D = d × (p (0) + p (1) + p (2) +
p (3) + ... + p (h) + h) + q (h) -d can be derived, and from (Equation 4) and (Equation 20) (Equation 21) P = p (0) + p (1) + P (2) + p
(3) + ... + p (h) + h Q = q (h) -d.

Here, a division circuit using the above-described calculation method will be described. As shown in FIG. 2, first, the dividend D and the divisor d are input to the input port 1 (S1). next,
In order to calculate the dividend D and the divisor d input to the input port 1, the switching circuit 2 switches to the input port side and the data addition circuit 6 is cleared (S2). Next, the dividend D and the divisor d sent through the switching circuit 2
Is stored in the latch circuit 3 (S3). Next, the approximate quotient output circuit 4 performs division based on the approximate value of the divisor d stored in the latch circuit 3 to calculate the approximate quotient (S
4). Next, the dividend error output circuit 5 calculates an error value with the dividend D input to the input port 1 based on the approximate quotient calculated in S4, and the data addition circuit 6 adds the approximate quotient. (S5). Next, it is determined whether the quotient p (0) output from the approximate quotient output circuit 4 is 0 (S6). If Yes, jump to S12,
If No, the switching circuit 2 switches to the dividend error output circuit 5 side in order to perform the calculation on the error value calculated in S5 (S7). Next, the error value sent via the switching circuit 2 is stored in the latch circuit 3 as a dividend (S8). Next, the approximate quotient is calculated in the same manner as in S4 (S9). Next, similarly to S5, the calculation of the error value and the addition of the approximate quotient are performed (S10). Next, as in S6, it is determined whether the quotient value p (0) is 0 (S11). If No, the process jumps to S8, and if Yes, a quotient and a remainder confirmation signal are transmitted and the process ends (S12).

As described above, according to this embodiment, the approximate value of the quotient can be obtained by one operation, so that the number of operations can be reduced.

[0020]

As described above, according to the present invention, the input port inputs the dividend and the divisor, and the switching circuit operates on the dividend input from the input port or is fed back from the dividend error output circuit described later. The error value is used as the dividend and the operation is performed or switched, and the latch circuit stores the value output from the switching circuit in synchronization with the clock, and the approximate quotient output circuit stores the quotient of the dividend and divisor stored in the latch circuit. The approximate value is output, and the dividend error output circuit calculates the error with the dividend input from the input port based on the approximate quotient output from the approximate quotient output circuit, and the data adder circuit outputs the approximate quotient output circuit. The sum of the approximate quotient output by the data correction output circuit and the approximate quotient output by the data addition circuit On the other hand, the data is corrected, the remainder and the quotient are output, and since the control circuit controls the entire apparatus, the division is performed by the power of 2 which is larger than the divisor and is the closest to the divisor. By obtaining the value, it is possible to realize a dividing device with excellent workability that can reduce the number of calculations and improve the calculation processing speed.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a divider according to an embodiment of the present invention.

FIG. 2 is a flowchart of a dividing device according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a division method in a conventional division device.

[Explanation of symbols]

 1 Input Port 2 Switching Circuit 3 Latch Circuit 4 Approximate Quotient Output Circuit 5 Dividend Error Output Circuit 6 Data Addition Circuit 7 Data Correction Circuit 8 Control Circuit

Claims (1)

[Claims] 1. An input port for inputting a dividend and a divisor, and switching between an arithmetic operation on a dividend input from the input port or an arithmetic operation using an error value fed back from a dividend error output circuit as a dividend. A switching circuit; a latch circuit that stores the value output from the switching circuit in synchronization with a clock; an approximate quotient output circuit that outputs an approximate value of the quotient of the dividend and the divisor stored in the latch circuit; The dividend error output circuit for calculating an error from the dividend input from the input port based on the approximate quotient output circuit, and the approximate quotient output from the approximate quotient output circuit are synchronized with a clock A data adding circuit for adding while adding, an error value output from the dividend error output circuit, and an addition value of an approximate quotient output from the data adding circuit Divider unit to the data correction output circuit for outputting the remainder and quotient performs data correction, characterized in that it and a control circuit for controlling the whole apparatus against.