JPH0834419B2 - Integrated circuit with short-circuit protection function - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit with a short-circuit protection function, and when the load is short-circuited, it is intended to prevent destruction of a semiconductor switch that controls the ON / OFF of the load. It is a thing.

<Prior Art> Many automobiles are equipped with functional relays. In this functional relay, the drive control IC controls the on / off of semiconductor switches such as power MOS FETs, which controls the current flow to the motor and light bulb.

FIG. 4 shows a functional relay of this kind. In this example, power MOS FET2 (hereinafter FET
When the gate of (abbreviated) is set to a high level (H), the FET2 becomes conductive, and a current flows along the route of battery (not shown) → ignition switch IG → bulb 3 → FET2 → ground, and the bulb 3 lights up. Further, the light bulb 3 is turned off by turning off the FET 2 by the drive control IC 1. The Zener diode 4 and the capacitor 5 form a surge protection circuit.

In the example of FIG. 4 described above, if the load (bulb 3 in this case) is short-circuited during energization, a large current flows and the FET 2 is destroyed. Therefore, conventionally, in order to prevent the destruction of the FET2 due to the short circuit of the load, the measures shown in FIGS. 5 and 6 have been taken.

In the example of FIG. 5, a fuse 6 is provided to prevent the FET 2 from being destroyed.

In the example of FIG. 6, an overcurrent detection circuit 7, an inverter 8 and an AND gate 9 are provided. Therefore, when a short circuit occurs in the load, a high level signal 7a is output from the overcurrent detection circuit 7, and the high level signal 7a is inverted by the inverter 8 and becomes a low level signal 8a, which is input to the AND gate 9. Therefore, the output 9a of the AND gate 9 becomes low level, and the FET 2 is cut off. In this way, destruction of FET2 was prevented.

<Problems to be Solved by the Invention> By the way, the conventional techniques shown in FIGS. 5 and 6 have the following problems.

(I) In the prior art shown in FIG. 5, the fuse 6 must be additionally provided, and the number of load circuit components increases.

(Ii) In the conventional technique shown in FIG. 6, the overcurrent detection circuit 7, the inverter 8 and the AND gate 9 must be separately provided, which complicates the configuration of the load circuit. Moreover, since the overcurrent detection circuit 7 is expensive, the cost is increased.

In view of the above-mentioned conventional technique, the present invention provides an integrated circuit with a short-circuit protection function that can reliably protect semiconductor switches such as FETs without complicating the load circuit.

<Means for Solving Problems> In the present invention for solving the above problems, a semiconductor switch that conducts a current to a load when a conduction signal is input, and a conduction signal input to the semiconductor switch. In an integrated circuit that controls the driving of a load circuit that has a holding element that holds the conduction state of the semiconductor switch for a certain period of time after being stopped, the short circuit occurs when a certain period of time elapses after the conduction signal is output to the semiconductor switch. The output of the conduction signal is stopped for a period of time, the voltage state of the load circuit at this stop is taken in as a voltage signal, and when the voltage signal is a signal indicating a short circuit of the load, the output of the drive signal thereafter is stopped, and otherwise In some cases, the drive signal is output again.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention. As shown in the figure, the light bulb 3 which is the load of the load circuit 10 is on / off controlled by the FET 2. FET2 drain output voltage V _D is resistance
It is divided by R ₁ and R ₂ . A surge protection circuit is formed by the Zener diode 4 and the capacitor 5. Although the details will be described later, the capacitor 5 has a function of holding the FET 2 in the conductive state for a certain period even after the input of the conduction signal of the FET 2 is stopped.

An integrated circuit 100 with a short circuit protection function (hereinafter abbreviated as an integrated circuit) according to the present embodiment outputs a conduction signal a that brings FET2 into a conduction state, and includes a drive control circuit 110, a delay pulse generation circuit 120, and It has an inhibit circuit 130, a drive circuit 140, an input circuit 150, and a memory circuit 160.

Of these, the drive control circuit 110 outputs a drive command b which is a high level signal.

On the other hand, the delay pulse generating circuit 120 is composed of a D flip-flop 121, an AND gate 122, a shift register 123 and an inverter 124. In addition, the inhibit circuit 130
Is composed of a NAND gate 131.

The drive circuit 140 is a P-channel type MOS FET141, N
It is composed of a channel type MOS FET 142 and an inverter 143. And the drain of FET141 is connected to the power supply,
The source of FET141 and the drain of FET142 are connected.
The source of T142 is grounded.

The input circuit 150 is a P-channel type MOS FET 151 and N
It is composed of a C-MOS inverter formed by a channel type MOS FET 152, and diodes 153 and 154 that limit the input voltage value to this C-MOS inverter.

The memory circuit 160 is composed of a D flip-flop.

Next, the operation of this embodiment will be described with reference to FIG. 1 and a time chart of FIG.

I: Operation from time t ₁ to time t ₃ (1-1) The drive command b is output at time t ₁ , and the AND signal c changes from low level L (hereinafter abbreviated as L) to high level H.
(Hereinafter abbreviated as H).

(1-2) At time t _2, the synchronization with the clock pulse CLK, the drive command b 'from the D flip-flop 121 is output. At this time, the AND signal c falls from H to L,
The shift register 123 starts operating and the storage circuit 1
60 is preset.

In (1-3) the time t ₂ later, since the delay pulse signal d is H, NAND signal e becomes L next FET141 conductive state (hereinafter referred to as ON). Further, the inverter signal f which is the inversion of the drive command b'becomes L and the FET 142 is turned off (hereinafter abbreviated as OFF). As described above, the FET 141 is turned on and the FET 142 is turned off. Therefore, the conduction signal a which has become H is sent to the FET 2 and the FET 2 is turned on.
It is turned on, and the electric current passes through the light bulb 3 and lights up.

(1-4) Immediately after lighting, the resistance of the light bulb 3 is small and a large current flows, and the drain voltage V _D becomes a high value, but after a while, the filament temperature rises and the resistance of the light bulb 3 increases.
The drain voltage V _D settles at a low value, which is the saturation voltage of FET2.

II: At time operation from t ₃ to time t ₄ (2-1) the time t ₃ to the time t ₂ time T ₁ has elapsed, the final stage output of the shift register 123 becomes H, the delay pulse signal d is L . The length of time T ₁ is set to the time until the filament of the light bulb 3 is sufficiently warmed up and the resistance of the light bulb 3 increases. The delayed pulse signal d changes from L to H at time t ₄ as the output of the final stage of the shift register 123 changes to L. In this embodiment, the negative pulse period T _{2 in} which the delayed pulse signal d is L is used as the delayed pulse.

(2-2) At time t _3, NAND signal e becomes H because the delayed pulse signal d is L, FET 141 is turned OFF. At this time, the FET 142 holds the OFF state as before time t ₃ . When the FETs 141 and 142 are both turned off in this way, the output of the conduction signal a is stopped. However, due to the charge voltage of the capacitor 5, the FET 2 remains in the ON state for a while after time t ₃ .

(2-3) FET2 is turned on by the charge voltage of capacitor 5
When it is normal and there is no load short circuit, the drain voltage V _D is small and the detection voltage V _{A obtained by} dividing the drain voltage V _D by the resistors R ₁ and R ₂ is also small. Therefore, FET15 of the input circuit 150
1 is ON, FET 152 is OFF, and the input signal g is H. When the At time t ₄ rises delayed pulse signal d, the input signal g is stored, the memory signal h becomes H.

(2-4) FET2 is turned on by the charge voltage of capacitor 5
When the light bulb 3 as the load is short-circuited at the time, the drain voltage V _D has risen to near the power supply voltage value, and the detection voltage V _A becomes H accordingly. Therefore, the FET 151 of the input circuit 150 is turned off, the FET 152 is turned on, and the input signal g becomes L. When the delayed pulse signal d rises at time t _4, the input signal g is stored, the memory signal h becomes L.

III: Operation after time t ₄ (3-1) When the storage signal h becomes L, the drive control circuit 110 discriminates this as a stop signal and forcibly stops the output of the drive command b. And the memory signal h is H
During the period, the drive command b is output according to the control of the light bulb 3.

(3-2) Therefore, at normal times when there is no short circuit of the load, the time
When the delayed pulse signal d changes from L to H at t ₄ , the NAND signal e
Becomes L, the FET 141 is turned on, and the FET 142 remains off, so that the conduction signal a is output again. Then, the FET 2 is turned on by the conduction signal a and the lighting of the electric bulb 3 continues.

(3-3) On the other hand, when the light bulb 3 is short-circuited, the memory signal h becomes L, and as shown by the chain double-dashed line in FIG.
The output of the drive command b stops. Therefore, drive command b'is L
Therefore, even if the delay pulse signal d becomes H at time t ₄ , the NAND signal e remains H and the FET 141 remains OFF. On the other hand, since the inverter signal f becomes H, FET1
42 turns ON. As a result, the conduction signal a is not output and the charge voltage of the capacitor 5 is lowered, so that the FET2
It turns off. Thus, when a short circuit occurs, the current flowing through the FET2 is cut off and the FET2 is prevented from being destroyed.

<Second Embodiment> FIG. 3 shows a second embodiment of the present invention. The integrated circuit 200 according to the second embodiment includes a drive control circuit 110, a delay pulse generation circuit 120, an inhibit circuit 230, a drive circuit 240,
It is composed of an input circuit 150 and a storage circuit 160. Among them, the circuits 110, 120, 150, 160 are the same as those in the first embodiment, and therefore, the inhibit circuit 230 and the drive circuit 240 different from those in the first embodiment will be described.

When the drive command b ′ is input and the delay pulse signal d is H, the FET 231 of the inhibit circuit 230 is turned on, the FET 241 of the drive circuit 240 is turned on, the FET 242 is turned off, and the conduction signal a is output. This state is t _{2 in} FIG.
It corresponds to the period from t _{3 to} the period from time t ₄ at the normal time.

When the drive command b ′ is input and the delay pulse signal d is L, the FET 231 is off, the FET 241 is on, and the FET 242 is off.
And the output of the conduction signal a is stopped. This state is second
In the figure, it corresponds to the period from t _{3 to} t ₄ .

When the drive command b'is not input, the FET 241 becomes OF
Since the F and FET 242 are turned on, the conduction signal a is not output regardless of the state of the delay pulse d. This state is the second
In the figure, it corresponds to the period after time t ₄ when the load is short-circuited.

As described above, the inhibit circuit 230 and the drive circuit 240 of the second embodiment have the same functions as the inhibit circuit 130 and the drive circuit 140 of the first embodiment. Therefore, even with the integrated circuit of the second embodiment, it is possible to prevent the FET 2 from being broken when a short circuit occurs.

<Effects of the Invention> According to the present invention as specifically described in connection with the above embodiments, the integrated circuit for driving and controlling the semiconductor switch determines a short circuit of the load, and when the short circuit occurs, the semiconductor switch is cut off. It is not necessary to provide a fuse or an overcurrent detection circuit outside the integrated circuit, and it is possible to avoid complicating the load circuit. Therefore, the installation space can be saved,
Contributes to the integration of the circuit configuration.

[Brief description of drawings]

1 is a circuit diagram showing the first embodiment of the present invention, FIG. 2 is a time chart showing the first embodiment, FIG. 3 is a circuit diagram showing the second embodiment of the present invention, and FIG. FIG. 6 to FIG. 6 are circuit diagrams showing the prior art. In the drawing, 2 is a FET (semiconductor switch), 3 is a light bulb, 5 is a capacitor (holding element), 10 is a load circuit, 100 and 200 are integrated circuits, and 1
10 is a drive control circuit, 120 is a delay pulse generation circuit, 130, 230
Is an inhibit circuit, 140 and 240 are drive circuits, 150 is an input circuit, and 160 is a memory circuit.

Claims (1)

[Claims] Claim: What is claimed is: 1. A semiconductor switch which conducts when a conduction signal is input and passes a current through a load, and the conduction state of the semiconductor switch is maintained for a certain period of time after the input of the conduction signal to the semiconductor switch is stopped. In the integrated circuit that drives and controls the load circuit that has a holding element, a drive control circuit that outputs a drive command and a delayed pulse that has a predetermined pulse width after a certain time delay from the time when the drive command is output. A delay pulse generation circuit that generates a drive pulse, an inhibit circuit that is in a drive mode when a drive command is output and a delay pulse is not output, and an inhibit circuit that is an inhibit mode when a drive command is output and a delay pulse is output, When the inhibit circuit is in the drive mode, a conduction signal is output to the semiconductor switch, and the inhibit circuit inhibits. The drive circuit whose output becomes high impedance when in the mode, the input circuit which takes in the voltage signal corresponding to the potential of the connecting portion connecting the semiconductor switch and the load, and the voltage signal which was taken in by the input circuit at the end of the delay pulse An integrated circuit with a short-circuit protection function, and a storage circuit for transmitting a stop signal for stopping the output of the drive command to the drive control circuit when the stored voltage signal is a signal indicating a short circuit of the load. circuit.