JPS63285022A - Integrated circuit with short-circuit protecting function - Google Patents

Abstract

PURPOSE:To prevent a load circuit from being complicated by allowing an integrated circuit itself applying driving control to a semiconductor switch to discriminate the short-circuit of the load, and interrupting the semiconductor switch at short-circuit. CONSTITUTION:After a conduction signal is outputted toward a semiconductor switch 2 and a prescribed time elapses, the output of a conduction signal is stopped for a short time only. Then the voltage state of a load circuit 10 at the stop is fetched as a voltage signal and the output of the succeeding driving signal is stopped when the voltage signal is a signal representing the short- circuited of the state load and when not, the driving signal is outputted again. Thus, the semiconductor switch such as a FET or the like is protected surely without complicating the load circuit.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an integrated circuit with a short-circuit protection function, and is intended to prevent destruction of a semiconductor switch that controls on/off of a load when the load is short-circuited. It is something.

<Conventional Technology> Automobiles are equipped with a large number of functional relays. In this functional relay, a drive control IC controls the on/off of a semiconductor switch such as a power MO5FET, thereby controlling energization/cutoff of current flowing to a motor, light bulb, etc.

FIG. 4 shows this type of functional relay. In this example, the power MO5FET 2 is controlled by the drive control ICI.
When the gate of FET (hereinafter abbreviated as FET) is set to high level (H), FET 2 becomes conductive, and battery (not shown) → ignition switch [G → light bulb 3 → FET
Current flows along the path 2→ground, and light bulb 3 lights up. Further, the light bulb 3 is turned off by turning off the FET 2 by the drive control IC 1. Note that a surge protection circuit is formed by the Zener diode 4 and the capacitor 5.

In the example shown in FIG. 4 described above, if the load (in this case, the light bulb 3) is short-circuited during energization, a large current will flow and the FET 2 will be destroyed. Therefore, in the past, F
In order to prevent the destruction of ET 2, the measures shown in Figures 5 and 6 were taken.

In the example shown in FIG. 5, a fuse 6 is provided to prevent destruction of the FET 2.

In the example of FIG. 6, the overcurrent detection circuit 7. It includes an inverter 8 and an AND gate 9.

Therefore, when a short circuit occurs in the load, a high level signal 7a is output from the overcurrent detection circuit 7, and this high level signal 7a is inverted by the inverter 8 to become a low level signal 8a, which is input to the AND gate 9. Therefore, the output 9a of the AND gate 9 becomes low level, and the FET 2 is cut off. In this way, destruction of FET 2 was prevented.

<Problems to be Solved by the Invention> By the way, the prior art shown in FIGS. 5 and 6 has the following problems.

(il) In the conventional technique shown in FIG. 5, a fuse 6 must be provided separately, which increases the number of components in the load circuit.

(!i) In the prior art shown in FIG. 6, the overcurrent detection circuit 7. The inverter 8 and AND gate 9 must be provided separately, making the configuration of the load circuit complicated. Moreover, since the overcurrent detection circuit 7 is expensive, the cost increases.

In view of the above-mentioned prior art, the present invention provides an integrated circuit with a short-circuit protection function that can reliably protect semiconductor switches such as FETs without complicating the load circuit.

<Means for Solving the Problems> The present invention, which solves the above-mentioned problems, consists of a semiconductor switch that becomes conductive and conducts current to a load when a conductive signal is manually applied, and a semiconductor switch that is connected manually to the conductive signal to the semiconductor switch. In an integrated circuit that drives and controls a load circuit that has a holding element that maintains the conduction state of the semiconductor switch for a certain period of time after the semiconductor switch is stopped, when a certain period of time has elapsed after a conduction signal is output to the semiconductor switch. , stops the output of the conduction signal for a short time,
The voltage state of the load circuit at the time of this stop is captured as a voltage signal, and when the voltage signal is a signal indicating a short circuit in the load, the output of subsequent drive signals is stopped, and when it is not, the drive signal is output again. shall be.

<Example> Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

First example> FIG. 1 shows a first embodiment of the invention.

As shown in the figure, the light bulb 3 serving as the load of the load circuit 1o is
On/off control is performed by FET 2. Drain output voltage V of FET 2. is divided by resistors R, , R2.

Further, a surge protection circuit is formed by the Zener diode 4 and the capacitor 5. The details will be explained later, but
The capacitor 5 has a function of keeping the FET 2 in a conductive state for a certain period of time even after the input of the conduction signal to the FET 2 is stopped.

The integrated circuit with short circuit protection function 100 (hereinafter abbreviated as integrated circuit) according to the present embodiment outputs a conduction signal a that makes the FET 2 conductive, and includes a drive control circuit 110 and a delay pulse generation circuit 120. and inhibit circuit 13
0, a drive circuit +40, an input circuit 150, and a memory circuit +60.

Of these, the drive control circuit 110 outputs a drive command which is a high level signal.

On the other hand, the delayed pulse generation circuit 120 includes D flip-flops 121 . ANDGATE 122. shift register +23
and an inverter 124. Further, the inhibit circuit 130 is composed of a Nant gate 131.

The drive circuit 140 is a P-channel type MOS FE.
T141. It is composed of an N-channel type MOS FET 142 and an inverter 143. The source of FET 142 is connected to the drain of FET 142, and FET 14
2 sources are grounded.

The input circuit 150 is a P-channel type MO5FET15.
It is composed of a C-MOS inverter formed of 1- and N-channel type O5FETs 152, and diodes 153 and 154 that limit the input terminal value to this C-MOS inverter.

The memory circuit 160 is composed of a D flip-flop.

Next, the operation of this embodiment will be explained with reference to FIG. 1 and FIG. 2 which is a time chart.

Operation: Operation from time t1 to time t3 (1-1) At time t, a drive command is output, and the AND signal C changes from low level (abbreviated below) to high level H.
(hereinafter abbreviated as H).

(1-2) At time t2, the drive command b° is output from the D flip 70 knob 121 in synchronization with the clock pulse CL. At this time, the AND signal C falls from H to L, the shift register 123 starts operating, and the memory circuit 160 is preset.

(1-3) After time t2, the delayed pulse signal d is H, so the NAND signal e becomes L, and the FET 141 becomes conductive (hereinafter abbreviated as ON). Further, the inverter signal f, which is the inversion of the drive command b', is activated, causing the FET 142 to enter a cut-off state (hereinafter abbreviated as OFF).

In this way, FET141 is ON and FET142 is OFF.
Since the signal becomes F, the conductive signal a that becomes H is sent to FET 2, which turns on, and current passes through the light bulb 3, turning it on.

(1-4) Immediately after lighting, the resistance of the bulb 3 is small and a large current flows, resulting in a high drain voltage VD. However, after a while, the filament temperature rises, the resistance of the bulb 3 increases, and the drain voltage VO is reduced by the FET. It settles to a low value, which is the saturation voltage of 2.

(2): Operation from time t3 to time t4 (2-1) At time 1, which has elapsed from time t2 to time T, the final stage output of the shift register 123 becomes H, and the delayed pulse signal d becomes L. Note that the length of time T is set to the time required for the filament of the light bulb 3 to sufficiently warm up and the resistance of the light bulb 3 to become large. delayed pulse signal d
At time t4, as the final stage output of shift register +23 becomes L, it becomes L or H. In this embodiment, the negative pulse period T2 during which the delayed pulse signal d is at L is used as a delayed pulse.

(2-2) At time t3, the delayed pulse signal d becomes L, so the NAND signal e becomes H, and the FETI 41 turns OFF. At this time, the FETI 42 maintains the OFF state as before time t3. When FETs 141 and 142 are both turned OFF in this way, the output of conduction No. 43a stops. However, due to the charging voltage of the capacitor 5, the FE
The ON state of T2 continues.

(2-3) FET by charging voltage of capacitor 5
2 is ON, if there is no load short circuit and the load is normal, the drain voltage vO is small, and the detected voltage vA obtained by dividing the stiffness by the resistors R, , II2 is also small.

Therefore, FET 151 of input circuit +50 is turned on.

FETl52 is turned OFF, and the human input signal g becomes H.

Then, when the delayed pulse signal d rises to L at time t4, the human power signal g is stored, and the stored signal becomes H.

(2-4) FET by charging voltage of capacitor 5
If light bulb 3, which is the load, is short-circuited when 2 is on, the drain voltage VD has risen to near the power supply voltage value,
Along with this, the detection voltage VA becomes H. Therefore, the input circuit 150<7) FET
151 is turned OFF, FETl52 is turned ON, and the human power signal g goes low. Then, when the delayed pulse signal d rises at time t4, the input signal g is stored and becomes the storage signal hLtL.

■: Operation after time 4 (3-1) When the memory signal becomes L, the drive control circuit 110 determines this as a stop signal and forcibly stops outputting the drive command. Light bulb 3 is off while the memory signal is H.
A drive command is output according to the control of the controller.

(3-2) Therefore, under normal conditions without a short circuit in the load, when the delayed pulse signal d goes from L to H at time t4, the NAND signal e goes to L and the FET 141 turns on, and the FE
Since T142 remains OFF, the conduction signal a is output 14 times. This conduction signal a causes FET 2 to become O.
It becomes N and the light bulb 3 continues to light up.

(3-3) On the other hand, if the light bulb 3 is short-circuited, the memory signal becomes L, and the output of the drive command stops, as shown by the dot-dashed line in FIG.

Therefore, since the drive command b° becomes L, even if the delayed pulse signal d becomes H at time t4, the NAND signal e remains at H and the FET 141 remains OFF. On the other hand, since the inverter signal f becomes H, the FETI 42 is turned ON. As a result, the conductive signal a is not output, and the charging voltage of the capacitor 5 becomes low, so that the FET 2 is turned off. Thus, in case of short circuit, FET
The current flowing through FET 2 is cut off, and destruction of FET 2 is prevented.

<Second example> FIG. 3 shows a second embodiment of the invention.

The integrated circuit 200 according to this second embodiment includes a drive control circuit +10. Delay pulse generation circuit 120. Inhibit circuit 230. Drive circuit 240. It consists of an input circuit +50 and a memory circuit 160.

Among these circuits, the circuits 110, 120, 150, and 160 are the same as those in the first embodiment, so the inhibit circuit 230 and drive circuit 240, which are different from the first embodiment, will be explained.

When the drive command b° is input and the delayed pulse signal d is H, FET2:11 of the inhibit circuit 230
is ON, FET 241 of drive circuit 240 is ON,
The FET 242 is turned off and the conduction signal a is output. In FIG. 2, this state corresponds to the period from t2 to t3 and the period after time t4 during normal operation.

When the drive command b' is input and the delayed pulse signal d is L, the FET 231 is turned off.

FET241 turns on, FET242 turns off,
Output of conduction signal a is stopped. This state corresponds to the period from t3 to t4 in FIG.

When the drive command b° is not input, the FET 241 is OFF and the FET 242 is ON, so the conduction signal a cannot be output regardless of the state of the delay pulse d. In FIG. 2, this state corresponds to the period after time t4 when the load is short-circuited.

In this way, the inhibit circuit 230 and drive circuit 240 of the second embodiment are similar to the inhibit circuit 1 of the first embodiment.
30 and the drive circuit 140. Therefore, even with the integrated circuit of the second embodiment, F at the time of short circuit
It can prevent the destruction of ET 2.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, the integrated circuit that drives and controls the semiconductor switch itself determines whether the load is short-circuited, and when the short-circuit occurs, the semiconductor switch is cut off. There is no need to provide a fuse or overcurrent detection circuit outside the integrated circuit, and it is possible to avoid complicating the load circuit. This saves installation space and contributes to the consolidation of circuit configurations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a time chart showing the first embodiment, FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and FIG. 6 to 6 are circuit diagrams showing the prior art. In the drawing, 2 is an FET (semiconductor switch), 3 is a light bulb, 5 is a capacitor (holding element), 10 is a load circuit, 100 and 200 are integrated circuits, 110 is a drive control circuit, +20 is a delay pulse generation circuit, 130. 230 is an inhibit circuit, 140 and 240 are drive circuits, 150 is an input circuit, and 160 is a storage circuit.

Claims (1)

[Claims] A semiconductor switch that becomes conductive when a conduction signal is input and passes current through the load; and a semiconductor switch that becomes conductive for a certain period of time after the input of the conduction signal to the semiconductor switch is stopped. In an integrated circuit that drives and controls a load circuit that has a holding element that holds a load, the drive control circuit outputs a drive command, and a delay pulse that has a predetermined pulse width delayed by a certain period of time from the time when the drive command is output. and an inhibit circuit that enters a drive mode during a period when a drive command is output and no delay pulse is output, and enters an inhibit mode during a period when a drive command is output and a delay pulse is output. , when the inhibit circuit enters the drive mode, it outputs a conduction signal to the semiconductor switch, and when the inhibit circuit enters the inhibit mode, the output becomes high impedance.The drive circuit outputs a high impedance signal, and the potential of the connection part connecting the semiconductor switch and the load is set to An input circuit that takes in a corresponding voltage signal, and a stop that stores the voltage signal taken in by the input circuit at the end of the delayed pulse and stops outputting the drive command when the stored voltage signal is a signal indicating a short circuit in the load. An integrated circuit with a short-circuit protection function, comprising: a memory circuit that sends a signal to a drive control circuit.