JPH08340167A - Clock use circuit board and manufacture thereof - Google Patents

Clock use circuit board and manufacture thereof

Info

Publication number
JPH08340167A
JPH08340167A JP7170189A JP17018995A JPH08340167A JP H08340167 A JPH08340167 A JP H08340167A JP 7170189 A JP7170189 A JP 7170189A JP 17018995 A JP17018995 A JP 17018995A JP H08340167 A JPH08340167 A JP H08340167A
Authority
JP
Japan
Prior art keywords
circuit board
plating
hole
electrode
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7170189A
Other languages
Japanese (ja)
Inventor
Hitoshi Maruyama
仁 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP7170189A priority Critical patent/JPH08340167A/en
Publication of JPH08340167A publication Critical patent/JPH08340167A/en
Pending legal-status Critical Current

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  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE: To provide a clock use circuit board, which can be subjected to punching work with good accuracy and easily, and a method of manufacturing the board. CONSTITUTION: In an insulating board 7, a plating hole 12 is bored in an electrode formation part 1 of a clock use circuit board 701. Then, a panel plating is applied to the surface of the board 7 and the inner wall of the hole 12. Then, the hole 12 and a circuit pattern formation part are covered with a resist film to form an electrode use plated film 100 on the inner wall of the hole 12 and to form a circuit pattern on the surface of the board 7. Then, the resist film is peeled off and after that, one part of the hole 12 with the film 100 formed on its inner wall is left to cut off an unnecessary part 702 of the board 7, whereby an electrode 10 is formed. In the case of the cut-off of the part 702, doglegged recess parts 11 made to recess into a doglegged shape are respectively formed in side parts 792, which are positioned at the parts of both sides of the electrode 10 formed on the inner wall of the hole 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,側面に電極を有する時
計用回路基板及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timepiece circuit board having electrodes on its side surfaces and a method for manufacturing the same.

【0002】[0002]

【従来技術】電子式時計の内部には,電子部品を搭載し
た時計用回路基板が設けられている(後述する図2参
照)。例えば,図15に示すごとく,かかる時計用回路
基板701の電極50は,その側面79に設けられてい
る。
2. Description of the Related Art A circuit board for electronic timepieces is provided inside an electronic timepiece (see FIG. 2 described later). For example, as shown in FIG. 15, the electrode 50 of the timepiece circuit board 701 is provided on the side surface 79 thereof.

【0003】上記時計用回路基板701を製造する方法
としては,従来,例えば,特公昭56─54648号公
報に開示された方法がある。以下,その概要を説明す
る。まず,図9に示すごとく,両面に銅箔を貼着した絶
縁基板7に,エンドミルにより一対の小孔91を穿設す
る。小孔91は,後工程の外形打ち抜き加工時に電極の
めっき膜の剥がれを防止するために設けたものである。
次に,図10に示すごとく,各小孔91の一部を覆うよ
うな径を有する大穴92を,エンドミルにより穿設す
る。
As a method of manufacturing the above-mentioned timepiece circuit board 701, there is a method disclosed in, for example, Japanese Patent Publication No. 56-54648. The outline will be described below. First, as shown in FIG. 9, a pair of small holes 91 are bored by an end mill in the insulating substrate 7 having copper foil adhered on both sides. The small hole 91 is provided in order to prevent the plating film of the electrode from peeling off when the outer shape is punched out in a later step.
Next, as shown in FIG. 10, a large hole 92 having a diameter that covers a part of each small hole 91 is bored by an end mill.

【0004】次に,図11,図12に示すごとく,小孔
91及び大穴92の内部を含めて,絶縁基板7の表面全
体に,パネルめっき61を施す。次に,図12,図13
に示すごとく,小孔91及び大穴92の表面,及び回路
形成部分の表面に,レジスト膜95を被覆させ,エッチ
ング処理を施す。次に,レジスト膜95を除去する。こ
れにより,図14に示すごとく,電極用めっき膜500
及び回路パターン52が形成される。また,電極用めっ
き膜500の周囲には,ランド951が形成される。
Next, as shown in FIGS. 11 and 12, panel plating 61 is applied to the entire surface of the insulating substrate 7 including the insides of the small holes 91 and the large holes 92. Next, FIG. 12 and FIG.
As shown in FIG. 5, the surface of the small hole 91 and the large hole 92, and the surface of the circuit forming portion are covered with a resist film 95 and subjected to etching treatment. Next, the resist film 95 is removed. As a result, as shown in FIG.
And the circuit pattern 52 is formed. A land 951 is formed around the electrode plating film 500.

【0005】その後,上記電極50を形成すべき大穴9
2の一部分及び小穴91の一部分を残して,図14,図
15に示すごとく,外形プレス抜き加工により,切除線
791に沿って絶縁基板7を打ち抜き,不要部分702
を切除する。また,同時に,図14に示すごとく,電子
部品を搭載するための搭載穴73及び,開口穴74を穿
設する。これにより,側面79に弧状の電極50を設け
た時計用回路基板701が得られる。尚,図11,図1
3において,符号62は銅箔を示す。
After that, the large hole 9 in which the electrode 50 is to be formed
As shown in FIGS. 14 and 15, leaving part of No. 2 and part of the small hole 91, the insulating substrate 7 is punched along the cutting line 791 by external press punching, and the unnecessary portion 702 is removed.
Excise. At the same time, as shown in FIG. 14, a mounting hole 73 for mounting an electronic component and an opening hole 74 are formed. As a result, the timepiece circuit board 701 having the arc-shaped electrode 50 on the side surface 79 is obtained. Incidentally, FIG. 11 and FIG.
In 3, the reference numeral 62 indicates a copper foil.

【0006】[0006]

【解決しようとする課題】しかしながら,上記従来の時
計用回路基板の製造方法においては,小穴91及び大穴
92を2回に分けて穴明けする必要がある。また,その
ため,穿設位置にズレが生じやすく,電極50の形状が
変形することがあり,精度上問題がある。また,作業工
程が長くなる。更に,回路形成工程におけるレジスト膜
の形成位置が僅かにずれた場合でも,小孔91の上下開
口部がレジスト膜95により被覆されず,その隙間から
エッチング液が浸入して,電極用めっき膜500が損傷
を受けることがある。
However, in the above-described conventional method for manufacturing a timepiece circuit board, it is necessary to open the small hole 91 and the large hole 92 in two steps. Therefore, the drilling position is likely to be displaced, and the shape of the electrode 50 may be deformed, which causes a problem in accuracy. In addition, the work process becomes long. Further, even if the resist film formation position is slightly deviated in the circuit forming process, the upper and lower openings of the small hole 91 are not covered with the resist film 95, and the etching solution penetrates through the gap to form the electrode plating film 500. May be damaged.

【0007】そこで,小孔91を明けることなく大穴9
2だけを形成することが考えられる。しかし,この場合
には,図15に示す如く,絶縁基板7の打ち抜き加工時
において,当該加工により形成される側面79と予め形
成された大穴92の内壁とが交差する部分が,鈍角状の
突出部98となる。そのため,打ち抜き型からの圧縮応
力により,大穴92付近の側面79に,バリ,或いは,
小穴91付近の側面79にめっき膜のはがれが発生する
ことがある。
Therefore, the large hole 9 is formed without opening the small hole 91.
It is conceivable to form only 2. However, in this case, as shown in FIG. 15, during punching of the insulating substrate 7, a portion where the side surface 79 formed by the machining intersects with the inner wall of the large hole 92 formed in advance is obtusely projecting. Part 98. Therefore, due to the compressive stress from the punching die, the side surface 79 near the large hole 92 is burred, or
The plating film may peel off on the side surface 79 near the small hole 91.

【0008】本発明はかかる従来の問題点に鑑み,精度
良く且つ容易に打抜き加工することができる,時計用回
路基板及びその製造方法を提供しようとするものであ
る。
In view of the above problems of the prior art, the present invention is to provide a timepiece circuit board and a method of manufacturing the same that can be punched with high precision and ease.

【0009】[0009]

【課題の解決手段】本発明は,時計用回路基板を形成す
るための絶縁基板を準備し,次いで,該絶縁基板におけ
る上記時計用回路基板の電極形成部分にめっき用穴を穿
設し,次いで,絶縁基板の表面及びめっき用穴の内壁に
パネルめっきを施し,次いで,上記めっき用穴及び回路
パターン形成部分をレジスト膜により覆ってエッチング
処理を行うことにより,上記めっき用穴の内壁には電極
用めっき膜を,絶縁基板の表面には回路パターンを形成
し,次いで,上記レジスト膜を剥離し,その後,上記電
極用めっき膜を形成した上記めっき用穴の一部を残し
て,上記絶縁基板の不要部分を切除することにより電極
を形成する,時計用回路基板の製造方法であって,上記
絶縁基板における不要部分の切除の際には,上記めっき
用穴の内壁に形成した上記電極の両側部分に位置する側
部に,「く」の字状に窪んだく字形凹部を形成すること
を特徴とする時計用回路基板の製造方法にある。
According to the present invention, an insulating substrate for forming a timepiece circuit board is prepared, and then a plating hole is formed in the electrode forming portion of the timepiece circuit board on the insulating substrate, and then a plating hole is formed. , The surface of the insulating substrate and the inner wall of the plating hole are subjected to panel plating, and then the plating hole and the circuit pattern forming portion are covered with a resist film to carry out an etching treatment so that the inner wall of the plating hole has an electrode. Forming a circuit pattern on the surface of the insulating substrate, then removing the resist film, and then leaving a part of the plating hole in which the electrode plating film is formed, leaving the insulating substrate A method of manufacturing a circuit board for a watch, wherein an electrode is formed by cutting off an unnecessary portion of the insulating substrate, which is formed on the inner wall of the plating hole when the unnecessary portion of the insulating substrate is cut off. On the side located on both sides of the electrode, in the manufacturing method of the timepiece circuit board and forming a shape in Ku-shaped recess which is recessed in the "V".

【0010】本発明において最も注目すべきことは,パ
ネルめっきが施されためっき用穴の一部を残して絶縁基
板を切除することによりめっき用穴の内壁に電極を形成
すると共に,上記電極の両側部分に位置する側部が
「く」の字状に窪むように切除してく字形凹部を形成す
ることである。
What is most noticeable in the present invention is that the electrode is formed on the inner wall of the plating hole by cutting off the insulating substrate leaving a part of the plating hole for panel plating, and This is to form a dogleg-shaped recess by cutting so that the side portions located on both sides are recessed in a dogleg shape.

【0011】上記く字形凹部は,上記電極の両側部分に
位置する側部において,「く」の字状に交わる二つの面
より構成されている。この二つの面は,絶縁基板の切除
の際に形成される。
The V-shaped concave portion is composed of two surfaces that intersect in a V-shape on the side portions located on both sides of the electrode. These two surfaces are formed when the insulating substrate is cut off.

【0012】く字形凹部の角度は,70〜110度であ
ることが好ましい。70度未満の場合には,絶縁基板に
クラックが発生するおそれがある。一方,110度を越
える場合には,電極の両側部分にバリが発生するおそれ
がある。
The angle of the V-shaped recess is preferably 70 to 110 degrees. If it is less than 70 degrees, cracks may occur in the insulating substrate. On the other hand, if it exceeds 110 degrees, burrs may occur on both sides of the electrode.

【0013】上記めっき用穴は,円形状であることが好
ましい。それは,めっき用穴を穿設する際の位置合わせ
が容易であり,まためっき用穴の形成位置精度が高いか
らである。また,めっき用穴の形状は,四角形状,又は
三形状でもよい。
The plating hole is preferably circular. This is because the positioning at the time of forming the plating holes is easy, and the accuracy of forming the plating holes is high. Further, the shape of the plating hole may be square or three.

【0014】上記めっき用穴の内壁には,パネルめっき
によって形成された電極用めっき膜が施されている。ま
た,めっき用穴の内壁だけでなく,その上下開口周縁部
にもパネルめっきを残すことによって形成したランドを
施すことが好ましい。これにより,めっき用穴の内壁を
被覆する電極用めっき膜の剥離を防止することができ
る。
The inner wall of the plating hole is provided with an electrode plating film formed by panel plating. Further, it is preferable to form the land formed by leaving the panel plating not only on the inner wall of the plating hole but also on the peripheral portions of the upper and lower openings thereof. As a result, peeling of the electrode plating film covering the inner wall of the plating hole can be prevented.

【0015】上記の製造方法により製造された時計用回
路基板としては,例えば,電極と回路パターンとを設け
た時計用回路基板において,上記電極は,時計用回路基
板の側面に形成した電極用めっき膜により形成されてお
り,上記電極の両側部分に位置する側部には,「く」の
字状に窪んだく字形凹部が形成されていることを特徴と
する時計用回路基板がある。
The timepiece circuit board manufactured by the above manufacturing method is, for example, a timepiece circuit board having electrodes and circuit patterns, and the electrodes are plated for electrodes formed on the side surface of the timepiece circuit board. There is a circuit board for a timepiece, which is formed of a film and has a V-shaped concave recessed in a V-shape on the side portions located on both sides of the electrode.

【0016】上記く字形凹部の角度は,上記と同様の理
由により,70〜110度であることが好ましい。
The angle of the V-shaped recess is preferably 70 to 110 degrees for the same reason as above.

【0017】[0017]

【作用及び効果】本発明の時計用回路基板の製造方法に
おいては,パネルめっきが施されためっき用穴の一部を
残して絶縁基板を切除すると共に,めっき用穴の内壁に
形成した電極の両側部分に位置する側部が「く」の字状
となるように切除してく字形凹部を形成している。その
ため,電極の両側部分にバリが発生することを防止する
ことができる。
In the method of manufacturing a timepiece circuit board according to the present invention, the insulating substrate is cut off while leaving a part of the panel-plated plating hole, and the electrode formed on the inner wall of the plating hole is removed. The side portions located on both sides are cut out to form a dogleg shape so as to form a dogleg shape. Therefore, it is possible to prevent burrs from being generated on both sides of the electrode.

【0018】更に,従来のようにめっき用穴から突出し
た小孔がないため,めっき用穴を被覆するレジスト膜の
形成位置が多少ずれた場合にも,めっき用穴の上下は完
全に被覆される。そのため,回路パターン形成の際に,
めっき用穴の内壁を被覆する電極用めっき膜がエッチン
グ処理により損傷を受けることを防止することができ
る。従って,めっき用穴の内壁に電極を損傷なく形成す
ることができる。
Further, since there is no small hole protruding from the plating hole as in the conventional case, the upper and lower parts of the plating hole are completely covered even if the formation position of the resist film covering the plating hole is slightly displaced. It Therefore, when forming a circuit pattern,
It is possible to prevent the electrode plating film covering the inner wall of the plating hole from being damaged by the etching process. Therefore, the electrode can be formed on the inner wall of the plating hole without damage.

【0019】また,本発明においては,1回の孔明けだ
けを行うことにより,めっき用穴を形成している。その
ため,従来のように2回の孔明け作業を行う必要がな
い。従って,打抜き加工が容易である。また,めっき用
穴は,1回の位置合わせをするだけで,その形成位置が
決定される。そのため,形成位置の誤差が少ない。それ
故,めっき用穴の内壁に形成される電極が変形すること
がない。また,電極の形成位置の精度も向上する。
Further, in the present invention, the plating hole is formed by performing the hole only once. Therefore, it is not necessary to perform the drilling work twice as in the conventional case. Therefore, punching is easy. In addition, the formation position of the plating hole is determined only by performing the alignment once. Therefore, there is little error in the forming position. Therefore, the electrode formed on the inner wall of the plating hole is not deformed. In addition, the accuracy of the electrode formation position is also improved.

【0020】次に,本発明の時計用回路基板において
は,時計用回路基板の側面に形成した電極の両側部分に
位置する側部には,く字形凹部が形成されている。その
ため,上記のごとく,バリの発生を防止することがで
き,また,電極の形成位置精度も高い。
Next, in the timepiece circuit board of the present invention, V-shaped recesses are formed on the side portions located on both sides of the electrodes formed on the side surfaces of the timepiece circuit board. Therefore, as described above, the occurrence of burrs can be prevented, and the electrode forming position accuracy is high.

【0021】本発明によれば,精度良く且つ容易に打抜
き加工することができる,時計用回路基板及びその製造
方法を提供することができる。
According to the present invention, it is possible to provide a timepiece circuit board which can be punched with high precision and easily, and a manufacturing method thereof.

【0022】[0022]

【実施例】本発明の実施例に係る時計用回路基板につい
て,図1〜図8を用いて説明する。本例の時計用回路基
板701は,図2に示すごとく,3個の電極10と回路
パターン52とを有している。電極10は,図1に示す
ごとく,時計用回路基板701の側面79に弧状に形成
した電極用めっき膜100により形成されている。電極
10の両側部分に位置する側部792には,「く」の字
状に窪んだく字形凹部11が形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A timepiece circuit board according to an embodiment of the present invention will be described with reference to FIGS. The timepiece circuit board 701 of this example has three electrodes 10 and a circuit pattern 52, as shown in FIG. As shown in FIG. 1, the electrode 10 is formed by an electrode plating film 100 formed in an arc shape on the side surface 79 of the timepiece circuit board 701. The side portions 792 located on both side portions of the electrode 10 are formed with a V-shaped concave portion 11 that is recessed in a V shape.

【0023】次に,上記時計用回路基板の製造方法につ
いて,図1,図3〜図8を用いて説明する。まず,図4
に示すごとく,時計用回路基板を形成するための絶縁基
板7を準備する。この絶縁基板7は,表裏両面に銅箔6
2を貼着したガラスエポキシ樹脂基板である。次いで,
図3に示すごとく,絶縁基板7における上記時計用回路
基板701の電極形成部分1に,エンドミルによりめっ
き用穴12を穿設する。めっき用穴12は,直径3.0
mmの円形である。
Next, a method of manufacturing the above-mentioned timepiece circuit board will be described with reference to FIGS. 1 and 3 to 8. First, Fig. 4
As shown in FIG. 3, an insulating substrate 7 for forming a timepiece circuit board is prepared. This insulating substrate 7 has copper foil 6 on both front and back surfaces.
2 is a glass epoxy resin substrate to which is attached. Then,
As shown in FIG. 3, a hole 12 for plating is formed by an end mill in the electrode forming portion 1 of the circuit board 701 for a timepiece on the insulating substrate 7. The plating hole 12 has a diameter of 3.0
It has a circular shape of mm.

【0024】次いで,図4に示すごとく,絶縁基板7の
表面及びめっき用穴12の内壁にパネルめっき61を施
す。次に,図5に示すごとく,めっき用穴12及び回路
パターン形成部分をレジスト膜35により被覆して,エ
ッチング処理を行う。これにより,図6に示すごとく,
めっき用穴12の内壁及びその上下開口周縁部並びに回
路パターン形成部分にパネルめっき61及び銅箔62を
残したまま,その他の部分のパネルめっき61及び銅箔
62がエッチングされる。
Next, as shown in FIG. 4, panel plating 61 is applied to the surface of the insulating substrate 7 and the inner wall of the plating hole 12. Next, as shown in FIG. 5, the plating hole 12 and the circuit pattern forming portion are covered with a resist film 35, and an etching process is performed. As a result, as shown in FIG.
While leaving the panel plating 61 and the copper foil 62 on the inner wall of the plating hole 12 and the peripheral portions of the upper and lower openings thereof and the circuit pattern forming portion, the other portions of the panel plating 61 and the copper foil 62 are etched.

【0025】その後,レジスト膜35を除去する。これ
により,図7,図8に示すごとく,めっき用穴12の内
壁には電極用めっき膜100が,めっき用穴12の上下
開口周縁部には輪状のランド51が,また,絶縁基板7
の表面には回路パターン52が形成される。
After that, the resist film 35 is removed. As a result, as shown in FIGS. 7 and 8, the electrode plating film 100 is formed on the inner wall of the plating hole 12, the ring-shaped lands 51 are formed on the upper and lower peripheral edges of the plating hole 12, and the insulating substrate 7 is formed.
A circuit pattern 52 is formed on the surface of the.

【0026】その後,図8,図3に示すごとく,切除線
791に沿って,絶縁基板7の不要部分702を打ち抜
き金型により切除する。この際,図1に示すごとく,電
極用めっき膜100を形成しためっき用穴12の一部を
残して電極10を形成するとともに,めっき用穴12の
内壁に形成した上記電極10の両側部分に位置する側部
792,「く」の字状に窪んだく字形凹部11を形成す
る。く字形凹部11の角度αは,70〜110度であ
る。また,電極10を形成する弧状のめっき用穴12の
中心Oの角度θは57°である。
After that, as shown in FIGS. 8 and 3, the unnecessary portion 702 of the insulating substrate 7 is cut along the cutting line 791 by a punching die. At this time, as shown in FIG. 1, the electrode 10 is formed while leaving a part of the plating hole 12 in which the electrode plating film 100 is formed, and the electrode 10 is formed on both sides of the electrode 10 formed on the inner wall of the plating hole 12. The side portion 792 located is formed with a V-shaped recess 11 recessed in a V shape. The angle α of the V-shaped concave portion 11 is 70 to 110 degrees. The angle θ of the center O of the arc-shaped plating hole 12 forming the electrode 10 is 57 °.

【0027】また,上記切除により,時計用回路基板7
01の外周には側面79が形成され,またその内部には
搭載穴73,開口穴74が穿設される。これにより,図
2に示すごとく,3個の弧状の電極10を有する上記の
時計用回路基板701が得られる。
Further, by the above cutting, the circuit board 7 for the timepiece is
A side surface 79 is formed on the outer periphery of 01, and a mounting hole 73 and an opening hole 74 are formed inside thereof. As a result, as shown in FIG. 2, the timepiece circuit board 701 having the three arc-shaped electrodes 10 is obtained.

【0028】次に,本例の作用効果について説明する。
本例の時計用回路基板の製造方法においては,図1に示
すごとく,パネルめっきが施されためっき用穴12の一
部を残して絶縁基板7を切除すると共に,めっき用穴1
2の内壁に形成した電極10の両側部分に位置する側部
が「く」の字状となるように切除してく字形凹部11を
形成している。そのため,電極の両側部分にバリが発生
することを防止することができる。
Next, the function and effect of this example will be described.
In the method of manufacturing a circuit board for a timepiece of this example, as shown in FIG. 1, the insulating substrate 7 is cut off while leaving a part of the plating hole 12 on which the panel plating is applied, and the plating hole 1
The electrode 10 formed on the inner wall of 2 is cut out so that the side portions located on both sides of the electrode 10 have a V-shape to form a V-shaped recess 11. Therefore, it is possible to prevent burrs from being generated on both sides of the electrode.

【0029】更に,図1,図6に示すごとく,従来のよ
うにめっき用穴から突出した小孔がないため,めっき用
穴12を被覆するレジスト膜35の形成位置が多少ずれ
た場合にも,めっき用穴12の上下は完全に被覆され
る。そのため,回路パターン52の形成の際に,めっき
用穴12の内壁を被覆する電極用めっき膜100がエッ
チング処理により損傷を受けることを防止することがで
きる。従って,めっき用穴12の内壁に電極10を損傷
なく形成することができる。
Further, as shown in FIGS. 1 and 6, since there is no small hole protruding from the plating hole as in the conventional case, even when the formation position of the resist film 35 covering the plating hole 12 is slightly shifted. The top and bottom of the plating hole 12 are completely covered. Therefore, it is possible to prevent the electrode plating film 100 covering the inner wall of the plating hole 12 from being damaged by the etching process when the circuit pattern 52 is formed. Therefore, the electrode 10 can be formed on the inner wall of the plating hole 12 without damage.

【0030】また,1回の孔明けだけを行うことによ
り,めっき用穴12を形成している。そのため,従来の
ように2回の孔明け作業を行う必要がない。従って,打
抜き加工を容易に行うことができる。また,めっき用穴
12は,1回の位置合わせをするだけで,その形成位置
が決定される。そのため,形成位置の誤差が少ない。そ
れ故,めっき用穴12の内壁に形成される電極10が変
形することがない。また,電極10の形成位置の精度も
向上する。
Further, the plating hole 12 is formed by performing the drilling only once. Therefore, it is not necessary to perform the drilling work twice as in the conventional case. Therefore, punching can be easily performed. Further, the formation position of the plating hole 12 is determined only by performing the alignment once. Therefore, there is little error in the forming position. Therefore, the electrode 10 formed on the inner wall of the plating hole 12 is not deformed. Moreover, the accuracy of the formation position of the electrode 10 is also improved.

【0031】また,上記の時計用回路基板701におい
ては,その側面79に形成した電極10の両側部分に位
置する側部792には,く字形凹部11が形成されてい
る。そのため,上記のごとく,バリの発生を防止するこ
とができ,また,電極10の形成位置精度も高い。
Further, in the above-mentioned timepiece circuit board 701, the V-shaped concave portion 11 is formed on the side portions 792 located on both side portions of the electrode 10 formed on the side surface 79 thereof. Therefore, as described above, it is possible to prevent the occurrence of burrs, and the formation position accuracy of the electrode 10 is high.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の時計用回路基板における,電極形成部
分を示す説明図。
FIG. 1 is an explanatory view showing an electrode forming portion in a timepiece circuit board according to an embodiment.

【図2】実施例の時計用回路基板の平面図。FIG. 2 is a plan view of the timepiece circuit board according to the embodiment.

【図3】実施例の,めっき用穴を穿設した絶縁基板の平
面図。
FIG. 3 is a plan view of an insulating substrate in which a plating hole is formed according to the embodiment.

【図4】実施例の,パネルめっきを施した絶縁基板の断
面図。
FIG. 4 is a cross-sectional view of an insulating substrate that is panel-plated according to an embodiment.

【図5】実施例の,レジスト膜により被覆した絶縁基板
の断面図。
FIG. 5 is a cross-sectional view of an insulating substrate covered with a resist film according to an example.

【図6】実施例の,エッチング処理を施した絶縁基板の
断面図。
FIG. 6 is a cross-sectional view of an insulating substrate that has been subjected to an etching process according to an example.

【図7】実施例の,レジスト膜を除去した絶縁基板の断
面図。
FIG. 7 is a cross-sectional view of an insulating substrate from which a resist film is removed according to an example.

【図8】実施例の,不要部分切断除去前の絶縁基板の平
面図。
FIG. 8 is a plan view of the insulating substrate according to the embodiment before cutting and removing unnecessary portions.

【図9】従来例の,電極形成用の小孔を穿設した絶縁基
板の平面図。
FIG. 9 is a plan view of an insulating substrate of the related art in which small holes for electrode formation are formed.

【図10】従来例の,電極形成用の大穴を穿設した絶縁
基板の平面図。
FIG. 10 is a plan view of a conventional example of an insulating substrate having large holes for electrode formation.

【図11】従来例の,パネルめっきを施した絶縁基板の
断面図。
FIG. 11 is a sectional view of a conventional example of an insulating substrate plated with a panel.

【図12】従来例の,レジスト膜により被覆した絶縁基
板の平面図。
FIG. 12 is a plan view of a conventional insulating substrate covered with a resist film.

【図13】従来例の,レジスト膜により被覆した絶縁基
板の断面図。
FIG. 13 is a cross-sectional view of a conventional insulating substrate covered with a resist film.

【図14】従来例の,打ち抜き加工前の,絶縁基板の平
面図。
FIG. 14 is a plan view of an insulating substrate of a conventional example before punching.

【図15】従来例の時計用回路基板における,電極形成
部分を示す説明図。
FIG. 15 is an explanatory view showing an electrode formation portion in a conventional timepiece circuit board.

【符号の説明】[Explanation of symbols]

1...電極形成部分, 10...電極, 100...電極用めっき膜, 11...く字形凹部, 12...めっき用穴, 51...ランド, 52...回路パターン, 7...絶縁基板, 79...側面, 792...側部, 701...時計用回路基板, 702...不要部分, 1. . . Electrode forming portion, 10. . . Electrode, 100. . . Electrode plating film, 11. . . V-shaped recess, 12. . . Plating hole, 51. . . Land, 52. . . Circuit pattern, 7. . . Insulating substrate, 79. . . Side, 792. . . Side, 701. . . Circuit board for watch, 702. . . Unnecessary part,

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 時計用回路基板を形成するための絶縁基
板を準備し,次いで,該絶縁基板における上記時計用回
路基板の電極形成部分にめっき用穴を穿設し,次いで,
絶縁基板の表面及びめっき用穴の内壁にパネルめっきを
施し,次いで,上記めっき用穴及び回路パターン形成部
分をレジスト膜により覆ってエッチング処理を行うこと
により,上記めっき用穴の内壁には電極用めっき膜を,
絶縁基板の表面には回路パターンを形成し,次いで,上
記レジスト膜を剥離し,その後,上記電極用めっき膜を
形成した上記めっき用穴の一部を残して,上記絶縁基板
の不要部分を切除することにより電極を形成する,時計
用回路基板の製造方法であって,上記絶縁基板における
不要部分の切除の際には,上記めっき用穴の内壁に形成
した上記電極の両側部分に位置する側部に,「く」の字
状に窪んだく字形凹部を形成することを特徴とする時計
用回路基板の製造方法。
1. An insulating substrate for forming a timepiece circuit board is prepared, and then a plating hole is formed in an electrode forming portion of the timepiece circuit board on the insulating substrate, and then,
Panel plating is applied to the surface of the insulating substrate and the inner wall of the plating hole, and then the plating hole and the circuit pattern formation portion are covered with a resist film for etching, so that the inner wall of the plating hole is used for electrodes. Plating film
A circuit pattern is formed on the surface of the insulating substrate, the resist film is then peeled off, and then unnecessary portions of the insulating substrate are cut off, leaving a part of the plating hole in which the electrode plating film is formed. A method for manufacturing a circuit board for a watch, wherein electrodes are formed by forming a side surface on both sides of the electrode formed on the inner wall of the plating hole when removing an unnecessary portion of the insulating substrate. A method for manufacturing a timepiece circuit board, characterized in that a V-shaped concave portion that is recessed in a V shape is formed in the portion.
【請求項2】 請求項1において,上記めっき用穴の上
下開口周縁部には,上記パネルめっきを残すことによっ
て形成したランドを設けることを特徴とする時計用回路
基板の製造方法。
2. The method for manufacturing a timepiece circuit board according to claim 1, wherein lands formed by leaving the panel plating are provided at upper and lower peripheral edges of the plating hole.
【請求項3】 請求項1又は2において,上記く字形凹
部の角度は,70〜110度であることを特徴とする時
計用回路基板の製造方法。
3. The method for manufacturing a timepiece circuit board according to claim 1, wherein an angle of the V-shaped recess is 70 to 110 degrees.
【請求項4】 請求項1〜3のいずれか一項において,
上記絶縁基板の切除は,打ち抜き金型により行うことを
特徴とする時計用回路基板の製造方法。
4. The method according to claim 1, wherein
A method for manufacturing a timepiece circuit board, wherein the insulating substrate is cut off by a punching die.
【請求項5】 電極と回路パターンとを設けた時計用回
路基板において,上記電極は,時計用回路基板の側面に
形成した電極用めっき膜により形成されており,上記電
極の両側部分に位置する側部には,「く」の字状に窪ん
だく字形凹部が形成されていることを特徴とする時計用
回路基板。
5. A watch circuit board provided with electrodes and a circuit pattern, wherein the electrodes are formed by an electrode plating film formed on a side surface of the watch circuit board and located on both sides of the electrodes. A circuit board for a watch, characterized in that a side face is formed with a concave V-shaped recess.
【請求項6】 請求項5において,上記く字形凹部の角
度は,70〜110度であることを特徴とする時計用回
路基板。
6. The timepiece circuit board according to claim 5, wherein the angle of the V-shaped recess is 70 to 110 degrees.
JP7170189A 1995-06-12 1995-06-12 Clock use circuit board and manufacture thereof Pending JPH08340167A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7170189A JPH08340167A (en) 1995-06-12 1995-06-12 Clock use circuit board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7170189A JPH08340167A (en) 1995-06-12 1995-06-12 Clock use circuit board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH08340167A true JPH08340167A (en) 1996-12-24

Family

ID=15900336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7170189A Pending JPH08340167A (en) 1995-06-12 1995-06-12 Clock use circuit board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH08340167A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396483B (en) * 2010-08-18 2013-05-11 Zhen Ding Technology Co Ltd Apparatus and method for manufacturing printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396483B (en) * 2010-08-18 2013-05-11 Zhen Ding Technology Co Ltd Apparatus and method for manufacturing printed circuit board

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