JPH08335643A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PURPOSE: To form channel width narrower than the resolution limit, by selectively oxidizing an ultra thin film polycrystal Si film, acting as a channel layer, formed on an Si nitride film, with an Si oxide film acting as a part of a gate insulation film and the Si nitride film worked into a specified form on its upper layer, as a mask. CONSTITUTION: An monocrystalline Si substrate 101 is thermal-oxidized for farming an SiO2 film 102, and then, in CVD manner, an Si3 N4 film 103 and a phosphorus dope polycrystalline Si film 104 are deposited. And then an amorphous Si film, acting as a channel layer, whose thickness is 3nm, an SiO2 film 106 acting as a part of a gate insulation film and an Si3 N4 film 107 are deposited sequentially. At the temperature where the SiO2 film 106 is deposited, the amorphous Si film whose thickness is 3nm is transformed into a polycrystalline Si film 105. Then, in dry oxidation manner, the polycrystalline Si film 105 is selectively oxidized, so that an element separation Si oxide film 108 is formed. Thus the channel layer width is formed narrower than the resolution limit, so that enough shift amount of threshold value is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Single-electron devices are expected to be the ultimate highly integrated low-power devices, but there has been a major obstacle so far that they operate only at extremely low temperatures. In 1993, Hitachi's Yano et al. Succeeded in operating a single-electron device (single-electron memory) at room temperature for the first time in the world by using an ultra-thin film polycrystalline Si transistor. The structure of the single electronic memory developed by Yano et al. And the outline of its operating principle will be described below with reference to FIG.

FIG. 10 shows a plan view (a) and cross-sectional views (b) and (c) of a conventional structure of an ultrathin film polycrystalline Si transistor. First, the single crystal Si substrate 601 is thermally oxidized to 5
After the SiO ₂ film 602 having a thickness of 00 nm is formed, a polycrystalline Si film 603 containing phosphorus is deposited to a thickness of 50 nm by the chemical vapor deposition method (CVD method). Next, the phosphorus-doped polycrystalline film 603 is processed into a desired shape by well-known lithography and dry etching to form a source 603 (a) and a drain 603 (b) wiring. Then, a 4 nm amorphous Si film to be the channel layer 604 is formed by the CVD method,
And 10 nm of SiO that becomes a part of the gate insulating film 605.
₂ Film 606 is deposited. At this time, the amorphous Si film is
The polycrystalline Si film 604 is formed by the temperature (750 ° C.) at which the O ₂ film 606 is deposited.

SiO ₂ on the channel polycrystalline Si film 604
The film 605, which is also used as a part of the gate insulating films 605 and 606, is a protective film against contamination and damage when the channel polycrystalline Si film 604 is dry-etched, and a channel polycrystalline Si film 604 by a post-cleaning process. Is used as an etching preventive film.

Next, using an electron beam (EB) lithography and a dry etching technique, a SiO ₂ protective film 605,
The channel polycrystalline Si film 604 is processed. Finally,
SiO ₂ film 6 to be the gate insulating film 606 by the CVD method
After depositing 30 nm of 06 and 100 nm of phosphorus-doped polycrystalline Si 607 to be the gate electrode 607, the gate electrode 607 is formed by a known technique, and the formation of the ultrathin film polycrystalline Si transistor is completed.

The key point for determining the characteristics of the ultra-thin polysilicon transistor is the channel polycrystalline Si film 604.
And the channel width thereof (corresponding to W in the plan view of FIG. 10). Similar to the flash memory, the single electronic memory determines the presence / absence of information (1 or 0) by the difference in the threshold value of the transistor. Therefore, the larger the difference between the thresholds at the time of writing and the erasing of information, the more stable the operation can be.
This difference in threshold becomes larger as the film thickness of the channel polycrystalline Si film becomes thinner and as the width W becomes smaller.

[0007]

One of the technical problems of the single-electron memory using the ultra-thin film polycrystalline Si transistor is the formation of a stable channel layer. As described above, in the single-electron memory, the smaller the thickness of the channel polycrystalline Si film and the smaller the width thereof, the larger the difference in threshold value. The thickness of the polycrystalline Si film can be obtained as a thin film by controlling the type of base film and the deposition time. However, the width of the channel layer is determined by the resolution limit of lithography, so it is below the resolution limit. Very difficult to do.

The technique capable of forming the smallest pattern by the current lithography is EB lithography.
It is very difficult to form a fine pattern of 100 nm or less with good controllability even by using a lithography technique.
Further, EB lithography still has many problems in terms of throughput and controllability, which becomes a bottleneck in mass production of a large capacity memory.

Therefore, in order to improve the characteristics of the single electron memory and the yield thereof, a technique capable of more stably controlling the channel layer having a width of 100 nm or less is essential.

[0010]

The above object is to provide an ultra-thin polycrystalline Si film, which becomes a channel layer formed on a Si nitride film,
This is achieved by performing selective oxidation using a Si oxide film that will be a part of the gate insulating film and a Si nitride film processed into a predetermined shape as an upper layer thereof as a mask.

[0011]

In the well-known LOCOS method typified by planar isolation, the film thickness of the Si oxide film serving as the buffer layer, the film thickness of the Si nitride film serving as the oxidation mask, and the oxidizing conditions (oxide film thickness, temperature, atmosphere) ) To control Si
The lateral extension of the oxide film, that is, the bird's beak length can be adjusted.

The present invention positively utilizes the lateral extension due to this oxidation to control the channel width of the ultrathin polycrystalline Si layer and simultaneously form an element isolation film with an adjacent element. Is.

Since the Si nitride film is used as the base of the channel polycrystalline Si film, the lower element is not oxidized, but only the polycrystalline Si film is oxidized. Further, since the selective oxidation amount is much smaller than that in the usual LOCOS method (50 nm or less), it is sufficient that the film thickness of the Si nitride film serving as a mask is 20 nm or less. Furthermore, since this Si nitride film is also used as a gate insulating film, it need not be removed.

On the other hand, by selective oxidation, the channel polycrystal S
Since the channel width of the i layer recedes inward from the pattern edge of the mask Si nitride film, the pattern edge has no adverse effect on the reliability of the gate insulating film and the like.

According to the present invention, a channel width below the resolution limit can be formed extremely easily, and a sufficient shift amount of the threshold value of the transistor can be secured. Moreover, since excimer laser lithography technology can be applied, mass productivity is dramatically improved.

[0016]

【Example】

(Embodiment 1) A first embodiment of the present invention will be described below with reference to FIG. First, the P-type (100) single crystal Si substrate 101 is thermally oxidized in a steam atmosphere at 1000 ° C.,
After forming the SiO ₂ film 102 with a thickness of 500 nm, CV
The Si ₃ N ₄ film 103 of 50 nm and phosphorus of
A phosphorus-doped polycrystalline Si film 104 containing x10 ²⁰ / cm ³ is deposited to 70 nm. In this embodiment, monosilane (SiH
₄ ) and phosphine (PH ₃ ) were used to deposit the phosphorus-doped polycrystalline Si film 104 at a temperature of 600 ° C. (FIG. 1).
(A)).

Next, the phosphorus-doped polycrystalline Si film 104 is etched by krypton fluoride (KrF) excimer laser lithography and dry etching to form source and drain wirings (not shown in FIG. 1 (see FIG. 10). )).

Next, a 3 nm thick amorphous Si film to be a channel layer, a 20 nm SiO ₂ film 106 to be a part of the gate insulating film, and a 15 nm Si ₃ N ₄ film are formed by the CVD method.
The film 107 is sequentially deposited. In the present embodiment, monosilane (SiH ₄ ) was used to deposit the amorphous Si film at a temperature of 520 ° C. However, it is of course possible to use disilane (Si ₂ H ₆ ). Further, at the temperature (750 ° C.) at which the SiO ₂ film 106 is deposited, the amorphous Si film having a thickness of 3 nm is polycrystalline S.
It is converted to the i film 105.

Subsequently, the uppermost Si ₃ N ₄ film 10 is formed by using electron beam (EB) lithography and dry etching.
7 patterning is performed (FIG. 1B). In this example, a pattern of Si ₃ N ₄ film 107 having a short side length of about 100 nm was formed.

Next, a 3 nm-thick polycrystalline Si film 105 is selectively oxidized by a dry oxidation method at 850 ° C. to form an element isolation Si oxide film 108. Since the polycrystalline Si film in the portion not covered with the Si ₃ N ₄ film 107 is oxidized,
Patterning of the channel layer 105 and insulation isolation between adjacent elements are performed in a self-aligned manner. Further, due to the lateral expansion of the element isolation oxide film 108, the channel polycrystalline Si film 105 is 25 degrees from the pattern edge of the Si ₃ N ₄ film 107.
and a channel layer having a width of 50 nm was obtained (Fig. 1).
(C)). In this embodiment, the dry oxidation method is used for forming the element isolation oxide film 108, but the same effect can be obtained by using the wet oxidation method. However, in wet oxidation, S
Since the i-nitride film has a high oxidation rate, it is necessary to form the Si nitride film with a large thickness.

Finally, 4 × 10 ²⁰ phosphorus is added by the CVD method.
100 n of phosphorus-doped polycrystalline Si film 109 containing / cm ³
After deposition, the gate electrode 109 is patterned.
(FIG. 1 (d)).

The single electronic memory prototyped by this method is
Approximately 2.3 times the threshold shift was obtained compared with the prototype manufactured by the conventional method. Further, since the Si nitride film has a very high hydrofluoric acid resistance and the amount of film abrasion due to pre-cleaning is small,
The gate breakdown voltage and yield were also better than those of the conventional method.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In the same manner as in Example 1, a 500 nm SiO ₂ film 202 was formed on a single crystal Si substrate 201.
After forming, a 30 nm Si ₃ N ₄ film 203 and a 50 nm SiO ₂ film 204 are deposited by the CVD method. Subsequently, a heat treatment is performed for 5 minutes in an ammonia (NH ₃ ) atmosphere at 700 ° C. to nitride the SiO ₂ film 204, and then a phosphorus-doped polycrystalline Si film containing phosphorus of 4 × 10 ²⁰ / cm ³ by a CVD method. 205 is deposited to 70 nm (FIG. 2)
(A)). Thereafter, phosphorus-doped polycrystalline S is formed by KrF excimer laser lithography and dry etching.
The i film 205 is etched to form source and drain wirings (not shown).

Next, the channel layer 206 is formed by the CVD method.
Which has a thickness of 3 nm, a 15 nm SiO ₂ film 207 which is a part of the gate insulating film, and a 10 nm Si film.
_{A 3} N ₄ film 208 is sequentially deposited. In this embodiment, amorphous Si
Disilane (Si ₂ H ₆ ) was used to deposit the film at a temperature of 450 ° C. In addition, the amorphous Si film is 15 nm SiO 2.
_{When the 2} film 207 is deposited, it is converted into a polycrystalline Si film 206 by the temperature (750 ° C.) in the furnace. Then, the EB lithography and the dry etching method are used to form the uppermost S layer.
The i ₃ N ₄ film 208 is patterned (see FIG. 2).
(B)). Also in this embodiment, Si having a short side length of about 100 nm is used.
_A pattern of ₃ N ₄ film 208 was formed.

Next, by a dry oxidation method at 800 ° C., the polycrystalline Si film 206 having a thickness of 3 nm is selectively oxidized to form an element isolation SiO ₂ film 209. By this selective oxidation,
The width of the channel polycrystalline Si film 206 was set back by 15 nm from the pattern edge of the Si ₃ N ₄ film 208, and a channel layer 206 having a width of 70 nm was obtained (FIG. 2C).

Finally, 4 × 10 ²⁰ phosphorus is formed by the CVD method.
100 n of phosphorus-doped polycrystalline Si film 210 containing 1 / cm ³
After the deposition, the gate electrode 210 is patterned.
(FIG. 2 (d)).

As in the present method, even if the Si oxide film is directly under the channel layer, the Si layer serving as an oxidation stopper is formed under the Si oxide film.
With the nitride film, the same effect as that of the first embodiment can be obtained. The single-electron memory prototyped by the method according to this example provided a threshold shift of about 1.8 times that of the prototype manufactured by the conventional method.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In the same manner as in Example 1, P
Die, (100) single crystal Si substrate 301, thickness 500
nm SiO ₂ film 302, 50 nm Si ₃ N ₄ film 30
3, and after forming a 70 nm phosphorus-doped polycrystalline Si film containing 4 × 10 ²⁰ / cm ^{3 of} phosphorus, the phosphorus-doped polycrystalline Si film is etched by KrF excimer laser lithography and dry etching to form source and drain wirings. Formed (not shown).

Next, a CVD method is used to form a polycrystalline Si film 304 having a thickness of 2.5 nm as a channel layer, a SiO ₂ film 305 having a thickness of 15 nm as a part of the gate insulating film, and a Si film having a thickness of 5 nm.
After sequentially forming the ₃ N ₄ film 306, the uppermost Si layer is formed by electron beam (EB) lithography and dry etching.
Patterning of the ₃ N ₄ film 306 is performed (FIG. 3A). In this example, a Si ₃ N ₄ film 306 pattern having a short side length of about 80 nm was formed.

Then, the polycrystalline Si film 304 having a thickness of 2.5 nm is selectively oxidized by a dry oxidation method at 850 ° C. to form an element isolation SiO ₂ film 307. In this embodiment, the width of the channel polycrystalline Si film 304 after selective oxidation is about 40 nm.
Was (Fig. 3 (b)).

Next, in order to adjust the gate capacitance, a gate insulating film is additionally deposited. In this embodiment, a 15 nm SiO ₂ film 308 is deposited by the CVD method. In a single-electron transistor, there is a trade-off relationship between the writing speed and the amount of threshold shift amount. That is, in order to increase the writing speed under a constant power supply voltage, the gate oxide film needs to be thinned, but at the same time, the threshold shift amount decreases. This decrease in the threshold shift amount can be corrected by making the channel width finer.

Finally, 4 × 10 ²⁰ phosphorus is added by the CVD method.
100 n of phosphorus-doped polycrystalline Si film 309 containing / cm ³
After the deposition, the gate electrode 309 is patterned.
(FIG. 3 (d)).

The single electronic memory prototyped by this method is
About three times the threshold shift was obtained as compared with the prototype manufactured by the conventional method.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. In the same manner as in Example 1,
A P-type (100) single crystal Si substrate 401 with a thickness of 50
0 nm SiO ₂ film 402, 50 nm Si ₃ N ₄ film 40
3, and after forming a 70 nm phosphorus-doped polycrystalline Si film containing 4 × 10 ²⁰ / cm ^{3 of} phosphorus, the phosphorus-doped polycrystalline Si film is etched by KrF excimer laser lithography and dry etching to form source and drain wirings. Formed (not shown).

Next, a 4 nm-thick polycrystalline Si film 404 which becomes a channel layer, a 40 nm SiO ₂ film 405 which becomes a gate insulating film, and a 15 nm Si ₃ N ₄ film are formed by the CVD method.
After sequentially forming the films 406, the uppermost Si ₃ N ₄ film 406 is patterned by KrF excimer laser lithography using the Levenson-type phase shift method and dry etching (FIG. 4A). In this example, a Si ₃ N ₄ film 406 pattern having a short side length of about 150 nm was formed.

Then, the polycrystalline Si film 404 having a thickness of 4 nm is selectively oxidized by a dry oxidation method at 850 ° C. to form an element isolation SiO ₂ film 407. By this selective oxidation, the width of the channel polycrystalline Si film 404 was set back by 30 nm from the pattern edge of the Si ₃ N ₄ film 406, and a channel layer 406 having a width of 90 nm was obtained (FIG. 4B).

Next, using hot phosphoric acid at 160 ° C., Si ₃
After removing the N ₄ film 406 pattern, it was diluted with nitrogen 2
Heat treatment is performed in an oxygen atmosphere of 100% to improve the film quality of the gate insulating film 405.

Finally, 4 × 10 ²⁰ phosphorus is added by the CVD method.
100 n of phosphorus-doped polycrystalline Si film 409 containing / cm ³
After the m deposition, patterning is performed to form the gate electrode 409.
(FIG. 4 (c)).

In this example, the channel layer was selectively oxidized without using EB lithography, but a very fine channel layer having a width of 90 nm could be formed.

(Embodiment 5) Next, a fifth embodiment of an ultrathin film polycrystalline Si transistor memory manufactured by using the method shown in Embodiment 1 will be described (FIGS. 5 to 9).

The P-type (100) single crystal Si substrate 501 is thermally oxidized to form a 500 nm SiO ₂ film 502, and then a 50 nm Si ₃ N ₄ film 503 and a high concentration of phosphorus are formed by a CVD method. 70nm phosphorus-doped polycrystalline Si
The film 504 is sequentially deposited. Subsequently, the phosphorus-doped polycrystalline Si film 504 is patterned by krypton fluoride (KrF) excimer laser lithography and dry etching to form a common source line 504 (a) which serves as a source and a drain of the polycrystalline Si transistor, and data. Form line 504 (b). In this embodiment, monosilane (Si) is used to deposit the phosphorus-doped polycrystalline Si film 504.
H ₄ ) and phosphine (PH ₃ ) gas, 600 ℃
Deposition was carried out at a temperature of. Further, as shown in FIG. 5A, the wiring width was 150 nm and the wiring interval was 200 nm.

Next, an amorphous Si film having a thickness of about 2.5 nm is deposited by the CVD method, and then a 90-minute annealing method is performed.
Amorphous Si film is polycrystalline S
i film 505. In this example, disilane (Si ₂ H ₆ ) was used for depositing the amorphous Si film, and the deposition was performed at a temperature of 450 ° C.

Next, a 20 nm SiO ₂ film 506 which becomes a part of the gate insulating film and a 15 nm S film are formed by the CVD method.
The i ₃ N ₄ film 507 is sequentially deposited (FIGS. 5A and 5B).
(C)).

Next, the uppermost Si ₃ N ₄ film 507 is patterned by EB lithography and dry etching. In this embodiment, as shown in FIG. 6, a hole pattern of 100 nm × 250 nm is provided between the common source line 604 (a) and the data line 604 (b), and the adjacent data line 604 (b) is formed. In between, a rectangular hole pattern having a width of 100 nm was formed.

Next, the element isolation oxide film 508 is formed by selectively oxidizing the polycrystalline Si film 505 having a thickness of 2.5 nm by a dry oxidation method at 850.degree. Since only the polycrystalline Si film in the portion not covered with the Si ₃ N ₄ film 507 is oxidized, patterning of the channel layer 505 and insulation isolation between adjacent elements are performed in a self-aligned manner. Further, due to the lateral expansion of the element isolation oxide film 508, the channel polycrystalline Si film 505 was recessed by 20 nm from the pattern edge of the Si ₃ N ₄ film 507, and a channel layer having a width of 60 nm was obtained (FIG. 7).

In this embodiment, a laminated film of Si nitride film 507 / Si oxide film 506 is used as the gate insulating film. However, as shown in FIG. 8, a CVD-Si oxide film 509 is further laminated to form a Si oxide film. When the film 509 / Si nitride film 507 / Si oxide film 506 laminated film is used, the reliability of the gate insulating film is further improved.

Finally, 4 × 10 ²⁰ phosphorus is added by the CVD method.
/ Cm ³ containing phosphorus-doped polycrystalline Si film 510 of 70 nm
After the deposition, patterning is performed to form a word line (gate electrode) 510 (FIG. 9).

The ultra-thin film polycrystalline Si transistor memory manufactured as a prototype in this embodiment is compared with that manufactured by a conventional method.
The amount of threshold shift increased by about 2.5 times.

[0049]

According to the present invention, the channel layer width of the ultra-thin film polycrystalline Si transistor can be formed below the resolution limit of lithography, so that a sufficient threshold shift amount can be secured. Further, even if a method combining KrF excimer laser lithography and super-resolution technology (phase shift) is applied, a channel width of 100 nm or less can be realized,
Mass productivity is dramatically improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth embodiment of the present invention.

FIG. 5 is an explanatory diagram of a first step of the fifth embodiment of the present invention.

FIG. 6 is an explanatory view of a second step of the fifth embodiment of the present invention.

FIG. 7 is an explanatory diagram of a third step of the fifth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a fourth step of the fifth embodiment of the present invention.

FIG. 9 is an explanatory diagram of a fifth step of the fifth embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a conventional method.

[Explanation of symbols]

501 ... Single crystal Si substrate, 502 ... Si thermal oxide film, 50
₃ , 507 ... CVD-Si ₃ N ₄ film, 505 ... Ultra thin film polycrystalline Si, 506, 507 ... Gate oxide film, 510 ... Gate electrode, 504 (a) ... Source, 504 (b) ... Drain.

Claims (8)

[Claims] 1. A polycrystalline Si MIS field-effect transistor having a thin polycrystalline Si film as a channel layer, both ends of which are connected to a low-resistance conductive film. Insulation isolation between
A semiconductor memory device characterized in that a thermal oxide film is formed by selectively oxidizing the polycrystalline Si film. 2. The polycrystalline Si MIS field effect transistor according to claim 1, wherein a patterned Si nitride film is included as a mask film for selectively oxidizing the polycrystalline Si film. A semiconductor memory device in which at least a part of the film is a gate insulating film. 3. The polycrystalline Si MIS field effect transistor according to claim 2, wherein the channel width of the polycrystalline Si film serving as a channel layer is smaller than the width of the patterned Si nitride film. 4. The film thickness of the channel layer is 1 nm or more and 10 n.
4. The semiconductor memory device according to claim 1, wherein the width of the channel layer is 100 nm or less when m or less. 5. The method according to claim 1, wherein the gate insulating film is a Si oxide film or a composite film of a Si oxide film and a Si nitride film, and the lowermost insulating film in contact with the channel layer is a Si oxide film. The semiconductor memory device described. 6. The gate insulating film according to claim 5, wherein
The film thickness of the lowermost Si oxide film in contact with the channel layer is 50 n
The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a thickness of m or less. 7. Polycrystalline Si according to claim 1, 2 or 3.
A semiconductor memory device using a MIS field effect transistor as a memory element. 8. A step of processing a low resistance conductive film on a Si nitride film into a predetermined shape, a polycrystalline Si film, a Si oxide film, and S.
It includes a step of sequentially forming an i-nitride film, a step of processing the Si nitride film into a predetermined shape, and a step of selectively oxidizing the lower-layer polycrystalline Si film using the Si nitride film as a mask. And a method for manufacturing a semiconductor memory device.