JPH08328562A - Signal processor - Google Patents

Abstract

PURPOSE: To prevent the occurrence of a noise in an output signal when a signal processing parameter and a signal processing program are revised by adding an envelope signal generation means generating an envelope signal changing facing to 0 or 1. CONSTITUTION: Respective parameter values are not inputted directly to multipliers 52, 54, but are connected through envelope generators 70, 71. Then, the envelope signal changing facing to 0 or 1 is generated according to a set envelope parameter, and by multiplying an output signal of a signal processing means by the generated envelope signal, an output signal level is controlled. Thus, for instance, when a signal processing parameter is revised, first of all, the envelope parameter is revised, and the output level of the signal processing means is made zero while spending a prescribed time so as to cause no noise. Then, the signal processing parameter is revised, and thereafter, the envelope parameter is revised, and the output level is returned to an original level while spending the time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device, and more particularly to a signal processing device configured so that noise does not occur in an output signal when a signal processing parameter or a signal processing program is changed.

[0002]

2. Description of the Related Art Conventionally, a sound effect imparting device has been proposed as a signal processing device using a DSP (digital signal processor). For example, for an analog or digital tone signal or voice signal input from the outside,
By the processing based on the DSP program, acoustic effects such as reverberation effect, delay effect, and modulation effect could be added. FIG. 8 is a functional block diagram showing a signal processing function of a sound effect imparting apparatus using a conventional DSP. The effect 1 process 50 and the effect 2 process 56 are process blocks for imparting acoustic effects such as reverberation effect, delay effect, and modulation effect, and the effect imparting characteristics can be changed by changing the effect process parameters. P11, P12, P21,
P22 is a level control parameter which is externally set for level control, and each parameter is multiplied by the signal after processing or before processing by the multipliers 52, 54, 58 and 60, and by the adders 55 and 61. Each is added and mixed.

[0003]

In the conventional signal processing apparatus as described above, for example, when performing on / off control of the sound effect by interlocking with the switch of the panel, the parameter P11 corresponding to the state of the switch is used. When P1 and P12 are changed to "1" and "0" or vice versa, there is a problem that the value of the output signal changes abruptly and pulse noise is generated. Further, even when the effect imparting parameter of each processing block is changed during signal processing, the value of the output signal changes abruptly, and similarly, pulse noise is generated. An object of the present invention is to improve the above-mentioned problems of the prior art and provide a signal processing device capable of changing a signal processing parameter or a processing program without generating noise during signal processing. .

[0004]

According to the present invention, in a signal processing device having a signal processing means for processing an input signal, the signal processing apparatus moves toward 0 or 1 according to the envelope parameter setting means and the set envelope parameter. It has an envelope signal generating means for generating a changing envelope signal, and a multiplying means for multiplying the output signal of the signal processing means by the generated envelope signal.

[0005]

According to the present invention, in the signal processing device, an envelope signal which changes toward 0 or 1 according to the set envelope parameter is generated, and the output signal of the signal processing means is multiplied by the generated envelope signal. Control the output signal level. Therefore, for example, when changing the signal processing parameter, first, the envelope parameter is changed, and a predetermined time is taken so that noise is not generated, and the output level of the signal processing means is set to 0.
To Next, the signal processing parameter is changed, and then the envelope parameter is changed, and the output level of the signal processing means is returned to the original level by taking a predetermined time so that noise is not generated. If the signal processing parameter is changed in such a procedure, a sudden change in the signal level does not occur, so that the generation of noise can be prevented.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing an example of the configuration of a system using a sound effect imparting device to which the present invention is applied. The effector 1 is a sound effect imparting device using a DSP as will be described later, and includes a microphone 3 or an electronic musical instrument 4.
The analog signal from is input, a desired acoustic effect is added, and the analog signal is output to the amplifier 5. The amplifier 5 amplifies the signal and is output from the speaker 6. Computer 2 which is a control device
Is for controlling the effector 1. For example, an ordinary personal computer to which a well-known MIDI interface circuit is added can be used. In the computer 2, for example, a DSP source program for executing signal processing with desired characteristics is input and edited, assembled, and converted into a DSP machine language. Then, the generated machine language or parameter is converted into, for example, a MIDI exclusive message and transferred to the effector 1.

FIG. 1 is a block diagram showing the configuration of the effector 1. The CPU 10 is a central processing unit that controls the entire effector based on a control program stored in the ROM 11. The RAM 12 is used as a work area and a buffer, and may be backed up by a battery. The MIDI interface circuit 13
Sends and receives messages with external MIDI equipment. The panel circuit 14 includes various switches and liquid crystal or LE.
It is composed of a display device for displaying characters and figures by D or the like.

The A / D converter 15 converts an analog tone signal input from the microphone 3 or the electronic musical instrument 4 into a digital signal. The DSP 16 has the configuration described below.
The digital tone signal is processed, and filtering or effects such as reverberation, delay, and modulation are performed. DSP-RA
M17 stores a DSP program or tone signal data being processed. The D / A converter 18 converts the digital musical tone signal processed by the DSP into an analog signal. The A / D converter 15 and the D / A converter 18 are controlled by a timing control circuit (not shown) to control the CPU 1
A / D, D / at a predetermined sampling cycle without going through 0
Performs A conversion and data transfer with the DSP. Bus 1
Reference numeral 9 connects each circuit in the effector 1.

FIG. 3 is a block diagram showing an example of the configuration of a DSP usable in the present invention. The configuration of the DSP 16 can be divided into three parts: a data storage and input / output unit, a calculation unit, and a control unit. The data RAM 30, which is a data storage unit, is connected to the data bus 37,
A memory having a storage capacity of word × 24 bits,
Ring buffer control is performed so that the data stored in each sampling cycle moves to the previous address. The coefficient RAM 39 is connected to the coefficient bus 38 by 1
It is a memory having a storage capacity of 28 words × 16 bits. This coefficient RAM stores parameters for effect imparting processing or envelope parameters for level control.

The delay RAM 34 is a built-in or externally attached RAM having a relatively large capacity, and has a structure of, for example, 64 kilowords × 24 bits. It is functionally the same as the data RAM 30, and the data moves to the previous address in each sampling cycle in the ring buffer format. If the sampling cycle is set to about 44 kHz, the delay RAM 34 can delay the signal for about 1.5 seconds at the maximum. The address buffer 31 comprises a plurality of registers, and the delay RAM writing circuit 3
2. The delay RAM read circuit 33 uses address buffers to control writing and reading of the delay RAM 34. The input circuit 35 and the output circuit 36 respectively input data from the bus 19 to the data bus 37 in the DSP and output data in the reverse direction.

The multiplier 40, which is an arithmetic unit, is provided in the data bus 3
The data on 7 is multiplied by the coefficient on the coefficient bus 38. The bit shift circuit 41 shifts the output data of the multiplier rightward and leftward by a predetermined number of bits (multiplies by a power of 2). Adder 4
2 adds the output of the bit shift circuit 41 and the output of the accumulator 44 and outputs the output to the accumulator 44.
And output to the register 43.

The CPU 45 in the DSP, which is a control unit, issues an instruction R
The DSP programs are fetched one by one from the OM 46 or the instruction RAM 47, decoded, and each block in the DSP is controlled via the control bus 48. The instruction ROM 46 and the instruction RAM 47 are external (DSP-R
(Corresponding to AM17), and the instruction RAM 47 has a path (not shown) for writing the DSP program from the external bus 19.

FIG. 9 is realized by the DSP 16.
It is a functional block diagram which shows a part of signal processing function regarding this invention. The same functional blocks as in the conventional example of FIG. 8 are assigned the same numbers. The difference from the prior art is that the respective parameter values are not directly input to the multipliers 52 and 54, but are connected via the envelope generators 70 and 71. This envelope generator 70, 71
Have a configuration as shown in the functional block diagram of FIG. 10, for example. In FIG. 10, the envelope generation parameter P is multiplied by −1 and input to the adder 74. The previous envelope value read from the address "00" of the delay circuit 74 using the data RAM 30 in the DSP is multiplied by 1 and is also input to the adder 74. The output of the adder 74 is converted into an absolute value by the absolute value circuit, and the data RA
It is written in the address "01" of M30 and is output as an envelope. (The multiplication process in FIG. 10 depends on the structure of the DSP and has no meaning.) FIG. 11 is a waveform diagram showing the operation of the envelope signal generator shown in FIG. When the envelope parameter P set from the outside is changed from k to -k at time t1, the envelope output Q linearly increases from 1 in a state of almost 0 toward an increase rate proportional to k.
For example, the sampling period is 40 kHz and P is −
If (2 to the minus 12th power = about (1/4) × 10 to the minus the 3rd power) is set, Q reaches 1 after about 4000 sampling cycles, so the time required for Q to reach 1 is 4000 / (40 × 1000) = 100 milliseconds.
It should be noted that the limiter function is activated to output the maximum value (1) when the addition result exceeds the maximum value (1) in the adder.

Next, at time t2, P changes from -k to k / 2.
When changed to, the envelope output Q is from 1 to k
It decreases linearly toward 0 with a descending rate proportional to / 2. In this case, Q is reduced to -1 if there is no absolute value circuit, but even if the output of the adder 74 becomes negative due to the action of the absolute value circuit 75, it is always corrected to a positive value, so the next calculation In, the value of P will be subtracted from this positive value. Therefore, strictly speaking, the value of Q does not always become 0, but takes a value between the absolute value of P and 0. However, since the value of P is very small, even if this value is used as the envelope value, the level of noise generated will be a level that can be ignored and there is no problem. Also, Q may be set to 0 by using a "rounding function" for forcibly resetting the lower predetermined bits to 0. For example, if P is set to-(2 to the 13th power = about (1/8) x 10 to the 3rd power), then about 8
Since Q reaches almost 0 after 000 sampling cycles,
The required time is 8000 / (40 × 1000) = 200 milliseconds. The signal level is controlled by multiplying the tone signal by the envelope signal Q.

FIG. 4 is a flowchart showing the main processing of the CPU of the effector 1. In step S10, it is determined whether or not there is a change in the state of the panel of the effector. When a change in the state of the switch or the like is detected, the process proceeds to step S11, and the coefficient data (effect imparting parameter) stored in the RAM 12 ) Is updated, and the process proceeds to step S16. In step S12, it is determined whether or not a MIDI message is received from the outside,
If the result is affirmative, the process proceeds to step S13, and it is determined whether the received message is a program (that is, coefficient data). If the result is affirmative, the process proceeds to step S14, but if negative, step S15. Move to. In step S14, a predetermined number of bytes for the program in the received data is stored in the receive buffer. Further, in step S15, a predetermined number of bytes corresponding to the coefficient data of the received data is stored in the reception buffer.

In step S16, in order to set the output signal level from the DSP to 0, only the envelope parameter in the coefficient data is changed to a positive value so that the envelope value changes toward 0, and the DSP is changed. Transfer to. In step S17, the process waits for the time required for the envelope value to reach 0. This time is calculated from the parameter value and the sampling period as described above. In step S18, the coefficient data or the program to be transferred stored in the RAM is processed by the DSP.
Transfer to. In step S19, in order to restore the output signal level from the DSP, only the envelope parameter in the coefficient data is changed to a negative value such that the envelope value changes toward 1, and the result is transferred to the DSP. .

FIG. 5 is a flow chart showing the processing of the CPU 45 in the DSP. In step S20, the in-DSP CPU 45 executes the signal processing program stored in the instruction RAM only once based on the activation signal input from the outside every sampling period. This processing is executed in a time shorter than the sampling cycle. In step S21, it is determined whether or not there is a coefficient data transfer request from the CPU of the effector, and if the result is affirmative, the process proceeds to step S22. In step S22, a predetermined number of bytes of coefficient data is received from the outside,
Store in the coefficient RAM 39. In step S23, it is determined whether or not there is a program transfer request, and if the result is affirmative, the process proceeds to step S24 to receive a predetermined number of bytes of program data from the outside, and execute an instruction RA.
Store in M47. With the configuration and processing as described above, it becomes possible to convert a program arbitrarily generated by the user into a machine language, transfer it to the DSP in the effector, and execute signal processing.

FIG. 6 is a flowchart showing a part of the signal processing executed in step S20 of FIG.
This process corresponds to the functional block diagram of FIG. 9, and in step S30, a process corresponding to the effect 1 process 50 in the functional block diagram is performed. In step S31, the envelope signal (E1) is generated by the process described later, and in step S32, the signal is multiplied by the signal after the process of step S30. Step S
At 33, an envelope signal (E2) is generated and multiplied at step S34 by the signal before the processing at step S30. In step S35,
The multiplication results of step S32 and step S34 are added, and the process proceeds to the effect providing process of the next stage. Thereafter, the same processes as in steps S30 to S35 are repeated as necessary to output the result.

FIG. 7 is a flow chart showing the envelope generation processing in step S31 or step S33 of FIG. In step S40, the envelope parameter P is read from the coefficient RAM. In step S41, the envelope value Q stored in the data RAM is read and added to the read P.
In step S42, the absolute value of the addition result is written as Q in the envelope storage address of the data RAM.

FIG. 12 is an explanatory diagram showing an example of a program for executing the level control. This program executes the processes corresponding to steps S31 and S32 of FIG. 6, for example. The envelope parameter P is stored in advance at address 01 (C (01)) of the coefficient RAM, and “1” is set in C (02) and C (03). Address 00 (D (00)) and address 01 (D (01)) of the data RAM are used to store the envelope value, and D (02) is the tone signal value after the effect imparting process,
It is assumed that the output signal value to the next stage is stored in D (03). The top three lines are programs for performing envelope signal generation processing, and correspond to the functional block diagram of FIG.

The first "ADD" multiplies the content (P) of C (01) by "-1", adds the result to the value of the accumulator, and stores it again in the accumulator. The value of the accumulator is reset to "0" in advance. The multiplication by "-1" depends on the DSP specifications, and the sign of P may be reversed by setting it to "1". The next "ADR" reads the envelope value Q from D (00) (as described above, the value written in D (01) in the previous process has moved), and reads from C (02). Multiply “1”, add the multiplication result and the value of the accumulator, and store the result in the register 43. "OU
"T" stores the absolute value of the contents of the register as the envelope value Q in D (01).

The lower three lines are programs for performing signal level control processing, and correspond to the multiplier shown in FIG. The first "AD
In “R”, the envelope value Q is read from D (01) and multiplied by “1” read from C (03),
The result is stored in the register 43 (that is, Q is transferred to the register). In the next "ADR", the tone signal is read from D (02), multiplied by Q stored in the register, and the result is stored again in the register 43. At the last "OUT", the contents of the register are changed to the data RA.
Store in address D (03) of M. A program that transfers the generated envelope value to the coefficient RAM and multiplies it with the signal as a coefficient is also conceivable. The signal level control is executed by the above processing.

Although the embodiment has been described above, the following modifications are also possible. In the functional block diagram of the embodiment shown in FIG. 9, the signal to which the effect is applied and the signal to which the effect is not applied are cross-faded, but even if the output of the signal to which the effect is applied is simply controlled by the envelope. Good. That is, in FIG. 9, the parameter P12, the envelope generator E2 (71), the multiplier 54, and the adder 55 may be omitted. Further, in FIG. 9, P12 may be an inverted (1-P11) signal of P11, and instead of the envelope generator E2 (71), a value obtained by subtracting the output of the envelope generator E1 (70) from 1 is multiplied. It may be added to the container 54. Although an example using a DSP is disclosed as an embodiment, the present invention can be implemented by a hardware circuit that processes a digital signal, and can also be implemented by an analog processing circuit. Further, the present invention can be applied to any signal processing circuit and device such as a filter circuit and an effect adding circuit in an electronic musical instrument, as well as a single acoustic effect imparting device.

[0024]

As described above, in the signal processing device of the present invention, even if an external device such as an amplifier or a speaker is connected, the signal is generated in a short time without generating noise. It is possible to change the processing parameters or the signal processing program itself. Therefore, if the sound effect imparting system is configured by using the signal processing device, the effect characteristics can be freely switched during the performance, and it is possible to impart a more varied sound effect to the musical tone signal. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an effector 1 of the present invention.

FIG. 2 is a block diagram showing a configuration of a sound effect imparting system.

FIG. 3 is a block diagram showing an example of the configuration of a DSP.

FIG. 4 is a flowchart showing a main process of a CPU of an effector.

FIG. 5 is a flowchart showing the processing of the CPU 45 in the DSP.

FIG. 6 is a flowchart showing the signal processing in S20 of FIG.

FIG. 7 is a flowchart showing an envelope generation process.

FIG. 8 is a functional block diagram showing a signal processing function of a conventional acoustic effect imparting apparatus.

FIG. 9 is a functional block diagram showing a part of a signal processing function according to the present invention, which is realized by the DSP 16.

FIG. 10 is a functional block diagram showing a configuration of an envelope generator of the present invention.

FIG. 11 is a waveform diagram showing the operation of the envelope signal generator.

FIG. 12 is an explanatory diagram showing an example of a program for executing level control.

[Explanation of symbols]

1 ... effector, 2 ... computer, 3 ... microphone, 4 ...
Electronic musical instrument, 5 ... Amp, 6 ... Speaker, 10 ... CPU,
11 ... ROM, 12 ... RAM, 13 ... MIDI interface, 14 ... Panel, 15 ... A / D converter, 16 ...
DSP, 17 ... DSPRAM, 18 ... D / A converter, 1
9 ... Bus

Claims (3)

[Claims] 1. A signal processing device having signal processing means for processing an input signal, wherein an envelope parameter setting means and an envelope for generating an envelope signal changing toward 0 or 1 according to the set envelope parameter. A signal processing device comprising: a signal generating means; and a multiplying means for multiplying an output signal of the signal processing means and a generated envelope signal. 2. The signal processing means is composed of a digital signal processor capable of externally setting at least one of a signal processing parameter and a program, and when the signal processing parameter or the program is changed,
Set the envelope parameter that the envelope signal changes toward 0, transfer the signal processing parameter or program to the digital signal processor after the envelope signal becomes 0, and then set the envelope parameter that the envelope signal changes toward 1. The signal processing device according to claim 1, further comprising change control means for setting. 3. The envelope signal generating means includes adding means for adding an envelope parameter to a previous envelope current value, and absolute value output means for outputting an absolute value of the addition result as an envelope current value. The signal processing device according to claim 1.