JP4400373B2 - Data processing circuit - Google Patents

Description

  The present invention relates to a data processing circuit suitable for use in generating a digital musical tone signal.

  When a musical sound signal is generated by digital technology, a digital musical sound signal (PCM (Pulse Code Moduration) data) generated by a tone generator circuit or PCM data received from the outside is input to an effect applying circuit, and an effect ( Effect) and a stereophonic effect. This effect applying circuit is configured to include a plurality of digital filters such as an FIR filter and an IIR filter, and each filter is generally configured by a DSP (digital signal processor).

  As is well known, the DSP has a program RAM (random access memory), a coefficient RAM, a data RAM in which musical tone data is temporarily stored, an arithmetic circuit, and the like, and from the data RAM based on a program in the program RAM. Data is read out, and a filter operation is performed on the musical tone data based on the program read from the program RAM and the coefficient read from the coefficient RAM in the arithmetic circuit. Then, the calculation result is converted into an analog signal by a next-stage DAC (digital / analog converter) and output to a speaker.

Further, in the processing of PCM data in the DSP, the coefficients of the arithmetic circuit described above are often changed in order to generate various musical sounds. This process is performed by rewriting the coefficient RAM with coefficients output from an external CPU (central processing unit). However, if the coefficient RAM is rewritten suddenly, there is a problem that noise is added to the PCM data. Therefore, two coefficient RAMs are provided, the coefficient to be rewritten is written in the second coefficient RAM, and coefficient interpolation is performed to gradually change the coefficient from the coefficient of the first coefficient RAM currently used to the coefficient of the second coefficient RAM. A circuit is provided.
Patent documents 1 to 3 are known as conventional technical documents related to the present application.
Japanese Patent No. 3230413 Japanese Patent No. 3013675 Japanese Patent No. 3116447

  By the way, in the above-described DSP, there is a case where a program is changed during the processing of musical sound data. In this case, the coefficient is also changed at the same time. In this program change, the program output from the CPU is written into the program RAM, and the output of the program RAM is changed to NOP (NO-operation) during this write operation. At this time, a coefficient is simultaneously output from the CPU, and this coefficient is written into the above-described second coefficient RAM.

However, in such a program change process, the coefficient of the program before the change is in the first coefficient RAM, and the coefficient of the program after the change is written in the second coefficient RAM. Thus, the interpolation processing described above is performed between the coefficient and the coefficient after the program change, and the coefficient obtained after the interpolation processing is completely different from the original coefficient. As a result, noise is present in the output PCM data. It will be included.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a data processing circuit in which noise is not included in the output even when a program is changed.

The present invention has been made to solve the above problems, and the present invention provides a program memory in which a program is stored, a coefficient memory in which a coefficient is stored, a program in the program memory, and a program in the coefficient memory. In a data processing circuit comprising a program counter for reading a coefficient, and an arithmetic circuit that operates according to the program and the coefficient, a new coefficient memory for storing the new coefficient after the change of the coefficient, and an old one before the change of the coefficient An old coefficient memory in which coefficients are stored, a coefficient interpolating means for sequentially generating coefficients from the coefficients in the old coefficient memory toward the coefficients in the new coefficient memory, and outputting them to the arithmetic circuit; the program and the coefficients Upon receiving the change instruction, and a rewriting means for rewriting said new coefficient memory are both new coefficients the old coefficient memory A data processing circuit according to claim Rukoto.

The present invention includes a program memory in which a program is stored, a coefficient memory in which a coefficient is stored, a program counter that reads a program in the program memory and a coefficient in the coefficient memory, and an operation that operates according to the program and the coefficient A new coefficient memory for storing the new coefficient after the change of the coefficient, an old coefficient memory for storing the old coefficient before the change of the coefficient, the new coefficient and the old An intermediate coefficient memory in which a coefficient interpolated with the coefficient is stored, and a subtracting means for obtaining 1 / X (X is a real number greater than 1) of a difference between the coefficient in the new coefficient memory and the coefficient in the old coefficient memory; The output of the subtracting means and the coefficient in the intermediate coefficient memory are added, and the addition result is output to the arithmetic circuit and written to the intermediate coefficient memory. The number interpolating means, when receiving a change instruction of the program and coefficients, said new coefficient memory, the old coefficient memory and a data processing circuit which is characterized by comprising a rewriting unit operable to rewrite the intermediate coefficient memory are both new coefficients .
The present invention receives a change instruction of the program and the coefficient, the data processing circuit according to claim 1 or claim 2, characterized in that it comprises a means for outputting a command for stopping the operation to the arithmetic circuit.

  According to the present invention, there is an advantage that noise is not included in the output even when the program is changed, and it is particularly suitable for generating a digital musical tone signal.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a musical tone signal generation circuit G to which a data processing circuit (hereinafter referred to as a DSP (digital signal processor)) according to an embodiment of the present invention is applied, and FIG. 2 is a musical tone signal generation shown in FIG. 2 is a block diagram illustrating a configuration of a mobile phone using a circuit G. FIG. In FIG. 2, reference numeral 1 denotes a CPU (central processing unit) that controls each part of the circuit, and performs normal communication and call processing, as well as game program processing. Reference numeral 2 denotes a ROM (read only memory) in which a program executed by the CPU 1, that is, a communication / call processing program, a game program, a music reproduction processing program, and the like are stored. Reference numeral 3 denotes a non-volatile RAM (random access memory) for data storage, and the CPU 1 temporarily stores data during each process.

4 is an input unit provided with a numeric keypad for inputting a telephone number and various function keys , and 5 is a display unit using a liquid crystal display. 6 is a communication unit having an antenna 7, and transmitted from the antenna 7 by modulating a carrier wave by transmission data, and outputs the demodulated incoming signal received through the antenna 7 to the CPU1 or audio processing section 8 . The audio processing unit 8 converts the audio signal output from the microphone 9 into digital data, further compresses it and outputs it as transmission data to the communication unit 6, and decompresses the compressed audio data output from the communication unit 6, The sound signal is converted and output to the speaker 10. The musical tone signal generation circuit G generates various musical tone signals such as a ringing melody, game effect music, and viewing music, and outputs them to the speaker 16.

Next, the tone signal generation circuit G will be described in detail with reference to FIG.
In FIG. 1, reference numeral 12 denotes a buffer register in which various data and control commands supplied from the CPU 1 via the bus line B are temporarily stored. A tone generator circuit 13 receives an incoming melody generation instruction from the CPU 1 via the buffer register 12, and generates and outputs a digital musical tone signal (PCM data) of the incoming melody. When receiving a game sound effect generation command from the CPU 1, PCM data of the game sound effect is generated and output. The DSP 14 adds an effect, a stereophonic effect (3D), and a wide stereo effect to the digital musical sound signal output from the sound source circuit 13 and outputs the signal to a DAC (digital / analog processor) 15. The DAC 15 converts the digital tone signal output from the DSP 14 into an analog tone signal and outputs the analog tone signal to the speaker 16.

  Next, in the DSP 14, 21 is a data RAM, which temporarily stores PCM data output from the tone generator circuit 13, and outputs the stored data to the arithmetic circuit 23 in accordance with a program output from the program RAM 22. The arithmetic circuit 23 performs an operation designated by the program output from the program RAM 22 on the PCM data output from the data RAM 21 and outputs the result. In this case, the coefficient K output from the selector 43 is used as the calculation coefficient. A buffer memory 24 temporarily stores the PCM data output from the arithmetic circuit 23 and outputs it to the DAC 15 at the timing of the clock pulse CLK1. Here, the clock pulse CLK1 is a clock pulse having the same frequency (48 KHz) as the sampling frequency of the PCM data.

The program RAM 22 is a RAM in which an effect program, a stereophonic sound effect program, a wide stereo effect program, and the like are stored in advance, and each program can be rewritten by a program output from the CPU 1. The program RAM 22 can store a program having a maximum of 768 steps, and each step is sequentially read and output in accordance with address data output from the program counter 27. For example, one or more of an effect program, a stereophonic effect program, a wide stereo effect program, and the like are stored in 768 steps. Then, according to the count output of the program counter 27 supplied to the address terminal, the effect program is read out, whereby an effect is given to the PCM data output from the data RAM 21 or the stereophonic sound effect program is read out. In addition, the wide stereo effect program is read out, and thereby the wide stereo effect is added to the PCM data. The program counter 27 is a 768-ary counter, and repeatedly outputs a count output of 0 to 767 in accordance with a clock pulse CLK2 having the following frequency.
Frequency = 48KHz × 768 = 36.864MHz

  31 to 34 are coefficient RAMs for storing calculation coefficients used in the calculation circuit 23. The coefficient RAM (previous stage) 31, the coefficient RAM (new) 32, and the coefficient RAM (middle) 34 are each 768 words (1 Word = 16 bits) and the coefficient RAM (old) 33 has a storage capacity of 768 bytes. Here, the number of bits of the coefficient is 16, so that the coefficient RAM (previous stage) 31, the coefficient RAM (new) 32, and the coefficient RAM (intermediate) 34 can each store 768 coefficients, and the coefficient RAM (Old) 33 can store the upper 8 bits of 768 coefficients. Further, the count output of the program counter 27 is applied to the address terminals of the coefficient RAMs 31 to 34, and data writing / reading is performed with respect to the address specified by the count output of the program counter 27. That is, each coefficient in the coefficient RAMs 31 to 34 corresponds to each program step of the program RAM 22.

Further, the coefficient RAM (previous stage) 31 is rewritten by the coefficient output from the CPU 1, and the coefficient RAM (new) 32 is rewritten by the coefficient output from the coefficient RAM (previous stage) 31. The coefficient RAM (old) 33 is rewritten by the coefficient output from the coefficient RAM (previous stage) 31 or the selector 43. In this case, the input data is switched by the selector 36. The coefficient RAM (intermediate) 3 4 is rewritten by the coefficient output from the coefficient RAM (front) 31 or selector 43. In this case, input data is switched by the selector 37.

  Reference numeral 40 denotes a coefficient interpolation circuit. If the coefficient is suddenly changed when the coefficient is changed, noise may be included in the output PCM data. Therefore, 256 clocks of the clock pulse CLK1 from the coefficient before the change to the coefficient after the change are included. A circuit for gradually changing the coefficient over time, a subtracting circuit 41 for subtracting the output of the coefficient RAM (old) 33 from the upper 8 bits of the output of the coefficient RAM (new) 32, and the output of the subtracting circuit 41 And an adder circuit 42 for adding the output of the coefficient RAM (intermediate) 34, a selector 43 for selecting one of the output of the coefficient RAM (new) 32 or the output of the adder circuit 42, and outputting the selected coefficient K to the arithmetic circuit 23; And an end determination circuit 44 for determining the end of interpolation. The operation of the coefficient interpolation circuit 40 will be described in detail later.

  Reference numerals 51 and 52 denote a start register and an end register, respectively. When the program is changed, the start address and end address of the program to be changed output from the CPU 1 are written. For example, when the effect program stored in the addresses 0 to 150 of the program RAM 22 is rewritten, “0” is written in the start register 51 and “150” is written in the end register 52. A comparison circuit 54 compares the output of the program counter 27 with the data of the start register 51 and the end register 52. The output of the program counter 27 is between the data of the start register 51 and the data of the end register 52. “1” is output in some cases, and “0” is output in other cases.

  55 is an AND gate (corresponding to the number of bits of the output of the program RAM 22). When the output of the comparison circuit 54 is "1", it is closed and outputs data "0 (all bits" 0 ")" When the output of the comparison circuit 54 is “0”, it is in an open state, and the program steps output from the program RAM 22 are output to the data RAM 21 and the arithmetic circuit 23. Since data “0” is a NOP (No Operation) instruction, malfunction during rewriting can be prevented. (If the NOP instruction is not “0”, the AND gate 55 changes it according to the bit arrangement.)

Next, the operation of the above-described tone signal generation circuit G will be described.
First, it is assumed that an effect program is stored in addresses 0 to 150 of the program RAM 22 and a stereophonic sound effect program is stored in addresses 151 to 767. In this case, the coefficients of the same effect program are stored in the addresses 0 to 150 of the coefficient RAMs 31, 32, and 34, respectively, and the coefficients of the same stereophonic effect program are stored in the addresses 151 to 767, respectively. . The coefficient RAM (old) 33 stores the upper 8 bits of each coefficient in the coefficient RAM (previous stage) 31.

  In this state, for example, when an incoming melody generation command is output from the CPU 1 to the tone generator circuit 13, the tone generator circuit 13 generates a digital musical tone signal (PCM data) of the incoming melody and outputs it to the DSP 14. The outputted PCM data is temporarily stored in the data RAM 21, and at the same time, the program counter 27 starts to count up the clock pulse CLK2. When the program counter 27 counts up with the clock pulse CLK 2, program steps are sequentially output from the program RAM 22 and supplied to the data RAM 21 and the arithmetic circuit 23 via the AND gate 55.

  On the other hand, when the program counter 27 counts up the clock pulse CLK2, the coefficients are sequentially read out from the coefficient RAM (new) 32, the coefficient RAM (old) 33, and the coefficient RAM (intermediate) 34, and the subtraction circuit 41 and the addition circuit. 42 is output. However, as described above, in the state where the coefficient is not changed, the upper 8 bits of the data of the coefficient RAM (new) 32 and the data of the coefficient RAM (old) 33 are the same. Therefore, the output of the subtraction circuit 41 is “0”. " As a result, the output data of the coefficient RAM (intermediate) 34 is output from the adder circuit 42, supplied to the arithmetic circuit 23 via the selector 43, and written to the coefficient RAM (intermediate) 34 via the selector 37.

As described above, when the program counter 27 counts up by the clock pulse CLK2, the program read from the program RAM 22 is sequentially sent to the data RAM 21 and the arithmetic circuit 23, and is read from the coefficient RAM (intermediate) 34. coefficients is Ru transmitted through the coefficient interpolation circuit 40 to the arithmetic circuit 23. Thereby, the effect program and the stereophonic sound effect program are repeatedly executed in sequence. The coefficient read from the coefficient RAM (intermediate) 34 is returned to the coefficient RAM 34 again and written to the same address. Therefore, there is no change in the data of the coefficient RAM (intermediate) 34.

Next, the operation for changing the coefficient will be described.
When the coefficient is changed, first, the changed coefficient (referred to as a new coefficient) output from the CPU 1 is written in the coefficient RAM (previous stage) 31. For example, when the coefficient of the effect program is changed, the new coefficient output by the CPU 1 is written to addresses 0 to 150 of the coefficient RAM (previous stage) 31.

Each time the coefficient in the coefficient RAM (new) 32 is read by the count output of the program counter 27, it is compared with the new coefficient read from the coefficient RAM (previous stage) 31 by the comparator and does not match. The coefficient in the coefficient RAM (new) 32 is rewritten with a new coefficient. The rewritten new coefficient is output to the subtraction circuit 41. The subtracting circuit 41 subtracts 8 bits of the coefficient before change (referred to as old coefficient) output from the coefficient RAM (old) 33 from the higher 8 bits of the new coefficient. The adder 42 adds the subtraction result to the lower 8 bits of the output (16 bits) of the coefficient RAM (intermediate) 34. The sign is extended to the upper bits. FIG. 5 shows a specific configuration example. The subtraction circuit 41 subtracts the input B (8 bits) from the input A (8 bits). The output A-B is 9 bits by adding a sign (SIGN 1 bit) (because it becomes a negative value when B> A). The adder 42 adds the input A (16 bits) and the input B (16 bits). In the input A, the output of the subtracter 41 is input as difference data. The sign (SIGN) is input to 8 bits from the MSB of input A, and the lower order is input to 8 bits below it. That is, the difference data obtained by shifting the output of the subtracter 41 by 8 bits in the lower direction is input to the input A of the adder 42. Here, as is well known, when a binary number is shifted by 8 bits in the lower direction, the binary number is divided by “256”. Therefore, the upper 8 bits of the old coefficient are changed from the upper 8 bits of the new coefficient. Subtracting and inputting the lower 8 bits of the subtractor 42 means giving the next difference data to the input A of the adder 42.
Difference data = (new coefficient−old coefficient) / 256 (1)

The adder circuit 42 adds the above difference data to the coefficient output from the coefficient RAM (intermediate) 34 and outputs the addition result of the following equation (referred to as an intermediate coefficient) to the arithmetic circuit 23 via the selector 43.
Intermediate coefficient = old coefficient + difference data (2)
At this time, the selector 37 is switched, and the intermediate coefficient output from the selector 43 is written into the coefficient RAM (intermediate) 34.

Next, when the same new coefficient is read again from the coefficient RAM (new) 32 after one clock of the clock pulse CLK1 (after 768 clocks of the clock pulse CLK2), the subtraction circuit 41 performs the subtraction of the above equation (1). The difference data is further added to the intermediate coefficient (old coefficient + difference data) read out from the coefficient RAM (intermediate) 34 to obtain the next intermediate coefficient.
Intermediate coefficient = old coefficient + 2 x difference data (3)
The intermediate coefficient is output to the arithmetic circuit 23 via the selector 43 and written to the coefficient RAM (intermediate) 34.

  Thereafter, the same operation is repeated every time one cycle of the clock pulse CLK1 elapses, whereby the intermediate coefficient output from the selector 43 is changed from the old coefficient to the new coefficient as shown in FIG. It increases monotonously (when the difference data is positive) or decreases (when the difference data is negative) at the timing of the clock pulse CLK1 and at the pitch of the difference data.

  When the difference between the intermediate coefficient and the new coefficient becomes smaller than the difference data of the above equation (1), the end determination circuit 44 detects this and outputs an end signal. When this end signal is output, the selectors 36, 37 and 43 are switched, and the new coefficient in the coefficient RAM (new) 32 is written into the coefficient RAM (old) 33 (upper 8 bits) and the coefficient RAM (intermediate) 34. It is. If the coefficient RAM (previous stage) 31 is rewritten by the CPU 1 before the end signal is output, the upper 8 bits of the intermediate coefficient at that time are written in the coefficient RAM (old). As a result, thereafter, as shown in FIG. 3B, the intermediate coefficient sequentially changes from the intermediate coefficient toward a new new coefficient (new coefficient).

  Although the above description is for one address of the coefficient RAM 31 (previous stage), the same operation is performed for the coefficients of other addresses. That is, when a new coefficient is written by the CPU 1 at, for example, addresses 0 to 150 of the coefficient RAM (previous stage) 31, the above-described interpolation processing by monotonically increasing or decreasing is performed for each of the new coefficients at addresses 0 to 150. Is called.

Next, the case of program change will be described with reference to the flowchart of FIG. When changing the program, the coefficients are usually changed.
When the program and coefficient are changed, the CPU 1 first outputs data specifying the rewrite range. The output data is written into the start register 51 and the end register 52 (step S1). For example, when the effect program is rewritten, the CPU 1 outputs the address 0 and the address 150, and these addresses are written in the start register 51 and the end register 52. When the start register 51 and the end register 52 are written, “1” is output from the comparison circuit 54 when the output of the program counter 27 is between the start address and the end address. All bits "0" (NOP instruction) are output from (step S2).

  When the program and the coefficient are changed, the selectors 36 and 37 are switched, and the output of the coefficient RAM (previous stage) 31 is written in each of the coefficient RAMs 32 to 34. That is, the coefficient interpolation process in the coefficient interpolation circuit 40 is not substantially performed (step S3).

  Next, the CPU 1 outputs a new program and a new coefficient. The output new program is written into the program RAM 22, and a NOP instruction is output from the AND gate 55 during this writing. Therefore, the arithmetic circuit 23 does not output an abnormal output during writing. Further, the new coefficient output from the CPU 1 is written in the coefficient RAM (previous stage) 31 and then written in the coefficient RAMs 32 to 34 (step S4). When the writing of the coefficient RAMs 32 to 34 is completed, the start register 51 and the end register 52 are cleared (step S5), and thereafter, a new program is output from the AND gate 55. In addition, new coefficients are output from the coefficient RAMs 32 to 34 in synchronization with the new program, but these are the same coefficients. Therefore, the output of the subtraction circuit 41 becomes “0”, and the old coefficients in the coefficient interpolation circuit 40 are changed. Interpolation to the new coefficient is not performed. As a result, when the program is changed, it is possible to prevent the inconvenience that the interpolation process is performed between the coefficient before the change and the coefficient after the change.

  The present invention is used for generating ringtones and game sound effects in a portable terminal.

It is a block diagram which shows the structure of the musical tone signal generation circuit G to which the data processing circuit by one Embodiment of this invention is applied. 3 is a block diagram showing a configuration of a mobile phone using the musical tone signal generation circuit G. FIG. FIG. 6 is a diagram for explaining the operation of the music signal generation circuit G. 4 is a flowchart for explaining the operation of the musical tone signal generation circuit G. 4 is a circuit diagram showing in more detail the configuration of coefficient RAMs 32 to 34, a subtracting circuit 41, and an adding circuit 42 in the musical tone signal generating circuit G. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... CPU, 12 ... Buffer register, 13 ... Sound source circuit, 14 ... Data processing circuit (DSP), 21 ... Data RAM, 22 ... Program RAM, 23 ... Arithmetic circuit, 24 ... Buffer memory, 27 ... Program counter, 31 ... Coefficient RAM (previous stage), 32 ... Coefficient RAM (new), 33 ... Coefficient RAM (old), 34 ... Coefficient RAM (intermediate), 36, 37, 43 ... Selector, 40 ... Coefficient interpolation circuit, 41 ... Subtraction circuit, 42 ... adder circuit, 44 ... end determination circuit.

Claims (3)

A program memory in which the program is stored;
A coefficient memory in which the coefficients are stored;
A program counter for reading a program in the program memory and a coefficient in the coefficient memory;
In a data processing circuit comprising the arithmetic circuit that operates according to the program and the coefficient,
A new coefficient memory for storing the new coefficient after the change of the coefficient;
An old coefficient memory in which the old coefficient before the coefficient change is stored;
Coefficient interpolation means for generating a coefficient that sequentially changes from the coefficient in the old coefficient memory toward the coefficient in the new coefficient memory, and outputting the coefficient to the arithmetic circuit;
Rewriting means for rewriting the new coefficient memory and the old coefficient memory with new coefficients when receiving the program and coefficient change instruction ;
A data processing circuit comprising: A program memory in which the program is stored;
A coefficient memory in which the coefficients are stored;
A program counter for reading a program in the program memory and a coefficient in the coefficient memory;
In a data processing circuit comprising the arithmetic circuit that operates according to the program and the coefficient,
A new coefficient memory for storing the new coefficient after the change of the coefficient;
An old coefficient memory in which the old coefficient before the coefficient change is stored;
An intermediate coefficient memory in which a coefficient obtained by interpolating the new coefficient and the old coefficient is stored;
Subtracting means for obtaining 1 / X (X is a real number greater than 1) of the difference between the coefficient in the new coefficient memory and the coefficient in the old coefficient memory;
A coefficient interpolation means for writing to said intermediate coefficient memory with the said output of the subtracting means adds the coefficients of the intermediate coefficients in memory, and outputs the addition result to the arithmetic circuit,
Rewriting means for rewriting the new coefficient memory, the old coefficient memory, and the intermediate coefficient memory with new coefficients when receiving the program and coefficient change instruction ;
A data processing circuit comprising: 3. The data processing circuit according to claim 1, further comprising means for outputting a command for causing the arithmetic circuit to stop the operation when receiving an instruction to change the program and the coefficient.

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