JPH02137895A - Sound source device - Google Patents

Abstract

PURPOSE:To facilitate looping control without increasing additional information for looping processing by reproducing an analog or digital audio signal with an identification flag indicating a looping section and muting the signal with an identification flag indicating the end of sound source data. CONSTITUTION:According to the identification flag indicating the looping section, continuous samples Sa of 1st kind are read repeatedly out of a sound source data memory 1 or continuous samples Sb of 2nd kind are read out to reproduce the analog or digital audio signal. Then when the identification flag indicates that the sound source data has no looping section and shows the end of the sound source data, the signal is muted. Consequently, the control at the end of looping processing and sound source data reproduction is facilitated without increasing the additional information for the looping processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sound source device for reproducing analog or digital audio signals such as musical tone signals.

[Summary of the invention]

The present invention provides a sound source data memory for storing sound source data consisting of a first type of consecutive plurality of samples having a looping section and a second kind of consecutive plurality of samples having no looping section; It has a flag check circuit that detects the presence or absence of a looping section of the sound source data and an identification flag indicating the end of the sound source data. Read out multiple consecutive samples to play back an analog or digital audio signal, and apply muting when the identification flag indicates that the sound source data has no looping section and is the end of the sound source data. This provides a sound source device that facilitates looping control without increasing additional information for looping processing.

[Conventional technique]

In general, sound sources used in electronic musical instruments, TV game machines, etc. are broadly divided into analog sound sources such as VCO, VCA, VCF, etc., and digital sound sources such as PSG (programmable sound generator) and waveform RoMm type. . In recent years, as a type of digital sound source, sampler sound 'a' (for example, Japanese Patent Laid-Open No. 62-2640
99 and Japanese Patent Laid-Open No. 62-267798) are also becoming widely known.

For this sampler sound source, - Since boat fishing requires a large memory capacity for storing sound source data, various methods have been devised to save memory. For example, looping processing using the periodicity of musical sound waves. Typical examples include bit compression processing using nonlinear quantization and the like.

Here, the looping process described above is also a method for continuing to output a sound for a longer time than the original duration of the sampled musical tone. That is, when considering a musical tone signal waveform, for example, immediately after the start of sound generation at -C, there is a formant part where the periodicity of the waveform is unclear, including so-called non-pitch components such as piano key tapping noise and wind instrument press noise. After that, the same waveform will appear repeatedly with a fundamental period corresponding to the musical pitch (pinch, pitch).

By setting n cycles (n is an integer) of this repetitive waveform as a looping section and reproducing the loop repeatedly as necessary, a long-lasting sound can be obtained with a small memory capacity.

[Problem to be solved by the invention]

Here, when the sound source data of the sampler sound source is read out from the memory and reproduced, some of the sound source data has a looping section and some does not. When ending the reproduction of the sound source data, the processing method for ending the reproduction of the sound source differs depending on the presence or absence of a looping section in -C.

That is, in the case of ending the reproduction of sound source data having a looping section, it is common to end the reproduction using a flag of the looping end point included in the sound source data of the looping section. In addition, in the case of ending the playback of sound source data that does not have a looping section, appropriate processing is required to end the sound at a predetermined position in the sound source data, and -a
Specifically, this is accomplished by adding a separate address for the reproduction end signal.

Therefore, if the processing method for ending the playback of sound source data differs depending on the presence or absence of a looping section, the sound source device that performs the above processing will use the data for determining the presence or absence of a looping section and the sound source data that does not have a looping section. A separate address, etc. is required for the playback end signal, which increases the memory capacity and the device. ! The problem of clutter arises.

The present invention has been proposed in view of the above-mentioned circumstances, and provides a sound source device that facilitates control of looping processing, termination of sound source data reproduction, etc. without increasing additional information for looping processing. The purpose is to

[Means to solve the problem]

A sound source device according to the present invention has been proposed to achieve the above-mentioned object, and includes a plurality of continuous samples of a first type having a looping section in which repeated playback is performed, as shown in FIG. a sound source data memory 1 that selectively stores sound source data consisting of Sa and a second type of continuous plurality of samples sb without the looping section;
an attached information register 2 for extracting data accompanying the sound source data; and a flag chienori circuit 3 for detecting from the extracted data an identification flag indicating the presence or absence of a looping section of the sound source data and the end of the sound source data. , an address for reading the first type of consecutive samples Sa and the second type of consecutive samples sb from the sound source data memory 1 from the extracted data and sound source data of the attached information register 2. an audio signal processing circuit 5 that performs signal processing (for example, decoding) on the sound source data to make it playable data based on the extracted data of the attached information register 2, and the flag check. By having a mute circuit 6 that mutes the signal-processed sound source data using the identification flag of the circuit 3, a plurality of consecutive samples Sa of the first type are transmitted from the sound source data memory l as the sound source data. When the analog or digital audio signal is reproduced by repeatedly reading from the memory 1 or by reading out a plurality of consecutive samples sb of the second type, the identification flag indicates that the sound source data has no looping section and the end of the sound source data is detected. It is characterized by applying muting when a certain thing is indicated.

[Operation] According to the present invention, the sound source data includes an identification flag indicating the end of the sound source data, and muting is performed by detecting the identification flag indicating that there is no looping section and the end of the sound source data. multiply.

〔Example〕

An embodiment of the sound source device according to the present invention will be described below with reference to the drawings. It goes without saying that the present invention is not limited to the following examples.

In FIG. 2, a memory 13 including a sound source data memory 11 and an address data memory 12 is supplied with sound source data from an external sound source data supply means 10. Prior to explaining the present invention, a method and apparatus for obtaining this sound source data will be briefly explained.

That is, first, FIG. 3 shows an example of a musical tone signal waveform before sampling. In the musical tone signal waveform shown in FIG. 3, the formant part FR is a part in which the periodicity of the waveform is unclear because non-pitch components such as piano key-press noise and wind instrument press noise are generally included immediately after the start of sound generation. occurs, and then the musical pitch (pitch,
The same waveform appears repeatedly with a fundamental period corresponding to the pitch). n periods of this repetitive waveform (n is an integer)
is a looping section LP, and this looping section LP is expressed between the looping points of the looping start point LP and the looping end point LPt. Then, by recording the formant portion FR and the looping section LP on a storage medium, and during playback, the looping section LP is repeatedly played following the playback of the formant portion FH, thereby making it possible to generate a musical tone over an arbitrary long period of time. It is possible.

When this musical tone signal waveform is divided into the formant portion FR and the looping section LP and recorded on a storage medium such as a memory, bit compression encoding is applied to reduce the amount of data.

By the way, there are various bit compression encoding methods that can be considered, but here, the present applicant has previously published Japanese Patent Application Laid-Open No. 62-008629 and Japanese Patent Application Laid-Open No. 62-003516.
A quasi-instantaneous companding type proposed in the above publication, that is, a high-efficiency encoding method in which a certain number of words (h samples) of peak value data is divided into blocks and bit compression is applied in units of blocks, is used. This high-efficiency focus compression encoding method will be schematically explained with reference to FIG.

In FIG. 4, the high-efficiency focus compression encoding system is composed of an encoder 70 on the recording side and a decoder 90 on the reproduction side. Data x (n) is supplied.

This input signal (peak value data) x(n) is obtained by the predictor 7
The prediction signal (peak value data) x(n) from the predictor 72 is supplied to the FIR (finite impulse response) digital filter 74, which is composed of the adder 72 and the adder 73. being sent. The adder 73 subtracts the predicted signal x(n) from the input signal x(n), thereby outputting a prediction error signal or a broadly defined difference output d(n). The predictor 72 generally calculates the past two human forces x(n-p), x
The predicted value "; (n) is calculated by a linear combination of (n-p+1)+...x(n-1).The above F
The IR filter 74 is hereinafter referred to as an encode filter.

In the high-efficiency focus compression encoding system, the sound source data is divided into blocks for each data within a certain period of time, that is, input data of a certain number of words, and the encoding filter 74 having the optimum characteristics is selected for each block. I try to do that. This can be achieved by providing in advance a plurality of (for example, four) encoding filters with different characteristics and selecting the filter with the optimal characteristics among these filters.However, The configuration of a general digital filter is as shown in the first EI.
By storing a plurality of coefficient sets (for example, four sets) of the coefficients of the predictor 72 of the encode filter 74 in a coefficient memory, etc., and switching and selecting these coefficient sets in a time-sharing manner, the An operation equivalent to selecting one of the plurality of encoding filters described above is often performed.

Next, the difference output d (n) as the prediction error is sent via an adder 81 to a bit compressor consisting of a shifter 75 with a gain G and a quantizer 76, and is sent to a bit compressor consisting of a shifter 75 with a gain G and a quantizer 76, for example, a floating point Compression processing or ranging processing is performed such that the exponent part in the display form corresponds to the gain G and the mantissa part corresponds to the output from the quantizer 76, respectively. That is, the shifter 75 shifts the input data by the number of bits corresponding to the gain G to switch the range, and the quantizer 76 performs requantization to extract a fixed number of bits from the bit-shifted data. There is. Here, the noise shaping circuit (noise shaper) 77 obtains a so-called quantization error corresponding to the error between the output and the input of the quantizer 76 using the adder 7, and converts this quantization error into a gain G-1. The signal is sent to the predictor 80 via the shifter 79, and so-called error feedback is performed in which the predicted signal of the quantization error is fed back to the adder 81 as a subtraction signal.

In this way, requantization by the quantizer 76 and error feedbanking by the noise shaping circuit 77 are performed, and an output 'a''(n) is taken out from the output terminal 82.

By the way, the output d'(n) from the adder 81 is calculated from the difference output d(n) by the noise shaper 77.
Predicted signal of quantization error from? (n), and the output a IT (
n) is the gain G and the output d' from the output adder 81
(n). In addition, the above quantizer】6
The output function (n) from the quantization process is the quantization error e (n) and the output d '' (n
), and the adder 78 of the noise shaper 77 extracts the quantization error e (n). This quantization error e (n) is the gain G
-' shifter 79 and a predictor 80 that takes a linear combination of r past inputs, resulting in a quantization error prediction signal 7(n).

The sound source data is subjected to the encoding process as described above, and is outputted from the quantizer 76 as an output ↑(n) through the output terminal 82.

Next, the prediction/range adaptation circuit 84 outputs mode selection information as optimal filter selection information and sends it to the predictor 72 and output terminal 87 of the encoding filter 74, and also outputs the gain G and the gain G-1 or the range information for determining the above bit shift amount is outputted to each shifter 75, 79 and output terminal 8.
It has been sent to 6.

An example of one block of output data from the bit compression encoding encoder 70 is shown in FIG. This one block of data consists of 1 byte of header information (parameter information or attached information regarding bit compression) RF and 8 bytes of sample data D46 to DB3.
It is made up of.

The header information (attached information) RF includes the range information of 4 bits, the mode selection information or filter selection information of 2 bits, and two flag information of 1 bit each, such as information Ll indicating the presence or absence of a loop and the waveform. It is composed of information El indicating whether there is a terminal block (end block) or not.

These pieces of information Ll and El correspond to the above-mentioned identification flag. Here, the peak value data of one sample is compressed and expressed in 4 bits, and the above data DAo=D11
．． Inside is 4-bit data D A6M for 16 samples.
~D 13L is included.

The compressed and encoded block unit data as shown in FIG. 5 is recorded in a storage medium such as a memory, and is supplied from, for example, the sound source data supply means 10 to the sound source data memory 11 of the memory 13 in FIG. For the compressed and encoded block unit data from the sound source data memory 11, the attached information is taken into the attached information register 14, and the sample data is decoded by the decoder 30. This decoder 3
0 consists of a decode filter 31 and a shifter 32,
Decode filter 31 consists of an adder 33 and a predictor 34. This decoder 30 will be explained with reference to FIG.

That is, in FIG. 4, the output (sample data) ↑(n>) from the output terminal 82 of the encoder 70 is transmitted to the input terminal 91 of the decoder 90 on the reproduction side, or is obtained by being recorded and reproduced. Signal 7' (
n) is supplied. This input signal 71 (n) is sent to an adder 93 via a shifter 92 with a gain of G-'. The output x'(n) from the adder 93 is sent to a predictor 94 to generate a predicted signal.

(n), and this predicted signal ma°(n) is sent to the adder 9
3 and the output from shifter 92 ';f'' (n)
is added. This addition output is output from the output terminal 95 as a decoded output ↑'(n). In this case, the output cuff II (n) from the shifter 92 is the input signal 7
v (n) multiplied by gain G-1. Also,
The output ↑'(n) of the adder 93 is the sum of the output ↑''(n) from the shifter 92 and the prediction signal 7'(n).

These shifter 92, adder 93 and predictor 94
They correspond to the shifter 32, adder 33, and predictor 34 in the figure, respectively.

Also, each output terminal 86 and B7 of the encoder 70
The range information and mode (filter) selection information output, transmitted, recorded, and reproduced are input to input terminals 9G and 97 of the decoder 90, respectively. The range information from the input terminal 96 is sent to the shifter 92 to determine the gain G-1, and the mode selection information from the input terminal 97 is sent to the predictor 94 to determine prediction characteristics. The prediction characteristic of this predictor 94 is selected to be equal to the characteristic of the predictor 72 of the encoder 70. In the case of FIG. 2, these range information and filter selection information are given from the attached information register 14.

The circuit shown in FIG. 2 is mainly used to perform the decoding operation as described above, and the decoded sound source data is
The signal is subjected to various processing such as addition of an envelope, reverberation, or echo processing, and then sent to the D/A converter 37 via the mute circuit 36, where it becomes an analog musical tone signal and is reproduced from the speaker 3B.

Furthermore, the circuit shown in FIG. 2 includes an address generation circuit 20 for reading out predetermined sound source data stored in the memory 13 in response to key-on and the like and for performing looping read processing. This address generation circuit 20 generates a data start address from the address data memory 12.
Data SA and looping start address data LSA
It has an address register 21 for reading the address data, an address counter 22 which is loaded with this address data and performs counting operation according to the clock, and a multiplexer 23 to which the address output from the address counter 22 is sent. ing. The load control terminal (preset control terminal) of the address counter 22 receives a timing pulse CPA, which will be described later, from the terminal 24 and is connected to the AND gate 25.
The AND gate 25 is gate-controlled by the output from the OR gate 26. Also, a directory address generation circuit 2 is provided in the address generation circuit 20.
B is provided, and the address output from this directory address generation circuit 2 is sent to the multiplexer 23. Either the directory address output or the address output from the address counter 22 is selected by a multiplexer 23, and the memory 13 is accessed by the address output from the multiplexer 23.

The attached information register 14 is a timing pulse C which will be described later.
At the timing when PI+ is supplied to the terminal 15, the above-mentioned hender information (parameter information regarding compression or attached information) is fetched, and the above-mentioned loop information (information 11 indicating the presence or absence of a loop) in the attached information fetched into this register 14 is read. )
Ll is ANDed through impark (negation gate) 16
The end information (information indicating whether or not it is the end block of the waveform) El is sent to the AND gate IT and the OR gate 26. The output signal from the AND gate 17 is supplied to the cent terminal S of the flip-flop 18, and the reset terminal R of the flip-flop 18 is supplied with a sound generation start signal (key-on signal) KON from the terminal 19. This key-on signal KON is the OR
It is also supplied to gate 26 and directory address generation circuit 28. This key-on signal KON includes not only a key-on of the electronic musical instrument but also a trigger signal for starting the sound generation of automatic performance software.

Next, FIG. 6 shows an example of the contents of the memory 13. For example, in 64, a RAM of the size of Hyde is installed in a plurality of memory areas, that is, at least the sound source data memory 1.
1 and the address/data memory 12 are used separately. Address data memory 12
is a part of a so-called directory area in the memory, and the data start address data SA and looping start address data LSA are accessed by the directory address from the directory address generation circuit 28. And these data SA, LSA
The start address of the first data portion SDF (corresponding to the formant portion FR of the signal waveform) consisting of a plurality of consecutive samples, and the start address of the data portion SDL (corresponding to the above looping section LP) consisting of a second consecutive plurality of samples is determined by The starting address is indicated respectively. In the example shown in FIG. 6, formant data SDF 1 and looping data are respectively indicated by SAI and LSAI.
Sound source data SDI consisting of data SDL l and SA2
, data 5DF2 indicated by LSA2, respectively.
．． Sound source data SD2 consisting of 5DL2 and sound source data S consisting only of data 5DF2 specified by SA3.
Although D3 is shown in the figure, other sound source data consisting only of a looping portion may also be considered. In reality, the address data SA and LSA indicate only the address of the header information (attached information) RF in the compression encoding unit, that is, the address of the header information (attached information) RF shown in FIG. The address instruction in units of bytes is performed by the address counter 22 or the like.

Next, the operation will be explained.

FIG. 7 is a timing chart for explaining time-division operation of signal processing, and T represents a sampling period. For example, when the sampling frequency is 32 kHz, T becomes 1/32 [msl]. This one sampling period T is first divided into the number of notes that can be produced simultaneously (8 pieces from Pois O to Pois 7 in the example), and the allocation of each Pois is made even more precisely in terms of time. It is divided and allocated according to the content of each time-sharing process. When the minimum unit time of this time division processing is τ, for example, τ. , τ1 is assigned to the time to read (fetch) the address data SA or LSA of the directory area, and the times τ2 to τ5 are assigned to the time to read the bit compression encoded data,
A time τ is allocated to updating the address counter 22. Also, among the above-mentioned times τ2 to τ5, time τ2 is used to read the attached information (hander information RF in Fig. 5), and time τ3 to τ is used to read the sample data (the
Data DAO to D6 in the figure. ) are assigned to each read. And the above timing pulse CP
h is output at the timing of the above-mentioned time τ, and the above-mentioned timing pulse CP is output at the timing of the above-mentioned time τ2.

Here, the key-on signal KON for starting sound generation is output during one period of the sampling period T (in the illustrated example, it is at a high level "°H" from time t0 to t1), and the leading edge of this KON signal Standby signal 5 at (rise)
TBY falls, number T.

It is designed to rise after a cycle (in the illustrated example, time ts after five cycles).

When this key-on signal KON is input to the terminal 19, the directory address generation circuit 28 generates a directory address based on the memory offset address set by the CPU system and the source number indicating the type of sound source, The signal is sent to the multiplexer 23. This multiplexer 23 receives the time τ of the time division slot. , τ
During , the address output from the directory address generation circuit 2B is selected to access the memory 13, and the predetermined address data in the address data memory 12, that is, the start of the sound source data corresponding to the above source number. The data SA indicating the address is read out and fetched into the address register 21 via the data bus. At this time, the key-on signal KON is sent to the AND gate 25 via the OR gate 26, and
Since the gate 25 is controlled to be on (conductive), the above time slot τ. A pulse CP with a timing of 22 starts a counting operation from this data SA, and the sound source data SDF whose starting address is SA is accessed in address order. When there is continuous loop data SDL in the data SDF, the data SDL is automatically sequentially accessed after the data SDF.

Here, after the next sampling period when the key-on signal KON is output (time (after time 1)), the key-on signal KON is in an initial state (low level "L" state).
The directory address generation circuit 28 outputs the start address data LSA of the loop data SDL. Therefore, the address register 21 takes in the loop start address data LSA, but the address
The counter 22 does not load the address from the address register 21 unless an input is input to the load control terminal, and continues the counting operation up to that point. Note that this operation is irrelevant in the case of only the data SDF of the formant part.

Then, the above end information El from the attached information register 14
When the flag is raised, that is, the loop data SDL
When the end block of (or the end block of the formant part data SDF) is reached, OR
The AND gate 25 is turned on (conductive) through the gate 26, and the looping start address data LSA in the address register 21 is loaded (preset) into the address counter 22 at the input timing of the timing pulse CP^. However, as mentioned above, the address data SA and LSA are addresses for each focus compression block, and the actual operation is to start the looping start block of the sound source data of the looping start block at the timing of signal processing of the next block. Access is made.

The end information El is also sent to the AND gate 17. Since the NOT output of the loop presence/absence information Ll is sent to this AND gate 17,
When the sound source data SD3 in FIG. 6 consists of only the first type of data (data corresponding to the formant part) SDF3 and there is no data SDL in the looping section, the output from the negation gate 16 is at a high level "H". ”. When such an end block of the sound source data SD3 is reached, the output from the AND gate 17 becomes a high level °'H'', and the flip-flop 18 is set to put the mute circuit into a muting state (a state in which the audio signal is cut off). LQ). This is a mute operation when there is no looping, but when looping is present, looping playback is repeated until the next key-on, and the sound is muted by envelope processing. When the key-on signal KOH is input, it is supplied to the reset input terminal R of the flip-flop 18, and the flip-flop 18 is put into the reset state regardless of its previous state, so that the muting state is canceled.

By the way, the two sound source data SDI, SD2,
Especially each looping data part SDL 1.5
Using the DL2, sound source data from the external sound source data supply means 10 is alternately sent to the memories of the 5DL1 and 5DL2.
area and read it out alternately to the decoder 3.
By decoding with 0, it is possible to decode sound source data over a long period of time. That is, while the sound source data from one memory area of the SDL 1.5DL2 is being read out and decoded, the external sound source data supply means 1 is sent to the other memory area.
Sound source data is written starting from 0, and writing and reading are performed alternately by alternating these memory areas.

This can be realized very easily by using the looping processing operation and alternately rewriting the looping start address data LSAI and LSA2.

That is, in the memory 13 of FIG. 6, the address data is written to the memory area 12a where the looping start address data LSAI is written.
and LSA2, and the sound source data 5D
While reading L1 and performing the above decoding process, looping start address data LS is stored in memory area 12.
Write A2 and set this LSA2 to address register 2.
1, and when it reaches the end of data SDL 1 (looping end), this address data LSA
By loading 2 into the address counter 22, access to the sound source data 5DL2 starts from the start address LSA2.

Next, looping start address data LSAI is written in the memory area 12 while this sound source data 5DL2 is read out and subjected to the decoding process. When the end of the data 5DL2 (looping end) is reached, this address data LSAI is transferred to the address counter 22.
Since the sound source data SDL 1 is loaded, access to the sound source data SDL 1 is started.

In this way, continuous decoding processing of sound source data over a long period of time can be realized without increasing hardware.

By the way, the above-mentioned bit compression encoding processing and other digital signal processing for generating sound source data are often implemented in software using a digital signal processing device (DSP). A software-like configuration using a DSP is often adopted for the reproduction of sound source data. Figure 8 shows an example of this.
An example of the overall configuration of a system including an audio processing unit (APU) 1OL as a sound source unit that handles sound source data and its surroundings is shown.

In FIG. 8, a host computer 104 installed in, for example, a general personal computer device, a digital electronic musical instrument, a TV game machine, etc. is connected to the APUIO 7 as the sound source unit, and is connected to the host combiator 104. The sound source data etc. are APIJ1
It is designed to be loaded in 07. That is, the sound source data supply means 10 is provided within the host computer 104.

Next, APtJ107 is a CPU such as a microprocessor.
(It is configured to include at least a central processing unit 103, a DSP (digital signal processing device) 101, and a memory 102 in which the above-mentioned sound source data etc. are stored. In other words, this memory Reference numeral 102 corresponds to the memory 13, in which at least sound source data is stored, and the DSP 101 performs various processes including readout control of the sound source data, such as looping processing, bit expansion (restoration) processing, and pitch conversion processing. , adding envelope 1, echo (reverb) processing, etc. The memory 102 is also used as a buffer memory for these various processes.
1 '01 controls the operations and contents of these various processes. In addition, the memory 13 (
Rewriting address data LSA in the memory 102) and sound source data supply means 10 (host computer 104)
The CPU 103 also performs the process of writing the sound source data from the source data into the memory 13.

Furthermore, D is applied to the sound source data from the memory 102.
The digital musical tone data finally obtained by performing the above various processing using SPIOI is sent to the D/A converter 105 (
The signal is converted into an analog signal by a D/A converter 37 (corresponding to the D/A converter 37) and then supplied to the speaker 106 (corresponding to the speaker 38).

Note that the present invention is not limited to the embodiments described above; for example, in the embodiments described above, the formant part and the looping section were connected to form the sound source data, but the sound source data consists only of the looping section. It can also be easily applied to the case of forming sound source data. In addition, the above decoder side configuration and external memory for supplying sound source data are ROM
May be supplied as cartridges or adapters;
It is applicable not only to the sound source of musical tone signals but also to voice synthesis.

〔Effect of the invention〕

According to the sound source device of the present invention, based on the identification flag indicating the presence or absence of a looping section, consecutive plural samples of the first type are repeatedly read out from the sound source memory, or consecutive plural samples of the second type are read out and the analog Alternatively, the digital audio signal is reproduced, and muting is applied using an identification flag indicating the end of the sound source data. Therefore, looping control can be facilitated without increasing additional information for looping processing.

In addition to the identification flag indicating the presence or absence of a looping section, a similar effect can also be obtained by using a flag indicating an end with a loop and a flag indicating an end without a loop.

4...Address generation circuit 6...Mute circuit

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram for explaining the basic configuration of a sound source device according to the present invention, FIG. 2 is a block circuit diagram showing an embodiment of the present invention, FIG. 3 is a musical tone signal waveform diagram, and FIG. 4 5 is a block circuit diagram showing a schematic configuration of a bit compression encoding system that compresses bits in units of blocks for each of multiple samples, and FIG. FIG. 6 is a schematic diagram showing an example of the contents of the memory, FIG. 7 is a timing chart for explaining the operation of the circuit in FIG. 2, and FIG. 8 is an audio processing unit (APU) ) and its surroundings. FIG. Patent issuer

Claims (1)

[Claims] Selectively stores sound source data consisting of a plurality of continuous samples of a first type having a looping section that is repeatedly played back and a plurality of consecutive samples of a second type having no looping section. a sound source data memory; and a flag check circuit for detecting the presence or absence of a looping section of the sound source data accompanying the sound source data and an identification flag indicating the end of the sound source data; A plurality of consecutive samples of one type are repeatedly read from the sound source memory, or a plurality of consecutive samples of the second type are read out to reproduce an analog or digital audio signal, and the identification flag indicates that the sound source data is looping. A sound source device that applies muting when there is no section, indicating the end of the sound source data.