JP2745866B2 - Digital data compression method for waveform data and tone control, and waveform data reproducing apparatus - Google Patents

Abstract

PURPOSE:To efficiently compress data by dividing waveform sample data into sections consisting of plural samples, detecting maximum value among the numbers of effective bits of respective data, section by section, and storing the data in the respective sections while making the data uniform to the number of bits corresponding to the maximum value. CONSTITUTION:One block of waveform sample data read out of a waveform memory 15 by a waveform read part 40 is further divided into plural sections (frame). A bit quantity detection part 56 detects the maximum values among the numbers of effective bits of the respective divided frames and a shift data generator 45 cuts the bits of the respective waveform sample data uniformly to the maximum bit length. Thus, the waveform sample data which are processed to the variable bit length are written in the waveform memory 15 again by a writing process part 58. At this time, the writing process is performed by adding various control data on the compression coefficient and weight coefficient of data used for reproduction processing, the number of bits of the waveform sample data, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for compressing various waveform data such as a sound source waveform, a sound signal waveform, and a control waveform, which can be used in an electronic musical instrument and other musical sound generators and sound signal processors. The present invention also relates to a method of compressing various digital data for generating or controlling musical tones.

[0002]

2. Description of the Related Art As one method for creating a sound source waveform in an electronic musical instrument, a sound actually produced acoustically by a natural musical instrument or the like is sampled and stored. 54-161313, JP-A-62-89093, JP-A-62-94896, and the like. Such an external sound sampling type sound source has the advantage that a high-quality musical sound waveform equivalent to that of a natural musical instrument can be obtained, but since the amount of waveform data is enormous, the waveform data storage device has a large capacity Had requested. In order to simplify the configuration of a storage device and circuits and devices related thereto, it has been considered to compress waveform data. For example, Japanese Patent Application Laid-Open No. 62-242993 discloses that musical tone waveform data is stored in a data expression format compressed by a linear prediction method (LPC method). In addition, Tokuhei 1
Japanese Patent Application No. -45078 discloses that waveform sample data is decomposed into a floating-point representation including a mantissa part and an exponent part, expressed, and stored. The data encoding method is not limited to PCM, but may be DPCM, ADPCM,
It is also known to employ various methods such as delta modulation to perform data compression.

Conventionally, not only a data storage device storing conventional PCM format data but also a data storage device employing the above-described data compression method, one-to-one data is stored in each storage address. And the data length (data size, that is, the number of bits constituting one data) of the data stored therein is fixed to a constant value. For example, a 16-bit address per address is 16
Normally, one data is stored with a data length of bits. Also, as a special use of memory, for example,
In some cases, one address of 16 bits is divided into two by 8 bits, and different 8-bit data is stored in each. However, even in that case, if the data to be stored is 8 bits, it is data having a fixed bit length of 8 bits.

[0004]

As described above, in the prior art, data is stored with a fixed bit length. Therefore, for data in which the number of effective bits is smaller than the fixed bit length, the storage element is not used. Wasted in vain. For example, when musical tone waveform data is stored so that the maximum amplitude value can be covered with a fixed bit length of 16 bits, the number of effective bits may be only a few bits at a sample point having a small amplitude value. In such a case, a storage element of 13, 14 bits per address is wasted. The number of storage elements that are wasted in this way is not negligible when summed up in the entire storage device, and hinders efficient use of the storage device as a whole,
This is a factor that hinders a reduction in circuit scale and cost. SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been developed in order to minimize the number of storage elements that are wasted as much as possible and to efficiently use a storage device. To improve the data compression method of digital data for generation or control, and to store data according to such method.
Waveform that reads storage device and reproduces waveform data properly
It is intended to provide a data reproducing device .

[0005]

According to a first aspect of the present invention, there is provided a waveform data compression method according to the present invention, wherein a first step of providing digital waveform sample data of a predetermined number of bits comprising a large number of samples; A second step of dividing the waveform sample data consisting of a plurality of samples into a plurality of sections consisting of a plurality of samples, and detecting a maximum value of the number of effective bits of the waveform sample data for each section;
Out of all the bits of each waveform sample data provided in the step, the lower bits corresponding to the number of bits corresponding to the maximum value detected in the second step are extracted for each section, and thus, for each section, A third step of obtaining waveform sample data aligned to the number of bits corresponding to the maximum value of
Bit number indication data indicating the number of bits corresponding to the maximum value
Storing the data in the storage device;
The bit number indication data for
And divide each part into the above section for the section before the section.
Separated between waveform sample data and stored in the storage device
And a fourth step of performing the above. According to a second aspect of the present invention, there is provided a waveform data compression method according to the present invention, wherein a first step of providing digital waveform sample data of a predetermined number of bits comprising a large number of samples; A second step of performing data compression processing for each block section, and dividing the waveform sample data of each block section into a plurality of frame sections consisting of a plurality of samples. A third step of respectively detecting the maximum value of the number of effective bits of the data sampled waveform sample data; and of all bits of the data-compressed waveform sample data provided in the second step, , The third
The lower bits corresponding to the number of bits corresponding to the maximum value detected in the step are extracted, and waveform sample data aligned with the number of bits corresponding to the maximum value of the section is obtained for each frame section and stored. 4th to be stored in the device
And the maximum value for each frame section.
Bit number indicating data indicating a corresponding bit number;
Is a step of storing each frame interval.
The number of bits indicating data of Te respectively divided into a plurality of parts
Each part to the frame section before the frame section.
The waveform sample data of the
And a fifth step of storing in the device .
A digital data compression method for generating or controlling a musical tone according to the present invention includes a first step of providing digital data for controlling a musical tone having a predetermined number of bits composed of a large number of samples; Is divided into a plurality of sections composed of a plurality of samples, a second step of detecting the maximum value of the number of effective bits of the digital data for each section, and a step of detecting all of the digital data provided in the first step. Of the bits, the lower bits corresponding to the number of bits corresponding to the maximum value detected in the second step are extracted for each section, and thus the number of bits corresponding to the maximum value of the section is aligned for each section. A third step of storing digital data in a storage device, and indicating the number of bits corresponding to the maximum value for each section.
Step for storing bit number instruction data in the storage device
And the bit number indication data for each section is
Each is divided into multiple parts, and each part is
Separate between the digital data for the section before
And a fourth step of storing in the storage device . Further, the waveform data reproducing apparatus according to the present invention
The waveform sample data and the bits according to the method described above.
The storage device storing the number instruction data;
Reading means for reading each data stored in the storage device;
The bits read from the data read by the read / write means.
To take out each part of the numerical instruction data and collect this
The more completed bit number indication data is reproduced, and the reproduced
To output the specified bit number indication data for the next section
Data read means and the read means.
Extract the waveform sample data from the extracted data
The bit number indication data for the section.
The bit number instruction data output from the data reproducing means is
A wave from which the waveform sample data is extracted with the indicated number of bits
Shape sample data extracting means.

[0006]

According to the waveform data compression method according to the first aspect, in the second step, the waveform sample data composed of a large number of samples is divided into a plurality of sections composed of a plurality of samples, and the waveform sample data is divided for each section. The maximum value of the number of effective bits of each is detected. Then, in the third step, out of all the bits of each of the waveform sample data, lower bits corresponding to the number of bits corresponding to the detected maximum value are extracted for each section, and thus, for each section, Obtain waveform sample data aligned to the number of bits corresponding to the maximum value and store it in the storage device. Therefore, for example, waveform sample data consisting of a large number of continuous samples such as from the start to the end of sound generation is divided into a plurality of sections, and the data bit size of each of these waveform sample data is determined by the number of effective bits for each section. Processing is performed so as to be trimmed to a variable bit length corresponding to the maximum value, and the variable bit length processed as described above is stored in the storage device. By employing such data compression processing for processing into a variable bit length, the data size of the waveform data stored in the storage device, that is, the bit length, can be arbitrarily variable instead of being fixed. Therefore, only the number of storage elements necessary for the effective bits of the waveform data is occupied, and unnecessary storage elements are not occupied. In other words, the remaining storage element can be used for storing other data without wasting the storage element, so that the storage device can be saved and used efficiently. Furthermore, in the fourth step
Corresponds to the maximum value of the waveform sample data for each section.
Multiple bit number data indicating bit number
, And divide each part for the section before that section.
Separated into the waveform sample data of
Waveform samples
Efficiently store bit number indication data between data
be able to.

According to the waveform data compression method according to the second aspect, the above-described variable bit length processing is performed on waveform data that has been subjected to a normal predetermined data compression processing (for example, data compression processing based on the LPC method or the like). Apply to In this case, the above-described variable bit length processing is performed for each frame section smaller than the block section where the predetermined data compression processing is performed. Since the variable bit length processing only needs to detect the maximum value of the number of valid bits, the processing is simpler than the normal predetermined data compression processing, and the frame interval is finer than the normal predetermined data compression processing. It is suitable to be performed every time, and by the synergism of both processes, it is possible to further reduce the data size while having a relatively simple configuration.

According to the method of compressing digital data for musical tone control according to the present invention, the variable bit length processing similar to the waveform data compressing method according to the first aspect is not limited to waveform data. It can be applied to various types of digital data, thereby saving and efficiently using a storage device for storing these various types of digital data for tone control for the same reason as described above. it can.

Some of the embodiments of the waveform data compression method according to the present invention according to the first aspect are as follows. a) The method further includes a fourth step of storing data indicating the number of bits for each section. b) In the fourth step, in each section, the waveform sample data of the section before the section is stored in a part of the storage area storing the waveform sample data. c) further comprising a fifth step of performing a data compression process on the waveform sample data provided in the first step, and in the second step, the waveform compressed in the fifth step. The maximum value detection processing of the number of effective bits is performed on the sample data.

Some of the embodiments of the waveform data compression method according to the present invention according to the second aspect are listed as follows. d) A fifth step of performing a process of further reducing the value of the waveform sample data according to an arbitrary weighting factor for each block section before, during, or during the data compression process of the second step. More. e) further comprising a sixth step of storing a data compression coefficient and a weight coefficient for each block section and storing data indicating the number of bits for each frame section. f) In the sixth step, the data compression coefficient and the weighting coefficient for each block section are stored in the storage device as a part of a storage area storing waveform sample data of a block section before the block section. In addition, the bit number indication data for each frame section is stored in a part of the storage area that stores the waveform sample data of the frame section preceding the frame section in the storage device. Things to do. One embodiment of the digital data compression method for musical tone control according to the present invention is as follows. g) further comprising a fourth step of performing a data compression process on the digital data provided in the first step, wherein in the second step, the digital data compressed in the fourth step is provided. The maximum number of effective bits detection process is performed.

[0011]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. --- Overall Flow of Waveform Data Compression / Reproduction Processing-- First, compression / reproduction of waveform data in one embodiment of the present invention is described.
The overall flow of the reproduction process will be schematically described with reference to FIG. First, a compression target waveform is prepared. As an example of this preparation method, by sampling and storing an original waveform generated by a natural musical instrument or the like, or by taking in a desired original waveform already stored in an external memory or the like from the external memory, You may do it.

The sampled original waveform may not be used as it is as a compression target waveform, but may be subjected to necessary processing before compression. Examples of such processing include a process of extracting the amplitude envelope of the original waveform, a process of removing the amplitude envelope from the original waveform and normalizing the amplitude level to a uniform level, and conversely, adding an arbitrary amplitude envelope. There are various types of processing, such as processing, processing for performing appropriate filtering, processing for adjusting the phase of a waveform, and processing for extracting noise components, and one or more of these may be performed. Also, a predetermined section may be cut out and stored without storing all of the processed original waveforms in the memory. In this case, a process of setting the start address of the original waveform stored in the memory and, if there is a section to be repeatedly read, setting the address of the section to be repeatedly read is also performed. Also, in order to ensure that repeated reading is performed smoothly,
Necessary waveform processing or the like may be performed.

Next, a process of compressing the waveform data and writing it to the memory is performed. Here, first, various "data settings"
I do. One of the "data settings" is a read address setting and a write address setting. The setting of the read address is to set an address range from which the original waveform subjected to the necessary processing as described above, that is, the waveform to be read from the memory storing the compression target waveform is stored.
That is, a read start address and a read end address of the original waveform memory, an address for setting a repetitive read range, and the like are set. The write address setting is a process of setting an address for specifying in which address range of the memory the waveform data after the data compression processing is to be written. As will be described later, in the following embodiment, the number of bits of one sample of the waveform data after data compression processing (that is, the data length) does not always match the number of bits of one address of the memory, and has a variable bit length. ,
In addition, one sample is not stored one-to-one at one address, but is packed and written. Therefore, even if the data amount (the number of samples) of the original waveform is known, the total storage addresses of the waveform data after data compression processing cannot be known until the compression processing is completed. Therefore, in this write address setting, a start address to write the first data can be set, but a write end address cannot be set. As will be described later, the write end address is set when the data compression process and the write process are completed.
The information is automatically stored and is convenient for later reproduction processing.

As another example of the "data setting" performed here, there is setting of a limited bit number. This is because a compression target waveform composed of a plurality of continuous cycles is divided into a plurality of sections (which are simply referred to as blocks or block sections), and the number of bits of one sample data after data reduction and compression processing is limited for each section. Second, the limit bit number is arbitrarily set for each section. In the entire section of the waveform from the start to the end of sound generation, there are portions where fine reproducibility is required such as an attack portion, and portions where fine reproducibility is not so required such as an attenuation portion. Therefore, if the number of bits after data reduction and compression processing is made variable in accordance with the precision required at the time of reproduction, it contributes to the reduction in the number of data bits, which is efficient. For this purpose, the waveform is divided into a plurality of sections, and the limited number of bits can be arbitrarily set for each section.

As another example of the "data setting" performed here, there is setting of a weight coefficient (shift data). In performing the waveform compression process, while performing a predetermined data compression process,
One of the features of this embodiment is that a reduction process for reducing the value of the waveform data according to an arbitrary weighting factor is performed before, after, or during the predetermined data compression process. A weight coefficient for that purpose is set. In the following example, the weighting operation is performed by data shift, and thus the weight coefficient is also referred to as shift data.
In the following embodiments, the weight coefficient (shift data) can be set for each block section, and the data reduction processing is performed for each block section according to an independent weight coefficient. Note that the method of “data setting” performed here is not limited to manual setting using a setting switch or the like, and data that has already been set may be imported from outside. The setting of the weight coefficient (shift data) may be manually or externally set at the data setting stage, but is automatically set according to the limited bit number during execution of the data compression processing. And may be changed.

Next, "data compression and reduction processing" is performed. Here, “predetermined data compression processing” according to a predetermined data compression technique such as a linear prediction method, and “data reduction processing” according to the above-mentioned weight coefficient (shift data) are performed. The "predetermined data compression process" is a so-called main data compression process according to a predetermined data compression technique such as a linear prediction method. On the other hand, the “data reduction process” is a process for further reducing the value of the waveform data in accordance with the weighting factor (shift data) at any stage before or after the “predetermined data compression process”. In other words, it is a sub data compression process. Details of the “data compression and reduction processing” will be described later.

Next, a process of processing the waveform sample data after the "data compression and reduction process" into data having a variable bit length is performed. Here, one block section is further divided into a plurality of sections (this is simply referred to as a frame or a frame section), the bit length of the waveform sample data is determined for each frame section, and each waveform sample is set so as to fit in the bit length. Trims the number of data bits. For example, the maximum value of the number of effective bits of the waveform sample data is detected for each frame section, and this is determined as the common bit length of the waveform sample data in that frame section. For example, assuming that 5 bits of “0” continue from the most significant bit in the waveform sample data specified by the 16-bit standard, the upper 5 bits of “0” correspond to a substantial value. The lower 11 bits are valid bits. The maximum value of the number of valid bits in the frame is a bit length that can cover all the valid bits of the waveform sample data in the frame. Therefore, even if the bit lengths of all the waveform sample data in the frame are trimmed by the bit length determined in this way, all the valid bits can be left. In this way, the waveform sample data is processed so as to be variable bit length data for each frame section. This variable bit length processing can be automatically performed based on the detection of the maximum value of the number of effective bits without manual operation. Of course, it is also possible to manually set and input the data variable bit length for each frame section.

Next, the waveform sample data processed into the variable bit length and subjected to the "data compression and reduction processing" is written into the memory. As described above, when storing waveform sample data having a variable bit length in the memory, one waveform sample data is packed and stored instead of one-to-one at each address.
Write control is performed in a part of a bit area of one address or over a plurality of addresses. In addition, various control data such as a compression coefficient used for data compression, a weight coefficient used for data reduction, data indicating the number of bits of waveform sample data, and the like are hidden so that the data can be used in a subsequent reproduction process. Control is performed to write the bit data in the waveform sample data. Details of such a writing process will be described later.

In the reproduction process, first, various parameters for generating a tone (envelope setting parameters, effect setting parameters, tone color control parameters, etc.) are set as is generally known. Then, a pitch specifying operation or a sound specifying operation of the generated sound is performed by a sound specifying means such as a keyboard, and the waveform sample data is sequentially read from the memory according to the specified pitch. As described above, since the read waveform sample data is data having a variable bit length as described above, a matching process for converting the data into a predetermined uniform bit length is performed. At the same time, hidden bit data mixed in the waveform sample data, that is, various control data, is extracted from the memory read data and separated from the waveform sample data. Details of such bit length matching processing and hidden bit separation processing will be described later. Next, the compressed waveform sample data is converted into a predetermined encoding form (for example, a PCM form).
And a calculation process of restoring the waveform sample data reduced by an arbitrary weight to a uniform weight. At that time, the compression coefficient and the weight coefficient included in the hidden bit data separated as described above, that is, the control data, are used, and the demodulation processing is performed according to the compression coefficient and the weight restoration calculation processing is performed according to the weight coefficient. . Detailed examples of these processes will be described later. Thus, ultimately, the normal data form (eg, PCM of uniform weight)
The waveform sample data restored to the form data) is D / A converted and acoustically pronounced.

--Description of Hardware Configuration Example-- Next, FIG. 2 shows a hardware configuration example of one embodiment of an electronic musical instrument that can be used for performing the above-described waveform data compression and reproduction processing. This will be described below. FIG.
The electronic musical instrument shown in FIG. 1 performs various processes and controls by a microcomputer, and includes a CPU (central processing unit) 10, a ROM 11 for storing programs and various data, and a RAM 12 for working and data storage.
It has. The analog signal external input unit 13 is for inputting an analog audio signal from the outside, and includes, for example, a microphone. Sampling device 1
Numeral 4 is for sampling the analog audio signal input from the analog signal external input unit 13 and converting it into digital waveform sample data encoded by PCM.

The waveform memory 15 is a readable and writable memory for storing waveform data, and is composed of, for example, a RAM, and may be made nonvolatile by a battery backup or other means as required. The waveform memory interface 16 controls reading and writing of the waveform memory 15. The disk memory device 17 comprises a large-capacity memory for storing waveform data and its driver.
It may be of any type, such as a built-in hard disk or a removable floppy disk. The disk interface 18 is an interface for reading and writing data with respect to the disk memory device 17. The DMA controller 19 reads / writes data from / to the disk memory device 17
A, and the disk memory device 1
It is used when transferring waveform data between the memory 7 and the waveform memory 15 and the like.

The waveform sample data obtained by PCM encoding the analog acoustic waveform signal input from the analog signal external input section 13 is subjected to waveform data compression processing. The original waveform data to be compressed sampled from the outside may be stored in the waveform memory 15 or may be temporarily stored in the disk memory device 17. The above-described processing (eg, removal of the envelope and extraction or creation of the attack portion and the repetition portion) of the original waveform data may be performed by using the microcomputer of the electronic musical instrument, or may be performed by the disk memory device 17.
May be stored once, set in a separate waveform processor or a waveform processing computer, and performed there. In the former case, a predetermined area of the RAM 12 or the waveform memory 15 may be used as a buffer memory in the course of the processing. Is stored in the waveform memory 15. In the latter case, a plurality of cycles of compression target waveform data consisting of a large number of processed sample points are loaded into the electronic musical instrument from the disk memory device 17 and stored in the waveform memory 15. Of course, original waveform data sampled by a separate appropriate sampling system is stored in a floppy disk or the like, and is stored in a disk memory device 1.
7 may be taken into the electronic musical instrument and stored in the waveform memory 15.

The compression target waveform prepared in the waveform memory 15 as described above is subjected to predetermined data compression processing and reduction processing. In this embodiment, the data compression processing and the reduction processing are executed under the control of the microcomputer. The operation section 20 includes various switches for selecting / setting / controlling a tone normally provided in an operation panel section of the electronic musical instrument, and switches and displays for selecting / setting / controlling other tone elements and various effects. In addition to the above, a switch, a display, and the like used for setting the above-described various types of data during the waveform processing, data compression, and reduction processing may be provided, but details thereof are omitted. The waveform buffer memory 21 is a buffer that temporarily stores the processed or processed waveform data when the data compression processing and the reduction processing are being executed. The waveform data subjected to the data compression and reduction processing stored in the buffer memory 21 is read out, and the processed waveform data is written to the waveform memory 15 while performing the above-described stuffing processing and hidden bit insertion processing.

As is generally known, the keyboard section 22 has a plurality of keys for designating the pitch of a musical tone to be generated. When a musical tone is reproduced, various parameters for musical tone generation are set in a desired state by the operation unit 20, as is generally known. Then, a desired key is pressed by the keyboard unit 22. The tone generator 23 reads out waveform data from the waveform memory 15 in accordance with various parameter setting states of the operation unit 20 and key press information of the keyboard 22, and generates a tone signal based on the waveform data. In this sound source section 23,
The above-described data bit length matching processing and hidden bit separation processing are performed, and demodulation processing and weight restoration calculation processing of compressed waveform sample data are also performed. The digital waveform sample signal generated from the sound source section 23 is converted into an analog signal by the D / A converter 24, and is given to the sound system 25 to be acoustically generated.

--Description of Blocks and Frames-- A compression target waveform stored in the waveform memory 15 is a PC.
M-coded fixed bit length (for example, one sample is 16 bits)
Bit), which consists of a number of sample points. When this is compressed, it is handled by dividing it into a block section and a frame section as described above. As an example, one block is composed of 1024 samples, and a series of compression target waveforms corresponding to one sound is generally composed of a larger number of samples as a whole, and therefore, a block section may be divided into a plurality of blocks. it can. One block is composed of 64 frame intervals, and thus one frame interval is composed of 16 sample points. In the compression and reduction processing of the waveform data, the processing is performed in accordance with the unique compression coefficient and weight coefficient for each block section. That is, the compression coefficient and the weight coefficient are common within one block section. In the variable bit length processing of the waveform data, a unique variable bit length is set for each frame section. That is, the bit length of the waveform sample data is common within one frame section.

--Outline of Compression and Writing-- FIG. 3 is a flowchart showing an outline of the entire process from the compression of the waveform data to the writing to the memory, which is executed under the control of the microcomputer. Things. First, in step 30, various types of data set in the above-mentioned "data setting" are received, and the data compression process is started. For example, the waveform memory 15
As described above, the read start address of the waveform to be compressed and the limited bit number data for each block are set according to the operator's request as described above. In the next step 31, the contents of the block counter for counting the block number for identifying the block section being compressed and the sample counter for counting the sample number for identifying the sample point in the block are initialized to 0. Reset to. Also, the contents of various registers are set to predetermined initial values. For example, the limited bit number data set for each block is set in the register storing the limited bit number.

In the next step 32, the waveform data of the first block section of the waveform to be compressed is stored in the waveform memory 1 based on the read start address set as described above.
Read from 5 Then, predetermined data compression processing and reduction processing are performed on the waveform data in the first one block section. Specific examples of the data compression processing and the reduction processing will be described later. In the next step 33,
Data indicating the start address of the memory area for storing the waveform data to be compressed is stored in the waveform start address table WST. When writing the compressed waveform data to the waveform memory 15, the start address stored in the waveform start address table WST is referred to, and the writing of the compressed waveform data is started from the start address. When reading the compressed waveform data, the start address stored in the waveform start address table WST is referred to, and reading is started from the start address. In the next step 34, head data of the compressed waveform data is written in the header of the area for storing the compressed waveform data.

Here, the format of the storage area of the compressed waveform data in the waveform memory 15 is exemplified as shown in FIG. The waveform numbers 1 to n correspond to n kinds of sounds or timbres, and the waveform data corresponding to the n kinds of sounds or timbres can be stored in the waveform memory 15. The number n may be fixed or variable. The waveform start address table WST stores start address data for each of the waveform numbers 1 to n. The data area is an area for storing waveform data for each of the waveform numbers 1 to n, and has a header section and a waveform sample data storage section corresponding to each of the waveform numbers 1 to n. In step 32, start address data is written to the waveform start address table WST corresponding to the waveform number assigned to the waveform to be compressed. The start address data specifies the start address of the waveform data storage area for the waveform number in the data area.

Examples of head data stored in the header section include waveform name data, compression flag flag data, envelope identification data, initial reproduction control data, address size data (or end address data), and the like. The waveform name data is data indicating a waveform name (for example, a tone color name). The compression presence / absence flag data is a flag indicating whether or not this waveform has been subjected to compression processing. In this embodiment, the description has been made on the assumption that compression processing is performed. However, since it is possible to select not to perform compression processing, such a flag is provided. Envelope identification data means whether the waveform data is provided with an entire volume envelope from the start to the end of sound generation, or is provided with an envelope only in the attack part, or The fluctuating volume envelope is data for identifying a volume envelope application state, such as whether the volume envelope is not provided (that is, normalized to a certain level) or the like.

The initial reproduction control data is various kinds of control data necessary for reproducing the waveform data in the first block section and the frame section, and is necessary for demodulating the compressed waveform sample data. Compression coefficient data, weighting coefficient data necessary for weight restoration calculation processing,
It is composed of data on the number of bits necessary for matching the data bit length. Since the data compression and the weight reduction processing are common in one block and the variable data bit length is common in one frame, the initial reproduction control data includes the compression coefficient and weight coefficient data for the first block and the first data. And bit number data for the first frame of the block. Note that the compression coefficient and the weight coefficient data for each block after the second block are written as hidden bit data in the storage area of the waveform sample data of the block immediately before the block together with the waveform sample data. . Also, the first
The bit number data of each frame after the second frame of the block is written as hidden bit data in the storage area of the waveform sample data of the immediately preceding frame as mixed with the waveform sample data. The compression coefficient and weight coefficient data relating to the first block and the bit number data relating to the first frame of the first block are stored in the header section as initial reproduction control data because there is no previous block or frame. It is.

The address size data (or end address data) is data indicating the total number of addresses (address size) storing the waveform data corresponding to the waveform number. This may be data indicating the address storing the last waveform sample data related to this waveform number, that is, data indicating the end address. As described above, the number of bits (ie, data length) of one sample of the waveform data after the data compression processing does not always match the number of bits of one address of the memory, and has a variable bit length. Instead of being stored one-to-one at one address, the data is packed and written. Therefore, the total storage addresses of the waveform data after the data compression processing are determined after the compression processing is completed. I don't know if I look at it. For this reason, address size data or end address data which is determined at the time when the data compression processing and the writing processing are completed are written into this header portion, so that it is convenient for the subsequent reproduction processing. Therefore, in the step 34, the address size data or the end address data is not written in the header portion.

The head data stored in the header section is not limited to the above example, and may be any data as needed. For example, when a section of a waveform is repeatedly read, loop address data for designating the section for repeated reading may be stored. When data compression is selectively performed according to any one of a plurality of data compression methods, data indicating the selected data compression method is stored in a header portion, which is convenient for demodulation. Alternatively, data indicating the name of the original waveform may be stored in the header section, read out and displayed as appropriate, and provided for the player's reference.

Returning to FIG. 3, in step 35, the waveform data of the next one block section of the waveform to be compressed is read out from the waveform memory 15, and a predetermined data is A compression process and a reduction process are performed. The waveform data of the first block which has been subjected to the data compression processing and the reduction processing by the processing of step 33 is temporarily stored in the waveform buffer memory 21 (FIG. 2). Then, the waveform data of the second block subjected to the data compression processing and the reduction processing by the processing in step 35 is also temporarily stored in the waveform buffer memory 21. As described above, the waveform buffer memory 21 temporarily stores compressed and reduced waveform data of two adjacent blocks (the preceding block and the next block).

In the next step 36, the waveform data of the preceding block of the waveform data temporarily stored in the waveform buffer memory 21 is processed into variable bit length data, and the processed data is written into the waveform memory 15. Do. Here, when writing the waveform data of the preceding block,
In the previous step 35, a process of writing the compression coefficient and the weighting coefficient data for the next block after the compression processing is completed in the waveform data is performed. Specific examples of the variable bit length processing and the write processing will be described later in detail. In this step 36, bit length processing and write processing are first performed on the waveform data of the first block.
In this case, the start address of the write is specified by the start address table WST.

In the next step 37, it is determined whether compression of all waveform data has been completed. If the processing has not been completed yet, the process goes to step 38 to indicate the next block. Then, the process returns to step 35, where the compression and reduction processing of the waveform data for the designated next block is performed, and the processing of step 36 is performed. Thus, the blocks are sequentially switched, and the processing of steps 35 and 36 is repeated. When the compression of all the waveform data is completed, step 3
7 is YES, and the procedure goes to step 39. Step 39
Then, in the header part of the waveform number currently being processed,
The address size data or end address data relating to the waveform data is written. Although not described in detail, the write address is appropriately designated by the address pointer when writing the compressed waveform data to the waveform memory 15, so that when the compression of all the waveform data is completed, the address pointer indicates the end address. doing. Therefore, in step 39, the address size data or end address data relating to the waveform data is automatically determined, and is written.

--Compression and Reduction Processing (First Embodiment)-The compression and reduction processing of the waveform data executed in the steps 32 and 35 is performed under the control of the microcomputer. FIG. 5 shows an embodiment (first embodiment) of waveform data compression and reduction processing performed under the control of the microcomputer.
FIG. 3 is a functional block diagram showing an example of the present invention). This waveform data compression and reduction processing will be described with reference to a functional block diagram as shown, and the presentation of a flowchart will be omitted. It goes without saying that the waveform data compression and reduction processing can be performed not only by the microcomputer but also by a hardware circuit according to the functional block diagram as shown. In the first embodiment, the waveform data reduction processing according to the weight coefficient
It is performed before data compression processing using a filter. In FIG. 5, the waveform memory reading unit 40
Is for reading the compression target waveform data from the waveform memory 15, and a read address signal is given under the control of the control unit 41. The control unit 41 is for performing overall control, and supplies a control signal to each unit. The block counter 42 counts the number of the block currently being processed. The sample counter 43 counts the number of the sample currently being processed.

As described above, in the initial state (at step 31 in FIG. 3), under the control of the control unit 41, the block counter 42 and the sample counter 43 are initialized to 0.
Reset to. Each time the waveform data for one sample is compressed and reduced, the sample counter 43 is incremented by one.
Count up. In addition, every time the processing for one block is performed, the block counter 42 is incremented by one. The sample counter 43 is reset to 0 when starting processing for one block. The read start address for specifying the range of the compression target waveform is
1 and the read address of the waveform memory 15 is obtained by adding the count value of the sample counter 43 to this start address and adding the count value of the block counter 42 with a predetermined weight (with a weight of 1024 times). Is specified. The read address data is given to the waveform read unit 40, and specifies the address of the sample data to be read from the waveform memory 15.
In addition, since one frame period is composed of 16 samples, bits higher than the fifth bit of the sample counter 43 are also used as data indicating a frame number.

The limited bit number register 44 stores data indicating a preset limited bit number for each block section, as described above, and performs each block section by the initial setting process in step 31 of FIG. The data indicating the limited number of bits for each is fetched into the register 44. In accordance with the output of the block counter 42, that is, the block number data, the limit bit number instruction data set corresponding to the block currently being processed is read from the register 44. The shift data generating section 45 generates shift data, that is, a weighting coefficient, and takes into consideration the limited bit number instruction data and the other data for the block given from the limited bit number register 44, which are appropriate shift data, that is, a weighting coefficient. Generate coefficients. This shift data generator 4
The shift data generated from 5 is registered in the shift data register 46. The shift data registered in the shift data register 46, that is, the weight coefficient, is given to a shift circuit 47 (that is, a weight calculation circuit).

The shift circuit 47 receives the waveform sample data read from the waveform memory 15 via the waveform read section 40, and shifts the value of the sample data downward by the number of bits corresponding to the shift data. , Performs a reduction operation of the value of the sample data. For example, if the waveform sample data having 10 bits of effective bits is shifted downward by 2 bits, the number of effective bits of the waveform sample data is reduced to 8 bits. The waveform sample data output from the shift circuit 47 is input to the compression filter unit 48. The compression filter section 48 performs a data compression process using a filter. The filter coefficient of the compression filter unit 48, that is, the compression coefficient, is calculated for each block section according to the linear prediction method based on the waveform sample data for each block section. For this purpose, a Hamming window multiplication unit 49, a Hamming buffer 50,
A coefficient generation operation unit 51 and a coefficient register 52 are provided. This detailed example will be described later. The calculated compression coefficient is stored in the coefficient register 52 and input to the compression filter unit 48.

The waveform sample data output from the compression filter unit 48 is temporarily stored in the block buffer 55 via the block buffer write control unit 53. The data stored in the block buffer 55 is appropriately read and controlled by the block buffer read control unit 54, and is input to the compression filter unit 48. This is because a one-stage filter circuit is used as the compression filter unit 48, and a two-stage compression filter is configured by circulating data therethrough. Therefore, to be precise, the waveform sample data output from the compression filter unit 48 in the second round is the data that has been subjected to the compression processing. The bit number detection unit 56 detects the number of effective bits of the compressed waveform sample data output from the compression filter unit 48. For example, in the compression-processed waveform sample data output according to the 16-bit standard, the higher-order “0” bits are excluded, and the number of lower bits from the highest-order bit among the bits where “1” is set is calculated. Detected as valid bits. Then, the bit number detection section 56 detects the maximum value of the effective bit number for each frame section and outputs it as frame-specific bit number data FBN. This bit number data per frame FBN
Are temporarily stored in the block buffer 55 via the block buffer writing control unit 53, and are used in the variable bit length processing for each frame. Also, the bit number detection unit 5
In step 6, the bit number data FBN per frame is compared with the bit number data stored in the bit number register 57. If the bit number data FBN per frame obtained this time is larger, this is stored in the bit number register 57. Store.

When the processing for one block is completed, the bit number data finally stored in the bit number register 57 is the maximum value of the effective bit number in the block. This is given to the shift data generating unit 45 as MBN. When the processing for one block is completed, the shift data generation unit 45 compares the limited bit number data of the block given from the limited bit number register 44 with the maximum bit number data MBN, and determines the maximum bit number data MBN. If is large,
Since the compressed waveform data exceeds the limited bit number set corresponding to the block, the control unit 41 is instructed to perform the compression and reduction processing on the block again, and the shift data to be supplied to the shift data register 46. The value of is made larger than the last time. In this manner, the shift data, that is, the value of the weighting coefficient is initially set to an appropriate predetermined value (a constant value or a value arbitrarily set for each block),
Judging from the relationship with the limited number of bits set corresponding to the block, the shift data, that is, the value of the weighting coefficient is automatically switched, and the compression and reduction processing for the block is performed again. The shift data, that is, the weighting coefficient is automatically controlled so that the data after the data compression and reduction processing falls within the limited bit number set corresponding to the block. The finally determined shift data relating to the block, that is, the weighting coefficient, is temporarily stored in the block buffer 55 via the block buffer write control unit 53, and later written into the waveform memory 15 together with the waveform sample data. Of course, instead of employing such a method of automatically determining the shift data, that is, the weight coefficient, the shift data may be manually set for each block.

When the processing for one block is completed, the shift data generating section 45 compares the limited bit number data of the block given from the limited bit number register 44 with the maximum bit number data MBN, and M
If the BN is smaller, the waveform data after compression is within the limited number of bits set corresponding to the block. A count-up instruction signal is provided to the block counter 42 and the control unit 41. As a result, the block counter 42 is counted up by one, and instructs to perform the processing of the next block. The block buffer 55 is a buffer memory included in the waveform buffer memory 21 of FIG. 2, and its memory format is exemplified in FIG. The block buffer 55 includes waveform data buffers BW (A) and BW (B).
, And one block of waveform sample data can be temporarily stored in each of them, and a total of two blocks of waveform sample data can be temporarily stored. Which buffer BW (A), BW
Whether to write to (B) depends on whether the block count value is even /
It can be switched alternately according to oddities. Thus, the waveform data buffer BW for two blocks
(A) and BW (B) are obtained because the waveform memory 1
This is because when writing the waveform data of a certain block into block 5, the compression coefficient and the shift data (weighting coefficient) for the next block are controlled to be written together as hidden bit data. Note that two adjacent blocks temporarily stored in the block buffer 55 are referred to as block A and block B for convenience.

Parameter buffers BP (A), BP
(B) is for temporarily storing control data to be written mixedly with the waveform sample data as hidden bit data. The compression coefficient and shift data (weight coefficient) of the block A or B and the block A Alternatively, bit number data for each frame in B (bit number data FBN for each frame) is stored. The header buffer is
This is a buffer for temporarily storing head data to be stored in the header section of the waveform memory 15. The filter delay buffer temporarily stores the signal data held at the end of the compression processing for the previous block in the delay circuit for delaying the unit of the signal in the compression filter unit 48. As described above, this is to prepare for re-compression and compression of one block of data when the number of bits of the waveform sample data after compression and reduction does not fall within the limited number of bits. is there. That is, in order to enable such re-execution, the content of the signal data in the delay circuit unit in the compression filter unit 48 must be reproduced to the content immediately after the end of the compression processing for the previous block. For this purpose, the signal data held at the end of the compression process for the previous block in the delay circuit unit in the compression filter unit 48 is temporarily stored in the filter delay buffer, and it is required to start over in the compression process for the next block. Then, the data stored in the filter delay buffer is set in the delay circuit unit in the compression filter unit 48, and the initial state for performing the compression process on the block is reproduced.

Returning to FIG. 5, the variable bit length processing and writing processing unit 58 reads out the compressed data of one block stored in the block buffer 55, and determines the number of data bits as the maximum bit in each frame section. In addition to performing “variable bit length processing” for trimming to the bit size of the number data FBN, the compression coefficient and shift data (weight coefficient) of the next block are mixed and written in the waveform sample data, and the variable bit of the next frame is written. It performs processing of writing data indicating several FBNs in the waveform sample data in a mixed manner. A detailed example will be described later.

--- Description of Compression Filter Unit (First Embodiment)-FIG. 7 conceptually shows a basic configuration example of the shift circuit unit 47 and the compression filter unit. 48A and 48B are cascade-connected in two stages.
In the first-stage filter 48A, the reduced waveform sample data output from the shift circuit unit 47 is transferred to the delay unit DA0.
And the multiplier M0 multiplies the output of the delay section DA0 by a coefficient a0. The output of the delay unit DA0 is input to the second delay unit DA1, and the output of the delay unit DA1 is multiplied by the coefficient a1 by the multiplier M1. In this way, the product obtained by multiplying the data one sample before and the data two samples before by the coefficient is added by the adder ADD, and the sum (convolution sum) is subtracted from the data at the current sample point by the subtractor SUB. The output of the subtractor SUB is input to the second-stage filter 48B. The second stage filter 48B is the first stage filter 48A.
And the coefficients b0 and b1 are different. Adopting the configuration in which the secondary filters 48A and 48B are connected in cascade in two stages has the advantage that the data compression process can be performed efficiently and the setting of the compression coefficient becomes easy. Further, a hardware circuit of a second-order filter for one stage may be prepared as the compression filter unit 48 and may be used in a time-division manner, so that the hardware configuration is simplified.

FIG. 8 shows an example of a hardware circuit of the compression filter section 48 comprising a one-stage secondary filter, and a subtracter 59 for subtracting the convolution sum from the input waveform sample data at the current sample point. Is output through a limiter 60. Further, the adder 61 adds the convolution sum to the output of the limiter 60 to reproduce the input waveform sample data at the current sample point.
Input to 3,64. In the multipliers 65 and 66, each delay unit 6
The outputs of 3, 64 are multiplied by the compression coefficients c0 and c1, and the convolution sum is obtained by the adder 67. Compression coefficient c0,
The values of c1 are a0 and a1 when this compression filter unit 48 is used as the first-stage filter 48A, and b0 and b1 when it is used as the second-stage filter 48B. At the time of the above-described redo processing, the contents of the filter delay buffer (the signal data held at the end of the compression processing for the previous block) are set in the delay units 63 and 64.

--Generation of Compression Coefficient-- Next, the Hamming window multiplier 49, the Hamming buffer 5
An example of a procedure for generating a compression filter coefficient according to a linear prediction method using 0, a coefficient generation operation unit 51, and a coefficient register 52 will be described with reference to FIG. First, one block (1024 samples) of waveform sample data is sequentially read from the waveform memory 15, input to the Hamming window multiplier 49, and multiplied by a Hamming window function. In this case, the Hamming window function also includes 1024 samples, and each sample value of the Hamming window function is multiplied by one block (1024 samples) of waveform sample data.
Then, the product Sn (where n = 0, 1, 2, 3,...)
1023) is stored in the humming buffer 50. Next, the coefficient generation calculation unit 51 obtains the autocorrelation function Ri for i = 0, 1, and 2 according to the following equation based on the waveform sample data Sn weighted by the Hamming window. Ri = ΣSnSn + i (where the cumulative range of Σ is n = 0
To 1023) Next, based on the autocorrelation function Ri obtained as described above,
The compression coefficients c0 and c1 are obtained according to the following equation. c0 = (R1, R0-R1, R2) / (R0, R0-R1, R1) c1 = (R2, R0-R1, R1) / (R0, R0-R1, R1) The first stage compression filter When the coefficients are obtained, c0 and c1 correspond to a0 and a1, and when the second stage compression filter coefficients are obtained, c0 and c1 correspond to b0 and b1.

Next, the compression filter coefficients c0 and c1 just obtained are
Is determined to be the first stage, and if so, the compression filter coefficients c0 and c1 just obtained, that is, a0 and a1 are stored in the coefficient register 52 and the compression filter unit 48
, And sequentially reads the waveform sample data relating to the block currently being processed from the waveform memory 15 and inputs it to the compression filter unit 48, where the compression filter coefficients c0, c0,
The compression processing according to c1, that is, a0, a1 is performed. Thus, the output of the first-stage filter 48A is obtained, and the obtained output is input to the Hamming window multiplication unit 49, where the output is multiplied by the Hamming window function. Then, the same processing as described above is repeated, and the product S
n is stored in the Hamming buffer 50, the autocorrelation function Ri is obtained, and the compression coefficients c0 and c1 are further obtained.
This time, the obtained compression coefficients c0 and c1 correspond to the compression filter coefficients b0 and b1 of the second stage.
2 and end the process. Although the description has been made before and after, in this way, after calculating the compression filter coefficients a0, a1, b0, and b1 for the block, the compression filter unit 48
Is used to compress the waveform sample data of the block as described above.

—Description of Variable Bit Length and Hidden Bit— One block of compressed data stored in the block buffer 55 is written to the waveform memory 15 by the variable bit length processing and writing processing unit 58. It is. FIG. 10 is a functional block diagram for explaining the processing operation of the variable bit length processing and writing processing unit 58. FIG. 11 schematically shows the procedure of the variable bit length processing and writing processing executed by the variable bit length processing and writing processing unit 58. In other words, FIG. 11 corresponds to step 3 in FIG.
6 shows the processing performed in step 6 in some detail, and FIG. 10 is a functional block diagram for performing processing equivalent to the procedure performed in FIG. First, an outline of the specifications of the variable bit length processing and writing processing of the waveform sample data and the writing processing of the hidden bit data performed by the variable bit length processing and writing processing unit 58 will be described as follows. FIG.
FIG. 2 shows an example of the format of the waveform sample data and the hidden bit data after the variable bit length processing.

1) Variable Bit Length The number of bits of the waveform sample data is common within one frame, and is variable for each frame. Specifically, based on the frame-by-frame bit number data FBN which is the maximum value of the number of effective bits detected in the frame,
Each sample data in the frame is extracted from the lower bits by the number of bits of the FBN. As a result, the number of bits of each sample data in the frame can be reduced by securing valid bits. FIG.
In the example of 2, the size of the waveform data in frame 0, that is, the bit length is 11 bits, and in frame 1, it is 10 bits.
Bit, frame 2 has 12 bits.

2) Hidden bits a) Bit number indicating data for each frame Data indicating the number of bits of the waveform sample data processed into a variable bit length for each frame as described above is the waveform sample of the previous frame. Write as hidden bit data mixed with data. The bit number indication data is 4-bit data, and is separated one bit at a time.
It is positioned on the lower side of the least significant bit LSB of the waveform data for the first four samples of the previous frame. In the example of FIG. 12, each bit of the hidden bit data corresponding to the bit number indication data is indicated by HB0, HB1, HB2, HB3. The binary coding weight of each hidden bit is H
B3 is the highest order, and hereafter HB2, HB1, HB0. In the example of FIG. 12, the contents of the hidden bits HB3 to HB0 of the frame 0 are “1010”, and the data length of the next frame 1 =
Indicates 10 bits. The contents of the hidden bits HB3 to HB0 of the frame 1 are "1100", which indicates that the data length of the next frame 2 is 12 bits. At the sample points having these hidden bits HB0 to HB3, the data length is substantially one bit larger than other sample points in the same frame. However, such hidden bits HB0 to HB3
, Ie, the size of the substantial waveform data is constant within the same frame. In addition,
As for the first frame 0 of the first block, since there is no frame preceding it, the bit number indication data is written in the header as described above. The reason why the bit number indicating data of the next frame is mixedly written in the waveform data of the previous frame and written is obvious so that the bit number indicating data can be read in advance in the reproducing process. That's why.

B) Shift Data (Weight Coefficient) The shift data (weight coefficient) for each block is written as hidden bit data mixed with the waveform sample data of the previous block. This shift data (weight coefficient) is 4-bit data, and is separated by 1 bit, and the least significant bit LS of the waveform data of 4 samples from the 5th to the 8th of the first frame 0 of the previous block is
B, respectively. In the example of FIG. 12, each bit of the hidden bit data corresponding to the shift data (weight coefficient) is indicated by HS0, HS1, HS2, and HS3.

C) Compression coefficients Four compression coefficients a0, a1, b0, b1 for each block
Is written as hidden bit data mixed with the waveform sample data of the previous block. Each compression coefficient is 8-bit data, and is separated by one bit to obtain a coefficient b
1 is positioned on the lower side of the least significant bit LSB of the waveform data for the ninth to sixteenth samples of the first frame 0 of the previous block, and the coefficient b
0 is located on the lower side of the least significant bit LSB of the waveform data for the ninth to sixteenth samples of the second frame 1 of the previous block, and the coefficient a1 is located on the third side of the previous block. 9 of frame 2
The lowermost bit LSB of the waveform data for the 8th to 16th samples is respectively positioned on the lower side, and the coefficient a0 for the ninth to 16th 8th samples from the fourth frame 3 of the previous block is stored. It is located on the lower side of the least significant bit LSB of the waveform data. In the example of FIG. 12, each bit of the hidden bit data corresponding to one compression coefficient is indicated by HC0 to HC7.

FIG. 13 shows an example of a memory format when data of a variable bit length having a format as shown in FIG. 12 is actually packed in the waveform memory 15 and stored. In the case of FIG. 13, the size of the storage address of the waveform memory 15, that is, the data length is fixed to 16 bits per address, and each address is accessed by an address signal. Instead of storing data of one sample point per address, data of a variable bit length is appropriately packed and stored. For example, a hidden bit HB0 accompanying the waveform data of the sample point 0 is added to the least significant bit of the address A0.
Is stored, the waveform data of sample point 0 is stored in the upper 11 bits, the hidden bit HB1 accompanying the waveform data of sample point 1 is stored in the upper 1 bit, and the waveform data of sample point 1 is stored in the upper 3 bits. Are stored in the lower 3 bits of the data. The remaining upper 8 bits of the waveform data at sample point 1 are stored in the lower 8 bits of address A1. As shown in the figure, the waveform data of each sample point and the data of the hidden bits are packed and stored. In FIG. 13, the numbers written in the address area indicate the sample point numbers of the waveform data stored therein, and the hatched portions indicate the areas where the hidden bits are stored. As described above, in order to efficiently pack data and store it in the waveform memory 15, one data is appropriately divided and stored over a plurality of addresses.

--- Variable Bit Length Processing and Writing Processing-- An example of variable bit length processing and writing processing will be described with reference to FIGS. In FIG. 10, the control unit 6
Numeral 8 controls the overall operation of the variable bit length processing and writing processing section 58. It is assumed that the control section 68 executes a processing program as shown in FIG. 11 to control the variable bit length processing and writing processing. May be. The sample and frame counter 69 determines the sample number SN of the waveform data to be read from the block buffer 55 by the sample clock S.
It increments according to CK, and also increments the frame number FN every 16 samples. The sample reading unit 70 controls to read the waveform data from the block buffer 55 corresponding to the sample number SN specified by the sample and frame counter 69. The least significant bit BNLSB of the block number data counted by the block counter 42 (FIG. 5) is given to the sample reading section 70 to notify the even / odd of the block number for which the compression processing has been completed. As a result, the two waveform data buffers BW (A) and BW of the block buffer 55
(B) It is specified from which of the waveform data is to be read out (FIG. 6). For example, even block numbers 0,
The waveform data of 2, 4,...
(A), and store the odd block numbers 1, 3, 5,
.. Are stored in the waveform data buffer BW (B). If the least significant bit BNLSB of the block number data is "0", the block of the even number has just finished the compression processing. Is stored in the waveform data buffer BW (A), and the preceding block is an odd block number, which is the waveform data buffer BW (B).
Will be stored. Therefore, the preceding block is an odd-numbered block stored in the waveform data buffer BW (B), and controls to read out the waveform data from this buffer BW (B). On the other hand, if the least significant bit BNLSB of the block number data is "1", the odd numbered block has just finished the compression processing, and the preceding block is the waveform data buffer BW (A).
Is controlled so that the waveform data is read from the buffer BW (A).

The shift data readout unit 71 includes parameter buffers BP (A), BP in the block buffer 55.
Control to read out the shift data (weight coefficient) from (B). The least significant bit BNLSB of the block number data is provided to the shift data reading unit 71 to notify the even / odd of the block number for which the compression processing has been completed. This indicates which of the two parameter buffers BP (A) and BP (B) (FIG. 6) of the block buffer 55 should read the shift data. For example, in the case of the above-described example, if BNLSB is “0”, the data in the waveform data buffer BW (B) is read out as the preceding block (odd-numbered block) and is read out from the waveform memory 15.
, The parameter data for the next block (even-numbered block) is stored in the parameter buffer B
Since the data is stored in P (A), the shift data readout unit 71 uses the parameter buffer BP (A)
And reads out the shift data for the next block from.
Conversely, if BNLSB is "1", the waveform data buffer B is regarded as a preceding block (an even-numbered block).
Since the data of W (A) is read and written into the waveform memory 15, the shift data reading unit 71 stores the shift data for the next block in the parameter buffer BP.
Read from (B).

The compression coefficient reading section 72 is provided with parameter buffers BP (A) and BP (B) in the block buffer 55.
To control the reading of the compression coefficients a0, a1, b0, b1 from. As described above, the least significant bit B of the block number data
NLSB is supplied to the compression coefficient reading section 72, and the block buffer 55 is provided in accordance with the even / odd of the block number.
The compression coefficient for the next block is read from one of the two parameter buffers BP (A) and BP (B). The next frame bit number data reading section 73 outputs the frame-specific bit number data FB for the next frame according to the frame number FN from the sample and frame counter 69.
N is the parameter buffer B in the block buffer 55
Reading control is performed from one of P (A) and BP (B).
For example, the least significant bit BNLSB of the block number data
Is "0", the waveform data stored in the waveform data buffer BW (B) is read out as the preceding block and is written into the waveform memory 15, so that the next frame is read from the parameter buffer BP (B) of the preceding block. The bit number data FBN for each frame is read out. Here, the read bit number data is written as hidden bit data.

Current frame bit number data reading section 74
Sends the frame-by-frame bit number data FBN for the currently processed frame to the block buffer 55 in accordance with the frame number FN from the sample and frame counter 69.
Control from one of the parameter buffers BP (A) and BP (B). For example, if the least significant bit BNLSB of the block number data is "0", the preceding block is a B block, as described above, so that the number of bits per frame data for the frame currently being processed is stored in the parameter buffer BP (B). Read FBN. Here, the read bit number data is used for adjusting the bit number of the waveform data of the frame. The hidden bit instructing unit 75 includes the sample and frame counter 6.
In accordance with the sample number SN of No. 9, it is determined whether or not the sample point is where the hidden bit data is to be inserted, and what kind of data is to be embedded as the hidden bit data, and instructed. As described with reference to FIG. 12, the bit number data of the next frame, the shift data of the next block, and each compression coefficient of the next block are stored in a predetermined sample number (1
Since the data is dispersedly embedded as hidden bit data below the waveform data of the sample number in the block), the predetermined sample number is determined and an appropriate instruction is issued.

In response to an instruction from hidden bit designating section 75, hidden bit assigning section 76 has a predetermined number below the waveform sample data read from sample reading section 70 at the sample number to which hidden bit data is to be added. One bit of the hidden bit data is added. From the shift data reading unit 71, the compression coefficient reading unit 72, and the next frame bit number data reading unit 73, data to be embedded as hidden bit data (4-bit shift data, 8-bit compression coefficients a0 to b1, and 4-bit The next frame bit number data) is provided to the hidden bit providing unit 76. As described with reference to FIG. 12, the hidden bit assigning unit 76 selects one predetermined bit among the predetermined sample numbers and hides it at the lower level of the waveform sample data of the sample number. Add as bit data. The adding unit 77 adds 1 to the bit number data of the current frame read from the current frame bit number data reading unit 74 at the sample number to which the hidden bit data is added according to the instruction from the hidden bit instruction unit 75. I do. Thereby, at the sample point to which the hidden bit data is added, the value of the current frame bit number data is
It is incremented by one in response to the addition of one bit.

The waveform data output from the hidden bit assigning section 76 is input to the upper bit input MSBIN of the data synthesizing section 78.
Given to. Lower bit input LS of data combining section 78
The output of the selector 79 is given to BIN. The data synthesizing unit 78 controls the synthesizing position so that the waveform data given to the input MSBIN is positioned above the bit position indicated by the bit position indicating data BPP output from the bit position indicating counter 80, The data of the upper bit input MSBIN and the data of the lower bit input LSBIN are combined to create 32-bit data. The 32-bit data output from the data synthesizing unit 78 is delayed by one sample clock in the buffer register 81. Then, of the 32-bit output of the buffer register 81, the upper 16 bits MSB16 are applied to the “1” input of the selector 79, the lower 16 bits LSB16 are applied to the “0” input of the selector 79, and the waveform memory writing unit 82
Given to.

The bit position indication counter 80
7 is a modulo 16 counter that adds the bit number data of the current frame output from 7 according to the sample clock SCK, and outputs bit position indication data BPP according to the count value. When the count value overflows (when it exceeds 16), an overflow signal OVF is output. The overflow signal OVF is applied to the selection control input of the selector 79, and if no overflow occurs, the lower 16 bits of the buffer register 81
The bit output LSB 16 is selected via the “0” input of the selector 79, and the lower bit input LSB of the data
Input to IN. On the other hand, when an overflow occurs, the upper 16 bits output MSB of the buffer register 81 are output.
16 is selected via the “1” input of the selector 79 and input to the lower bit input LSBIN of the data synthesizing unit 78.
The overflow signal OVF is supplied to the waveform memory writing unit 82, and instructs the waveform memory 15 to write the lower 16-bit output LSB16 of the buffer register 81 when an overflow occurs. Waveform memory 15
Is designated by a write address counter 83. In the write address counter 83, a write start address is set first, and thereafter, is incremented according to an overflow signal OVF.

The data synthesizing section 78 guides the data input to the upper bit input MSBIN to any one of the 32-bit output bit position ranges in accordance with the instruction of the bit position instruction data BPP, and outputs it. The 16-bit data input to the lower bit input LSBIN is directly output to the lower 16-bit range of the 32-bit output, and is output at the bit position where the data input to the upper bit input MSBIN is output. The data input to the upper bit input MSBIN is output with priority. This is because the higher-order bit “0” of the 16-bit data input to the lower-bit input LSBIN is packed with the data input to the upper-bit input MSBIN. The output data appears as it is on the output side. The bit position indication data BPP takes 16 values from 0 to 15, and indicates the bit position of any of the lower 16 bits of the 32-bit output of the data synthesizing unit 78 using this value. MSB of upper bit input
So that the least significant bit of the data input to IN comes
Deriving the data. When the data of sample number 0 is input to the upper bit input MSBIN of the data synthesizing unit 78,
Assuming that the value of the bit position indication counter 80 is 0 and the bit position indication data BPP indicates 0, an example of a data synthesis state is shown in FIG. At this time, the data of the sample number 0 input to the upper bit input MSBIN of the data synthesizing unit 78 is packed near the least significant bit of the data synthesizing unit 78 as shown in FIG.

At the next sample timing, the data of the lower 16 bits LSB 16 of the data synthesizing section 78 is supplied to the lower bit input LSBIN of the data synthesizing section 78 via the register 81 and the “0” input of the selector 79. At this time, the bit position indication counter 80 has counted the number of bits x of the data of the sample number 0, and the bit position indication data BPP indicates x. At this time, the data of the next sample number 1 is input to the upper bit input MSBIN of the data synthesizing unit 78, and
According to the instruction of BPP = x, as shown in FIG. 14B, the data is packed into the bit position range immediately above the data of sample number 0. When the data shown in FIG. 14B is output from the register 81, the bit number x of the data of the sample number 1 is further added in the bit position indication counter 80, and the count value becomes 2x. This value 2x is
It is assumed that the value causes an overflow. Then, due to this overflow, the lower 16-bit data LSB16 of the register 81 is written to the waveform memory 15. That is, the data of sample number 0 and a part of the data of sample number 1 are exactly packed into 1 address = 16 bits and written.

At this time, the selector 79 sets the register 81
Of the upper 16-bit data MSB16 of the data synthesizer 78 via the "1" input, and the lower bit input LSBI of the data synthesizer 78 is selected.
Enter N. That is, the rest of the data of the sample number 1 is input to the lower bit input LSBIN of the data synthesizing unit 78. At this time, the data of the next sample number 2 is input to the upper bit input MSBIN of the data synthesizer 78. The value of the bit position indication counter 80 is B
A PP = 2x-16, in response to an instruction of this, as shown in (c) of FIG. 14, the data of Sample No. 2 is packed immediately bit position range of the upper of the remaining data of the sample number 1. In this way, only the data of the number of valid bits specified by the bit number data (or the value obtained by adding 1 to the value when the hidden bit data is involved) is extracted,
The data is packed into the waveform memory 15 without waste.

Next, a description will be given along the entire flow of the variable bit length processing and the writing process with reference to FIG. Set to. Then, when the processing of each block is started, the least significant bit BNLSB of the block number data at that time is fetched and used for the above-mentioned even / odd determination of the block number. Next, the sample and frame counter 69 is reset. Then, the waveform data specified by the sample and the sample number SN of the frame counter 69 is read from one of the waveform data buffers BW (A) or BW (B) in the block buffer 55. Then, according to the sample number SN, the bit number data of the next frame, the shift data of the next block, and each compression coefficient of the next block are added to the waveform data as hidden bit data. The bit number of the data is determined according to the bit number data of the current frame and the presence / absence of hidden bits, the bit number of the data is trimmed to this bit number, and the data is written into the waveform memory 15 as described above. Do. Then, the above processing is repeated for one frame. After that, the parameter of the number of bits for each frame is switched, and the above processing is repeated. When the processing for one block is completed, this processing is completed.

When the writing process for all blocks related to the waveform is completed, the write address counter 83 of the waveform memory 15 indicates the end address. In step 39 of FIG. 3, the end address data at this time is stored in the header portion, or size data indicating the storage address range is obtained from the difference between the end address and the write start address, and this is stored in the header portion. I do.

--Reproduction Process-- An example of the process of reproducing and generating the compressed and reduced waveform data stored in the waveform memory 15 and generating sound will be described below. The sound source section 23 in FIG. 2 performs a reproduction process, and one embodiment thereof is shown in FIG. In FIG. 2, the microcomputer scans the keyboard section 22 and the operation section 20, detects key depression and key release, detects a selection state such as a tone color, and sets a plurality of key depression information (for example, 8).
Assigned to any one of the tone generation channels of. The microcomputer outputs, for each channel, a key code KC indicating the key assigned to each channel and a key-on signal KON indicating whether the assigned key is kept pressed or released. Number data TN indicating touch and touch data TD indicating key touch.
Is output. The output of the microcomputer is taken into the sound source unit 23 via the interface 90. The interface 90 outputs the key code KC of the key assigned to each channel and the key-on signal KON in a time-sharing manner according to a predetermined channel time-sharing timing, and outputs the tone number data TN and the touch data TD of the selected tone. I do. The sound source unit 23 performs various processes in 8-channel time division based on the data supplied from the interface 90, and generates time-division musical tone waveform signals for 8 channels.

The F number generating circuit 91 generates an F number which is a constant corresponding to a pitch frequency of a musical tone to be generated, in accordance with a key code KC given from the interface 90, and comprises, for example, a ROM or a table. . This F number is repeatedly accumulated by the accumulator 92, and a carry signal from an appropriate digit is output as a note clock pulse NCL. The note clock pulse NCL corresponds to the pitch frequency of the musical tone to be generated, and instructs the sampling point increment for each pulse. The note clock pulse NCL, that is, the sample point increment, is a data read command for the waveform memory 15 for one sample point per pulse. The clock and timing signal generation circuit 93 generates a system clock pulse and various other timing signals, supplies them to each circuit, and forms and outputs a key-on pulse and a key-off pulse based on a key-on signal KON provided from the interface 90. . The system clock pulse is a two-phase clock, and one cycle corresponds to the time slot width of one channel. The first key-on pulse KONP1 is a pulse that becomes "1" only once in the time slot of the corresponding channel when the key-on signal KON rises from "0" to "1", that is, at the start of key depression. The second key-on pulse KONP2 is such that the key-on pulse KONP1 is "1".
Is a pulse which becomes "1" only once in the time slot of the corresponding channel in the next time division channel cycle. The key-off pulse KOFP is the key-on signal KON
Falls from "1" to "0", that is, at the time of key release, "1" only once in the time slot of the corresponding channel.
It is a pulse that becomes These pulses are given to each circuit in order to control processing synchronized with key-on and key-off.

The parameter data generating circuit 94 sets the tone of the musical tone, performs touch control, and performs key scaling based on the tone color number data TN, the touch data TD, and the key code KC provided from the interface 90. To generate various parameter data. An example of parameter data generated in consideration of the selected timbre, key touch, and key scaling is as follows. Envelope setting data EVD for setting an envelope, start address data SA for designating a waveform reading start address, first address There are initial data length data ILENG indicating the data bit length of the first frame of the block, compression coefficient data ICO for the first block, shift data ISF for the first block, and the like. Of these parameter data, those stored in the header of the waveform memory 15 are read out via the waveform memory interface 16.

The envelope generator 95 generates and outputs envelope waveform data ED in a time division manner for each channel based on the key-on pulses KONP1 and KONP2, the key-off pulse KOFP and the envelope setting data EVD. The data retrieval / reproduction unit 96 includes the accumulator 9
In response to the note clock pulse NCL given from step 2, the sample point increment for specifying the sample point number of the data to be read from the waveform memory 15 is performed.
Based on the sample point number and the data length of the data to be read, an address at which the data to be read is stored is specified, and an address signal CA is generated. Since this address signal CA is a relative address in the area where the waveform data corresponding to one tone color is stored, the generated address signal is added to the start address data SA, which is an absolute address, to add the generated address signal to the absolute address. The signal is converted into a signal, and this is input to the waveform memory 15 as an address. The waveform memory 15 reads out 16-bit storage data from one storage address in accordance with the input address signal.

The data fetching / reproducing section 96 stores the 16-bit data R read from the waveform memory 15.
D is input, and data of one required sample point having a variable bit length is extracted therefrom. If data for one necessary sample point is stored over a plurality of addresses, necessary data is connected and taken out from data read from the plurality of addresses. Further, the data extracting / reproducing unit 96 includes the waveform memory 1
5, "hidden bit" data is extracted from the 16-bit data read out, and these are connected to form hidden bit data HB0 to HB3 and HS0 to HS.
3. Provide a complete set of HC0 to HC7, and extract bit number indication data for each frame, shift data for each block, and compression coefficient data for each block stored in the waveform memory 15 as "hidden information" . Using the bit number indication data extracted from the hidden bits, the waveform memory 1
From the 16-bit data read out from No. 5,
A process of extracting data of one sample point having a variable bit length is performed. In the first frame, the variable length data for one sample point is extracted by using the initial data length data ILENG from the parameter data generation circuit 94.

The waveform sample data CWD extracted by the data extracting / reproducing section 96 is input to a compressed data demodulation circuit 97, and the ordinary PCM-encoded waveform data W
Demodulate to D. In this case, the compression demodulation of the waveform data in the corresponding block section is performed using the compression coefficients a0, a1, b0, and b1 extracted from the hidden bits. In the first block section, a demodulation operation is performed using the initial compression coefficient data ICO from the parameter data generation circuit 94. The waveform sample data WD output from the compressed data demodulation circuit 97 is input to the shift circuit 98 and is restored to the weight common to all blocks. In this case, a process of restoring the weight of the waveform data of the corresponding block section using the shift data SFD extracted from the hidden bits is performed. In the first block section, shift data SFD is generated using the initial shift data ISF from the parameter data generation circuit 94, and a weight restoration operation is performed. The data shift direction by the shift circuit 98 is just opposite to the shift direction by the shift circuit 47 in FIG.

The waveform data output from the shift circuit 98 is multiplied by the envelope waveform data ED from the envelope generator 95 in the multiplier 99, and the volume amplitude level is controlled according to the envelope waveform. The reproduction and control of the waveform data up to the multiplier 99 is performed in a time-division manner for each channel. And sum the tone waveform data of all channels. This output is the digital / analog converter 2
4 (FIG. 2) and is acoustically pronounced via the sound system 25.

--- Description of Data Extraction / Reproduction Unit-- FIG. 16 is a block diagram showing an example of the internal configuration of the data extraction / reproduction unit 96. A note clock pulse NCL for instructing data reading for each sample point is provided by a sample counter. 101, a data length counter 102, an address counter 103, a data position reproducing circuit 104, a hidden bit reproducing circuit 105, and a data register 106. The sample counter 101 counts the note clock pulse NCL, and sets the number of the sample point to be reproduced to 1
Sample number SN indicated by relative number in block
Is output. FIG. 17 shows a detailed example of this. The sample counter 101 includes an adder 107 and an adder 107.
And an 8-stage / 4-bit shift register 108 for dynamically storing the addition result of each channel in synchronization with the time-division timing, and a gate 109 for gating the output of the shift register 108. The output of the gate 109 is input to the adder 107, and is added to the note clock pulse NCL applied to another input of the adder 107. The output of the gate 109 is output as the sample number SN.
The 10-bit sample number SN specifies relative sample numbers 0 to 1023 in one block. Also,
The gate 109 is closed by the second key-on pulse KONP2, but is open otherwise. The display “8D” in the block of the shift register 108
Indicates that there are eight stages, and the shift control is performed by the two-phase system clock pulse in synchronization with the channel time division timing. The same applies to the other shift registers marked “8D”.

With this configuration, the sample counter 101
Is cleared once at the beginning of key press by the second key-on pulse KONP2, and thereafter, the note clock pulse NCL
Is generated, and a sample number SN indicating the number of the sample point to be reproduced is designated by relative numbers 0 to 1023 in one block. The generated sample number SN is input to the hidden bit control signal generation circuit 110. The hidden bit control signal generation circuit 110 outputs each hidden bit data H
It recognizes the sample numbers to which B0 to HB3, HS0 to HS3, and HC0 to HC7 are assigned. First, in order to recognize the first four sample numbers in one frame to which hidden bit data HB0 to HB3 corresponding to the bit number data of each frame consisting of 4 bits are assigned,
A NOR gate 111 is provided. Of the 10-bit sample number SN, the least significant 4 bits S0, S1,.
S2 and S3 identify 16 sample points in one frame, and the upper two bits S2 and S3 are input to the NOR gate 111. At the first four sample points in one frame, the two bits S2 and S3 of the sample number SN are both "0" and the output of the NOR gate 111 is "1". 1
The output of 11 is "0". The output of the NOR gate 111 is supplied to another circuit as a hidden bit control signal HBC1 of the bit number data. It is shown that. The lower 4 bits S0, S1, S2, S3 of the sample number SN are input to the AND gate 112, and at the last sample point of the frame, these bits S0 to S3 are all "1".
The output of the AND gate 112 becomes "1", and this is given to another circuit as the frame change signal HBC2.

In order to recognize four sample numbers from the fifth to the eighth in the first frame of each block to which hidden bit data HS0 to HS3 corresponding to the shift data of each block of 4 bits are allocated. In addition, a NOR gate 113 and an AND gate 114 are provided.
Top 4 of sample number SN consisting of 10 bits
Bits S6, S7, S8, and S9 are input to NOR gate 113. During the first four frames (frames 0 to 3) in one block, the most significant four bits S6, S7, S8, S9
Are all “0”, and the output of the NOR gate 113 is “1”. The output signal of the NOR gate 113, the third bit S2 of the sample number SN, and the bits S3, S from the fourth bit to the sixth bit of the sample number SN
The signal obtained by inverting S4 and S5 is the AND gate 114
Is input to The output of the NOR gate 113 is "1", the bit S2 is "1", and the bits S3, S4 and S5 are all "0" because of the four frames from the fifth frame to the eighth frame of the first frame 0 of the block. Sample numbers 4, 5, 6, 7
It is time. At that time, the output of the AND gate 114 becomes "1", which is supplied to another circuit as the shift data hidden bit control signal HSC.

The first four frames (frames) of each block to which the hidden bit data HC0 to HC7 corresponding to the four compression coefficient data a0, a1, b0, and b1 for each block of 8 bits are assigned. In order to recognize eight sample numbers from ninth to sixteenth in 0-3), NOR gate 113 and AND gates 115-11
8 are provided. As described above, the output of the NOR gate 113 is “1” during the first four frames (frames 0 to 3) in one block. This NOR gate 113
And the fourth bit S3 of the sample number SN
The signal obtained by inverting the fifth and sixth bits S4 and S5 of the sample number SN is input to the AND gate 115. The output of the NOR gate 113 is "1", the bit S3 is "1", and the bits S4 and S5 are "0" because of the eight sample numbers 8 to 16 of the first frame of the block. It is at the time of 15. At that time, the output of the AND gate 115 becomes "1", which is the hidden bit control signal HC for the compression coefficient b1.
It is given to other circuits as b1. As shown in FIG. 12, these sample numbers 8 to 15 are assigned hidden bit data HC0 to HC7 of the compression coefficient b1.

The output signal of the NOR gate 113, the signal obtained by inverting the fourth bit S3, the fifth bit S4, and the sixth bit S5 of the sample number SN are the AND gate 1
16 is input. The output of NOR gate 113 is "1"
And bits S3 and S4 are "1" and bit S5 is "0".
Is obtained for eight sample numbers 24 to 31 from the ninth to sixteenth frames of the second frame of the block. At that time, the output of the AND gate 116 becomes "1", which is the hidden bit control signal HCb0 for the compression coefficient b0.
As given to other circuits. As shown in FIG. 12, these sample numbers 24-31 are assigned hidden bit data HC0-HC7 of the compression coefficient b0. Similarly, the output signal of the NOR gate 113 and the sample number S
A signal obtained by inverting the fourth bit S3 and the sixth bit S5 of N and the bit S4 of the fifth bit is input to the AND gate 117. Ninth to 1 in third frame of block
At the eight sample numbers 40 to 47 up to the sixth, the output of the AND gate 117 becomes "1", which is given to another circuit as a hidden bit control signal HCa1 for the compression coefficient a1. The output signal of the NOR gate 113 and the fourth to sixth bits S3, S4, S5 of the sample number SN are input to the AND gate 118. The output of the AND gate 118 becomes "1" at the eight sample numbers 56 to 63 from the ninth to sixteenth frames of the fourth frame of the block, and this is output to another circuit as a hidden bit control signal HCa0 for the compression coefficient a0. Given.

Each of the hidden bit control signals HBC1 to HCa0
Are OR-combined by an OR gate 137, and a hidden bit control signal HC indicating presence of a hidden bit is output. All bits of the sample number SN are given to the AND gate 119,
At the time of the last sample number 1023 of the block, the output of the AND gate 119 becomes "1", which is supplied to another circuit as a block end control signal BFC.

Returning to FIG. 16, the data length counter 102
Is a modulo 16 counter that inputs data length instruction data LENG output from the data register 106 and accumulates the data at each timing of the note clock pulse NCL. This modulo number 16 corresponds to the bit number 16 of one address in the waveform memory 15. Therefore, the count value of the data length counter 102 indicates a boundary of the variable length data in the memory address. A detailed example of this is shown in FIG.
02 denotes an adder 120, a selector 121 that inputs the addition result of the adder 120 to a “1” input, and a selector 12
An 8-stage / 4-bit shift register 122 for inputting the output of 1 and dynamically storing the data for each channel in synchronization with the time division timing, and a gate 123 for gating the output of the shift register 122 are provided. The output of the gate 123 is input to the adder 120, and is added to the data length indication data LENG added to the other inputs of the adder 120.
The output of the gate 123 is input to the “0” input of the selector 121. The gate 123 is closed by the second key-on pulse KONP2, but is open otherwise. The selector 121 selects the addition result of the adder 120 added to the “1” input when the note clock pulse NCL is generated (when “1”), and inputs the “0” when it is not generated (when “0”). Select and hold the count value added to.

With this configuration, the data length counter 102
Is cleared once at the beginning of key press by the second key-on pulse KONP2, and thereafter, the note clock pulse NCL
The data length indication data LENG is accumulated each time.
The data length indication data LENG indicates the net data length of the waveform data portion, that is, the number of bits, and does not indicate the data length including the hidden bits HB0 to HC7. In order to add the actual data length at the sample points including the hidden bits HB0 to HC7, the above-mentioned hidden bit control signals HBC1, HSC, HCb1, HCb0, H
The signal HC obtained by OR-combining Ca1, HCa0 is added to the adder 12
A carry-in input Cin of 0 is input, and 1 is added as a hidden bit. Data length counter 1
02 is output from the gate 123, and this is the pull-out pointer (fetch pointer) POP.
As given to other circuits. This pull-out pointer POP indicates the bit position in the storage address where the least significant bit of the data of one sample point to be taken out is located.

For example, in the case of FIG. 13, the pull-out pointer POP at the first sample point 0 indicates "0", that is, the least significant bit 0 of the storage address by clearing with the key-on pulse KONP2. Next, when the timing of the note clock pulse NCL arrives, 11 of the data length instruction data LENG and the hidden bit control signal HBC1
Is added by the adder 120, and POP = 12, indicating bit 12 of the storage address. Next, when the timing of the note clock pulse NCL arrives, 12
Since + 12 = 24, “1” is generated in the carry-out output Cout by the adder 120, and the addition result becomes 8,
Indicates bit 8 of the storage address. As described above, the pull-out pointer POP indicates the bit position in the storage address where the least significant bit of the data of one sample point to be taken out is located.

Carry out output Cou of adder 120
The signal of t is an address increment pulse ADINC
Is output from the data length counter 102. The address counter 103 performs an address count for reading the waveform memory 15 based on the address increment pulse ADINC and the note clock pulse NCL, and outputs an address signal CA which is a relative value of a read address. Address increment pulse ADINC generated at the timing of note clock pulse NCL
Is an effective address increment pulse, and the address is counted up by one.

FIG. 18 shows a detailed example of this. The address counter 103 includes an 8-stage / 1-bit shift register 124 for delaying the note clock pulse NCL.
AND gate 1 receiving the output of shift register 124 and address increment pulse ADINC
25, an adder 126 to which the output of the AND gate 125 is input to one side, a gate 127 for gating the addition result of the adder 126, And an 8-stage / 22-bit shift register 128 for dynamically storing data. The output of the shift register 128 is the adder 12
6 and is added to the output of the AND gate 125. Further, key-on pulses KONP1 and KONP2 are input to the NOR gate 1294, and the output thereof outputs the gate 1 pulse.
27 is controlled.

In the data length counter 102, the timing at which a carry-out output is generated from the adder 120 is as follows.
Since the delay of the shift register 122 delays the timing of the note clock pulse NCL by eight system clocks, the shift register 124 delays the note clock pulse NCL by eight system clocks to match this. Therefore, at the timing of the note clock pulse NCL, the data length instruction data LEN
As a result of adding G, the address increment pulse AD
When INC occurs, the output of the AND gate 125 becomes "1".
And the address counter 103 counts up one address. In the address counter 103, the gate 12
7 is output as an address signal CA.

For example, in the case of the example of FIG. 13, the address signal CA initially indicates "0", that is, the storage address A0 by clearing with the key-on pulses KONP1 and KONP2. Is read. Next, note clock pulse NCL
Comes, the addition output of the adder 120 of the data length counter 102 becomes 12, as described above, which is selected by the selector 121 and
And after 8 system clocks, POP = 12 is output. At this time, the adder 120 further adds 12 and the carry-out output Cout becomes "1", and the note clock pulse NCL delayed by 8 system clocks with "1" of the address increment pulse ADINC.
Are added to the AND gate 125, and the address counter 1
03 is counted up. Therefore, the address signal C
A indicates "1", that is, the storage address A1, and the 16-bit data stored at this address A1 is read. On the other hand, the selector 121 does not select the output of the adder 120, and the output POP of the data length counter 102 maintains 12.

As can be understood, the sample number 1 stored over the two addresses A0 and A1
, The pull-out pointer POP indicates the bit 12 in the address A0 where the least significant bit of the data is located, and the output address signal CA of the address counter 103 specifies the next address A1. That is, the address signal CA precedes the pull-out pointer POP by one address. this is,
As will be described later, the data position reproducing circuit 104 stores the data of the previous address read from the waveform memory 15 in order to reproduce the data of one sample point stored over the two addresses. This is because the pull-out pointer POP is temporarily held and indicates the least significant bit of data to be taken out for the read data of the previous address thus temporarily held.

The data position reproducing circuit 104 receives 16-bit data RD read from the waveform memory 15 and (a) prepares one sample point of data stored over two addresses. And (b) aligning the bit position of the data in accordance with the least significant bit of the variable bit length data, so that the variable bit length can be selected from the 16-bit data. And performs a pre-processing for extracting only a necessary portion of the data for one sample point. This detailed example is shown in FIG. 19, and the data position reproduction circuit 104 includes a shifter 130 having a 32-bit parallel input / 16-bit parallel output. The 16-bit data RD read from the waveform memory 15 is directly input to the upper 16 bits of the shifter 130. The read data RD is applied to the “0” input of the selector 131, and the output of the selector 131 is input to the 8-stage / 16-bit shift register 132, and the shift register 1
The output of 32 is added to the “1” input of the selector 131 and is applied to the lower 16 bits of the shifter 130. Note clock pulse NCL and key-on pulse KONP1
Is added to the NOR gate 133. When the output signal of the NOR gate 133 is "0", the "0" input of the selector 131 is selected, and when the output signal is "1", the "1" input is selected.

The control input of shifter 130 includes pull-out pointer PO from data length counter 102 in FIG.
P is input. This pull-out pointer POP
Is one of the 32-bit parallel input data of the shifter 130.
A bit corresponding to the least significant bit of data to be taken out as 6-bit parallel output data is indicated. For example, PO
If P = 0, the least significant bit of the 32-bit parallel input data is taken as the least significant bit of the 16-bit parallel output data, and the upper 16-bit data is extracted therefrom. Also,
If POP = 1, the second lower bit of the 32-bit parallel input data is taken as the least significant bit of the 16-bit parallel output data, and the upper 16-bit data is extracted therefrom. If POP = 12, the 13th bit from the bottom of the 32-bit parallel input data is taken as the least significant bit of the 16-bit parallel output data, and the upper 16-bit data is extracted therefrom.

Of the 32-bit parallel input of the shifter 130, the upper 16 bits are data RD currently read from the waveform memory 15, and the lower 16 bits input from the shift register 132 are read from the immediately preceding address. Data. Therefore, the read data of two addresses is arranged in the shifter 130. When the data of one sample point is stored over two addresses, the sum of the two addresses arranged in the shifter 130 is calculated. The necessary data of one sample point can be extracted from the 32-bit parallel data. Further, since the pull-out pointer POP indicates the least significant bit of the variable bit length data, the input bit position of the data to be extracted as the least significant bit of the 16-bit parallel output data is determined by the pull-out pointer POP. , It is possible to perform a process of aligning the bit position of the data in accordance with the least significant bit of the variable bit length data.
It is possible to perform preprocessing for extracting only a necessary portion of data of one sample point having a variable bit length from 16-bit data.

FIG. 13 shows an example. When the first key-on pulse KONP1 is generated, the address counter 103 shown in FIG. 18 is cleared, the address signal CA becomes "0", and data is read from the address A0. At this time, the selector 131 outputs the read data RD from the address A0 by the output “0” of the NOR gate 133.
Is selected and loaded into the shift register 132. In the next cycle, the selector 131 selects the output of the shift register 132 based on the output “1” of the NOR gate 133, and stores and holds the read data RD from the address A0. At this time, the pull-out pointer POP is “0”,
The lower 16 bits of the input of the shifter 130, that is, the read data from the address A0 held in the shift register 132 are selected and output as they are. This completely includes the data at the sampling point 0 in the lower 12 bits. That is, the least significant bit of the data at the sampling point 0 to be extracted first is completely extracted in accordance with the least significant bit of the 16-bit output. This is schematically shown in FIG. 20 (a).

Next, when the note clock pulse NCL is generated, the pull-out pointer POP becomes "12" after eight system clocks as described above, and the address signal CA switches to the address A1 (see FIG. 18). .
However, since the note clock pulse NCL input to the NOR gate 133 is not delayed, when the output of the NOR gate 133 becomes “0” due to the note clock pulse NCL, the address signal CA has not yet changed, and the address A0 is not changed. Is read by the selector 131 and stored in the shift register 132. Therefore, after eight system clocks, the read address of the waveform memory 15 changes to A1, and when the read data RD of A1 is input to the upper 16 bits of the shifter 130, the lower 16 bits of the shifter 130 have the previous address A0. Is provided from the shift register 132. In this way, the read data of two consecutive addresses are arranged at the input of the shifter 130. At this time, the pull-out pointer POP is “12” and indicates the position of the least significant bit of the data at the sample point 1 at the preceding address A0. This allows
The least significant bit of the data at sample point 1 is the least significant bit, and the 16-bit data above the least significant bit is extracted from shifter 130. This means that the data at sample point 1 is
It contains exactly 2 bits, so
Sampling point 1 stored separately in two addresses
Are aligned and the least significant bit is output aligned with the least significant bit of the 16-bit output. This is schematically shown in FIG. 20 (b). In this way, the shifter 130 outputs 16-bit data D1 in which the bit positions of the target variable data length data to be extracted are aligned in order from the least significant bit. Since the 16-bit data D1 sometimes includes unnecessary data on the upper bits,
This does not mean that only the data of the variable data length for one sample of interest is extracted. Therefore, further processing is required.

Referring back to FIG. 16, the data position reproducing circuit 10
The data D1 output from the shifter 130 of No. 4 is passed through the hidden bit separation circuit 134 to the data matching circuit 1
35 is input. When the data D1 includes the hidden bits HB0 to HC7, the hidden bit separation circuit 134 separates the hidden bits, and extracts only the net waveform data and inputs it to the data matching circuit 135 as data D2. The data matching circuit 135 is for extracting only the waveform sample data of a variable bit length for one target sample from the data D2. The one-bit hidden bit possibility signal HBP separated by the hidden bit separation circuit 134 (this is a signal that may be any one of the hidden bits HB0 to HC7) is input to the hidden bit reproduction circuit 105. Is done. Based on the hidden bit possibility signal HBP supplied from the hidden bit separation circuit 134, the hidden bit reproduction circuit 105 generates a set of hidden bit data HB0 to HB3, H
Regenerate S0 to HS3 and HC0 to HC7. Recovered hidden bit data HB0 to HB3, HS0 to HS3, HC0 to H
C7, that is, bit number data (data length indication data LENG) for each frame, shift data (weighting coefficient) and compression coefficient data a0, a1, b for the next block
0 and b1 are given to the data register 106.

A detailed example of the hidden bit separation circuit 134 and the data matching circuit 135 is shown in FIG. In this embodiment, the bit length, that is, the size of the net waveform sample data is variable in the range of 2 bits to 15 bits. Therefore, the maximum bit length of valid data is
16 bits when hidden bits are included, and 15 bits when hidden bits are not included. Therefore, the maximum data length of the valid data of the data D1 that may include hidden bits is 16 bits, and therefore, the data D1 is extracted in a 16-bit configuration. The maximum bit length of the effective data of the data D2 after the hidden bit separation is 15 bits. Also, 1
It is assumed that the most significant bit of the variable-length waveform data for the sample is a sign bit.

Referring to FIG. 21, hidden bit separation circuit 13
4 comprises a selector 138 which inputs the lower 15 bits of the data D1 to the "0" input and the upper 15 bits of the data D1 to the "1" input. Selector 138
Inputs the above-mentioned hidden bit control signal HC (see FIG. 17) to the selection control input, selects the "1" input when HC is "1", and selects the "0" input when HC is "0". Therefore,
When extracting the data of the sample point including the hidden bits HB0 to HC7, the upper 15 bits of the data D1 are selected by the HC "1", and the hidden bits HB0 to HC7 in the least significant bit are excluded. This 15-bit data is
As described above, the data is enough to secure the effective bits of the net waveform data. On the other hand, hidden bits HB0-H
When extracting data of sample points not including C7,
The lower 15 bits of the data D1 are selected according to "0" of HC. This 15-bit data is also enough data to secure valid bits of the net waveform data as described above. The 15-bit net waveform data D2 obtained by separating the hidden bits in this manner is supplied to the data matching circuit 13
5 is input. As described above, this data D2 may include not only the waveform data of the target one sample point but also a part of the waveform data of the next sample point.

In data matching circuit 135, data D2
In order to extract only the waveform data of the target one sample point from the data, if the data size is extracted with a variable length, there is an inconvenience in later data processing. Therefore, the data size is adjusted to a fixed-length data size of 15 bits. I am trying to do it. For this purpose, first, only the waveform data of the target one sample point is extracted from the data D2, and then the extracted 1
If the waveform data at the sample point alone does not satisfy the fixed-length data size of 15 bits, a process of extending the sign bit to all the remaining upper bits is performed.
The entire data size is adjusted to a fixed length of 15 bits while extracting only the variable-length target waveform data of one sample point. In the data matching circuit 135 of FIG. 21, the data D2 is input to the sign bit extracting circuit 139, and the sign bit SB is extracted.
The data length indication data LENG is decoded by the decoder 140, and one output line corresponding to the most significant bit of the variable length data among the 15 decode output lines becomes a signal "1". The output of the decoder 140 indicates the position of the code bit SB to be extracted by the code bit extraction circuit 139. For example, when the bit length is 10 bits, the 10th bit of the data D2 is the most significant bit of the variable length data, that is, the sign bit SB, which is extracted according to the signal “1” of the 10th output line of the decoder 140. It is.

In the data matching circuit 135 of FIG. 21, the bit-by-bit independent selector 141 selects only the target waveform data for one sample point, and excludes some data of other sample points. Instead, the sign bit S
B is to be extended. Lower 14 of data D2
Of the bits (the most significant bit can be only the sign bit SB, which can be set here by the output of the sign bit extracting circuit 139 and thus can be excluded here), the data of the least significant bit 0 is always one target sample. Since the waveform data corresponds to points, the data may not be input to the selector 141 but may be directly input to the output register 142. The data of bits 1 to 13 other than the least significant bit 0 of the lower 14 bits of the data D2 are A-inputs 1A to 13A for each bit of the selector 141.
Respectively. Sign bit extraction circuit 139
The signal of the sign bit SB extracted from the
Common inputs are made to the 1-bit-specific B inputs 1B to 13B. The selection control for each bit of the selector 141 is performed by 13 signal lines provided from the select signal generation circuit 143, respectively. Select signal generation circuit 143
Is the code bit S according to the output signal of the decoder 140.
A selection control signal "1" is applied to all the upper bits from the bit position of B.

For example, assuming that the sign bit SB is the lower second bit 1 of the data D2, all 13 signal lines of the select signal generation circuit 143 are set to "1". The code bits SB of the B inputs 1B to 13B are selected by bits. If the sign bit SB is the lower third bit 2 of the data D2, the lower one signal line of the select signal generation circuit 143 is set to "0", the upper 12 signal lines to "1", and In the separate selector 141, the waveform data of the A input 1A is selected by the bit 1 and the B input 2B-1 by the bits 2 to 13.
Select 3B sign bit SB. Also, the sign bit S
Assuming that B is the lower fourth bit 3 of the data D2, the lower two signal lines of the select signal generation circuit 143 are set to "0", the upper eleven signal lines are set to "1", and the bit-by-bit independent selector 141 is set. Then, the A input 1A, 2 in bits 1 and 2
A waveform data is selected, and B input 3B with bits 3 to 13
Select the code bits SB of .about.13B. Hereinafter, as the position of the sign bit SB is shifted, the bit-by-bit selection mode is similarly shifted, and after all, only the target waveform data of one sample point is selectively extracted, and the data of the other sample points are excluded. Instead, extending the sign bit SB is achieved.

The least significant bit of data D2 and selector 14
1 and the sign bit SB extracted from the sign bit extracting circuit 139, a total of 15-bit data is input to the output register 142, and the register 142 is output at the rising timing of the system clock pulse φ2.
It is taken in. The rising timing of the system clock pulse φ2 is in the middle of one time slot of the time division channel timing, and the data is taken in a state where the data at the time division channel timing has sufficiently risen. The output of the output register 142 is output as the waveform data CWD for one sample from which extraction has been completed. FIGS. 22 and 23 show a detailed example of the hidden bit reproducing circuit 105 and the data register 106. FIG. The hidden bit reproduction circuit 105 and the data register 106 are provided corresponding to the types of the hidden bits. In FIG. 22, a hidden bit reproduction circuit 105A for “bit number data” and a data register 106A
Bit recovery circuit 10 for "shift data"
5B and a detailed example of the data register 106B are shown. FIG.
3, the hidden bit reproducing circuits 105C to 105F and the data register 10 for the respective compression coefficients b1, b0, a1, a0.
The detailed example of 6C-106F is shown.

As shown in FIG. 22, hidden bit reproducing circuit 105A for "bit number data" and data register 10
6A, the hidden bit reproducing circuit 105A
Is an AND gate 145 to which a note clock pulse NCL is delayed by an 8-stage / 1-bit shift register 144 and a hidden bit control signal HBC1 is input,
Second key-on pulse KNOP2 and AND gate 145
An OR gate 146 to which the output of the OR gate 146 is input, a selector 147 controlled by the output of the OR gate 146, and an 8-stage / 4-bit shift register 148 to which the output of the selector 147 is input. The output of the shift register 148 is directly added to the “0” input of the selector 147. Of the four bits of the “1” input of the selector 147, the most significant bit is supplied with the signal of the least significant bit of the data D 1 output from the shifter 130, that is, the hidden bit possibility signal HBP. Of the four bits of the “1” input of the selector 147, the remaining lower three bits are obtained by shifting the output of the shift register 148 one bit lower.

With this configuration, first, when the second key-on pulse KONP2 becomes "1", the OR gate 1
The “1” input of the selector 147 is selected by the output “1” of 46. At this time, the data of the sample number 0 read from the address A0 is given as the data D1 based on the address clear by the first key-on pulse KONP1 generated one cycle before, and the hidden bit possibility signal HBP hidden is bit HB0 stored with the sample number 0 is given. The output of the shift register 148 because any value of the beginning,
It will be described as x (x may be either 0 or 1). As a result, HB0, x, x, x
The 4-bit data having the content “1” of the selector 147
The data is taken into the shift register 148 via the input. In the next cycle, the output of the OR gate 146 becomes “0”,
The data HB0 fetched into the shift register 148,
x, x, and x are held in the shift register 148 via the “0” input of the selector 147.

Next, when the note clock pulse NCL is generated and the data of the sample number 1 is provided as the data D1, "1" of the HBC1 and the delay output "1" of the note clock pulse NCL (shift register 14)
4 is to synchronize with HBC1: FIG.
7), the output of the AND gate 145 becomes “1”, the output of the OR gate 146 becomes “1”, and the “1” input of the selector 147 is selected. At this time, the hidden bit HB1 stored along with the sample number 1 is given as the hidden bit possibility signal HBP, so that 4-bit data having the contents of HB1, HB0, x, x from the upper bits is input to the selector 147 at the "1" input. Through the shift register 14
8. In the next cycle, the output of the OR gate 146 becomes “0”, and the data HB 1, HB 0, x, x captured in the shift register 148 is held in the shift register 148 via the “0” input of the selector 147. Next, a note clock pulse NCL is generated and the data D
When the data of the sample number 2 is provided as 1, the hidden bit HB2 stored with the sample number 2 is provided as the hidden bit possibility signal HBP, and HB2, HB1, HB0, and x are shifted by the shift register in accordance with the above. 148 and is held.

Further, when the note clock pulse NCL is generated and the data of the sample number 3 is provided as the data D1, the hidden bit HB3 stored with the sample number 3 is provided as the hidden bit possibility signal HBP. As described above, HB3, HB2, HB1, and HB0 are taken into the shift register 148 and held. Thereafter, within that frame, the note clock pulse NCL
Occurs, the output of the AND gate 145 does not become "1" because the hidden bit control signal HC1 is "0", and the above-mentioned HB3, HB2, HB1, and HB0 are held in the shift register 148. Thus, the four hidden bits HB3,
HB2, HB1, HB0 are reproduced, and the shift register 14
8 is held. This is given to the data register 106A as hidden information HD indicating the data bit length of the next frame.

The data register 106A has 8 stages /
It includes a 4-bit shift register 149 and a selector 150. The initial data length data ILENG is input to the “10” input of the selector 150, and “01” is input.
The hidden information HD, that is, data indicating the data bit length of the next frame is input to the input, and the output of the shift register 149 is input to “00”. Selector 150
The first key-on pulse KONP1 is input to the upper bits, and the output of the AND gate 151 is input to the lower bits. The frame change signal HBC2 and the note clock pulse NCL from the AND gate 112 in FIG. 17 are applied to the AND gate 151. With this configuration, first, the key-on pulse KONP1 becomes “1”.
, The selector 150 selects the initial data length data ILENG of the “10” input, and
Take in 9. In the next cycle, the selector 150 sets “0”.
"0" input is selected and the captured data ILENG is held. The output of the shift register 149 is supplied to each circuit as the data length instruction data LENG as described above.
Therefore, in the first frame 0, the initial data length data IL given from the parameter data generation circuit 94
ENG is used as data length indication data LENG. In frame 0, as described above, hidden information HD indicating the data bit length of the next frame is provided to selector 150.

Next, when the frame is switched, the output of the AND gate 151 becomes "1", the selector 150 selects the information HD of "01" input, and
Take in 9. In the next cycle, the selector 150 sets “0”.
Select "0" input and hold the captured data HD.
Thus, in the second and subsequent frames, the hidden information HD indicating the data bit length stored as hidden information together with the waveform data of the previous frame is transmitted to the data length indicating data LE.
Used as NG. First key-on pulse KONP1
May be delayed by 8 system clocks by an 8-stage / 1-bit shift register 152 to generate a second key-on pulse KONP2. The hidden bit reproduction circuit 105B for shift data and the data register 106B have substantially the same configuration as the above-mentioned hidden bit reproduction circuit 105A and data register 106A. The difference is that the AND gate 1 corresponding to the AND gate 145
The point that the hidden bit control signal HSC for the shift data output from the AND gate 114 of FIG. AND gate 1 corresponding to AND gate 151
The point is that the block end control signal BFC output from the AND gate 119 of FIG. 17 is input to 51B. As a result, the shift register 148B stores the hidden bit data HS corresponding to the shift data for the next block.
3, HS2, HS1, and HS0 are reproduced and stored, and are taken into the shift register 149B at the end of the block. Therefore, the shift register 149B outputs shift data SFD relating to the block currently being processed.

In FIG. 23, hidden bit reproducing circuit 105C for compression coefficient b1 and data register 106C
Has almost the same configuration as the above-mentioned hidden bit reproduction circuit 105B and data register 106B. The difference is that the shift register 148C, 149C has 8 bits, and the AND gate 145C corresponding to the AND gate 145B has hidden bit control for the compression coefficient b1 output from the AND gate 115 of FIG. The point at which the signal HCb1 is input and the initial data given to the "10" input of the selector 150C are the initial compression coefficient I corresponding to b1.
CO. FIG.
7 and the block end control signal BFC output from the AND gate 119 is input. As a result, hidden bit data HC0 to HC7 corresponding to the compression coefficient b1 for the next block are reproduced and stored in the shift register 148C, and are taken into the shift register 149C at the end of the block. Therefore, from the shift register 149C,
The compression coefficient b1 for the block currently being processed is output. The hidden bit reproduction circuits 105D, 105E, and 105F and the data registers 106D, 106E, and 106F for the other compression coefficients b0, a1, and a0 have substantially the same configurations as the hidden bit reproduction circuit 105C and the data register 106C. The difference is that each of the AND gates 145D, 145E, and 145F corresponding to the AND gate 145C has
The point is that the hidden bit control signals HCb0, HCa1, HCa0 for the compression coefficients b0, a1, a0 output from the respective AND gates 116, 117, 118 in FIG. 17 are respectively input. Thereby, each of the registers 106D, 106E,
From 106F, compression coefficients b0, a1, and a0 relating to the block currently being processed are output, respectively.

--- One example of a compressed data demodulation circuit-- The waveform data CWD extracted and reproduced by the data extracting and reproducing unit 96 is compressed as shown in FIG. The data demodulation circuit 97 uses an LPC demodulation circuit. In this case, the compressed data demodulation circuit 97 outputs the LP data as shown in FIG.
It can be constituted by a C demodulation circuit. In the figure, 153 and 154 are limiters, 155 to 158 are adders, 159 to 162 are multipliers, and 163 to 166 are 8-stage shift registers. The configuration is the reverse of that of the compression filter circuit shown in FIG. 7, and the compression coefficients b0 and b1 of the second stage are used as demodulation coefficients of the demodulation circuit of the first stage.
The first-stage compression coefficient a is used as the demodulation coefficient of the first-stage demodulation circuit.
Use 0, a1.

—Another Example of Compression and Reduction Processing (Second Embodiment) — In the above embodiment, the data reduction processing using the weight coefficient (shift data) is performed before the data compression processing using the compression filter. Although it is performed, it may be performed later in the data compression process as described below. FIG.
Is the weighting factor (shift data) at the later stage of the data compression process
1 shows a configuration example of a circuit for a compression and reduction operation when performing a data reduction process according to FIG. The compression filter circuit has a cascade connection of secondary filters in two stages, as described above. The first-stage filter 48A includes a subtractor 170,
It comprises adders 171, 172, multipliers 173, 174, and delay units 175, 176. The second-stage filter 48B includes:
Subtracter 177, adders 178 and 179, multiplier 180,
181, delay units 182 and 183. The waveform data to be compressed is input to the subtractor 170 of the first-stage filter 48A, and the subtracter 170 subtracts the second-order convolution sum by the coefficients a0 and a1. Subtractor 1 of second stage filter 48B
The output of 77 is the output signal of the compression filter. The output signal of the compression filter is input to the shift circuit 47, and is weighted (shifted) in the direction of reduction by the weight coefficient (shift data). The output of the shift circuit 47 is temporarily stored in the block buffer 55 as compressed and reduced waveform sample data, and then written into the waveform memory 15.

The shift circuit 184 shifts the data by the same amount in the direction opposite to the shift direction of the shift circuit 47, and simulates the restoration of the weight during reproduction. Then, the output of this shift circuit 184 is added to delay units 175, 176 and 176 via adders 178 and 171.
182 and 183, whereby the multiplication operation of the compression coefficient is performed on the signal simulating the weight restoration at the time of reproduction. As a result, a high-precision compression filter operation that absorbs a data truncation error due to data shift-down can be performed. In the case of the second embodiment, the compression filter coefficients a0, a1, b0, b1
May be calculated by the same method as in the first embodiment. Since the position of the shift circuit 47 differs, the functional block diagram of FIG. 5 cannot be applied to the second embodiment in its entirety, but the shift circuit 47 and the compression filter unit 48 in FIG. The configuration may be appropriately changed so that the configuration described above can be implemented. In the case of the second embodiment, the procedure of the demodulation of the compressed data and the restoration of the weight at the time of reproduction are opposite to those of the first embodiment.
As shown in FIG. 26, the configuration of the sound source section 23 may be changed so that the shift circuit 98 is arranged before the compressed data demodulation circuit 97.

--- Modification Example-- Not limited to either the first or second stage of the data compression process,
It is also possible to perform data reduction processing using a weight coefficient (shift data) in both cases. Further, a data reduction calculation process using a weight coefficient (shift data) may be inserted in the middle of the data compression process. The weight calculation is not limited to the data shift, and may employ multiplication or division. The division of the waveform section is not limited to the one composed of blocks and frames as in the above embodiment, but may be any division. The variable bit length data according to the present invention must be
It is not necessary to write the data in the memory.
Further, the control data for reproduction (compression coefficient and weighting coefficient) is not limited to the form of the hidden bit, and may be given separately as appropriate. The data compression method is not limited to the LPC method.
Any other method such as M, ADPCM, and delta modulation may be adopted.

In the above embodiment, the present invention is applied to the musical tone waveform data. However, the present invention is not limited to this, and the envelope waveform data for setting the volume level, the envelope waveform data for various controls, or the time variation of the filter coefficient, etc. The present invention can be applied to various waveform data in an electronic musical instrument, such as various types of control data. Further, the present invention is not limited to waveform data in electronic musical instruments, but may be applied to compression of waveform data in other voice or sound processing devices. The present invention is not limited to waveform data, but can be applied to compression of digital data for tone control, that is, for sound control. According to the viewpoint of the variable bit length processing, the data compression processing and the data reduction processing by weight coefficient calculation as in the above embodiment are not essential to the present invention. That is, the present invention can be applied to compress the bit size of digital data that has not been subjected to special data compression processing.

In the above embodiment, the data take-out / playback section performs multi-stage processing steps such as sample count, data length count, address count, data position play, hidden bit play, etc., to take out and play one sample of data. This is necessary, and this is performed at the timing of one sample. Therefore, it may be necessary to take a long time for one sample. In order to solve this problem, it is preferable to execute processing over a plurality of sampling timings in the same channel timing by a pipeline processing method, so that the time of one sample is shortened and the data reading speed is increased. Can be. The present invention is not limited to a completed single electronic musical instrument, and may be applied to one component of a modularized electronic musical instrument. Further, the present invention can be applied to an apparatus which does not have a sound selection keyboard or switch means and generates a musical tone based on input of chord information. Furthermore,
The present invention can also be applied to a device for generating data relating to the formation or control of a tone signal without having a device for generating a tone signal or a speaker for acoustically generating a tone. Electronic musical instrument is a word used in a very broad sense. Further, the present invention can be applied to a general sound processing device or sound processing device.

[0112]

As described above, according to the present invention, waveform sample data consisting of a large number of samples or other musical tone control digital data is divided into a plurality of sections consisting of a plurality of samples. The maximum value of the number of effective bits is detected, and the lower bits of the number of bits corresponding to the maximum value detected in each section are extracted from all the bits of each data. Since waveform sample data aligned to the number of bits corresponding to the maximum value is obtained and stored in the storage device, the data bit size itself is most efficiently compressed without changing the data resolution. The effect is excellent. Accordingly, there is an effect that the storage device and the like can be saved and used efficiently. Furthermore, waveform sample data for each section
(Or other digital data for tone control)
Bit number indication data indicating the number of bits corresponding to the value
Each is divided into multiple parts, and each part is
The waveform sample data (or other
Of digital data for musical tone control)
The stored waveforms are stored in the
Sample data (or other digital data for tone control)
The data indicating the number of bits is efficiently stored between
It has an excellent effect that it can be Sand
That is, a memory for storing the bit number indication data exclusively.
Free bits in each address without occupying the address
And storing the bit number indication data separately at
To save more and use storage more efficiently
Can be achieved. Furthermore, the waveform data reproduction of the present invention
According to the device, the waveform sample data (and
Is other digital data for tone control) and bit number
From the storage device that stores the
Data and read the number of bits from the read data.
By extracting each part of the instruction data and collecting it
And reproduces the completed bit number indication data.
Bit number indication data for the next section, and
Further, the waveform sample data is obtained from the read data.
When taking out the data, the reproduced video for the section
The number of bits specified by the data
Since they were taken out of the data, Do that wave different number of bits
Shape data is appropriately extracted for the required number of bits and played back
Can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an overall flow of a waveform data compression / reproduction process according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a hardware configuration example of one embodiment of an electronic musical instrument that can be used for performing compression and reproduction processing of waveform data according to the present invention.

FIG. 3 is an exemplary flowchart showing an outline of an overall image of processing from compression of waveform data to writing to a memory executed under control of a microcomputer in the embodiment.

FIG. 4 is a view exemplifying a format of a storage area of compressed waveform data in the waveform memory of FIG. 2;

FIG. 5 is a functional block diagram showing one embodiment of waveform data compression and reduction processing performed under the control of the microcomputer of FIG. 2;

FIG. 6 is a diagram illustrating a memory format of a block buffer in FIG. 5;

7 is a diagram conceptually illustrating a configuration example of a shift circuit and a compression filter unit in FIG.

FIG. 8 is a diagram illustrating an example of a hardware circuit of a compression filter unit including a one-stage secondary filter.

FIG. 9 is a flowchart illustrating an example of a procedure of a generation operation of a compression filter coefficient according to a linear prediction method.

FIG. 10 is a functional block diagram for explaining a processing operation of a variable bit length processing and writing processing unit in FIG. 5;

FIG. 11 is a flowchart showing an outline of a procedure of variable bit length processing and writing processing executed by the variable bit length processing and writing processing unit.

FIG. 12 is a diagram showing an example of the data format of waveform sample data and hidden bit data after variable bit length processing.

FIG. 13 is a diagram showing an example of a memory format when data of a variable bit length having a format as shown in FIG. 12 is actually packed into a waveform memory and stored.

FIG. 14 is a view for explaining a process of packing variable-bit-length data and writing the data into a memory;

FIG. 15 is a block diagram showing one embodiment of a sound source unit in FIG. 2;

FIG. 16 is a block diagram showing an example of the internal configuration of a data retrieval / reproduction unit in FIG. 15;

17 is a block diagram showing a specific example of a sample counter and a hidden bit control signal generation circuit in FIG.

FIG. 18 is a block diagram showing a detailed example of a data length counter and an address counter in FIG. 16;

FIG. 19 is a block diagram showing a detailed example of a data position reproducing circuit in FIG. 16;

20 illustrates an operation example of the shifter in FIG.

FIG. 21 is a block diagram showing a detailed example of a hidden bit separation circuit and a data matching circuit in FIG. 16;

FIG. 22 is a block diagram showing a detailed example of a hidden bit reproduction circuit and a data register in FIG. 16;

FIG. 23 is a block diagram showing another detailed example of the hidden bit reproducing circuit and the data register in FIG. 16;

24 is a block diagram showing an example of a compressed data demodulation circuit in FIG.

FIG. 25 is a block diagram conceptually showing an embodiment in which a shift circuit for a data reduction operation is provided at a stage subsequent to a compression filter unit.

FIG. 26 is a block diagram showing an embodiment of a sound source unit for reproducing waveform data that has been subjected to compression and reduction processing according to the example of FIG. 25;

[Explanation of symbols]

13: Analog signal external input unit, 14: Sampling device, 15: Waveform memory, 21: Waveform buffer memory, 2
3 ... tone generator, 44 ... limited bit number register, 45 ... shift data generator, 46 ... shift data register, 47 ...
Shift circuit (weight calculation circuit), 48 ... compression filter section,
49: Hamming window multiplication unit, 51: Coefficient generation operation unit, 55
.., A block buffer, 56, a bit number detecting section, 58, a variable bit length processing and writing processing section, 76, a hidden bit assigning section, 78, a data synthesizing section, 96, a data extracting and reproducing section, 97, a compressed data demodulating circuit, 98: Shift circuit for weight restoration.

Claims (5)

(57) [Claims] A first step of providing digital waveform sample data of a predetermined number of bits composed of a large number of samples; dividing the waveform sample data composed of a large number of samples into a plurality of sections composed of a plurality of samples; A second step of detecting the maximum value of the number of effective bits of the waveform sample data each time, and the second step for each section of all bits of each waveform sample data provided in the first step. The lower bits corresponding to the number of bits corresponding to the maximum value detected in the step are respectively extracted, and waveform sample data aligned to the number of bits corresponding to the maximum value of the section for each section is thus obtained,
Bi showing a third step of storing it in the storage device, the number of bits corresponding to the maximum value of each of said sections
Storing the number-of-units instruction data in the storage device.
And the bit number indication data for each section
Each is divided into a plurality of parts, and each part is
Separating between the waveform sample data for the
Storing the waveform data in a storage device . 2. A first step of providing digital waveform sample data of a predetermined number of bits consisting of a large number of samples; and dividing the waveform sample data consisting of a large number of samples into a plurality of block sections consisting of a plurality of samples. A second step of performing data compression processing for each block section; and dividing the waveform sample data of each block section into a plurality of frame sections consisting of a plurality of samples, and performing the data compression processing for each frame section. A third step of detecting the maximum value of the number of effective bits of each of the waveform sample data provided in the second step; The lower bits for the number of bits corresponding to the maximum value detected in the step are respectively extracted, and thus To obtain waveform sample data aligned to the number of bits corresponding to the maximum value of the section between every, a fourth step of storing it in the storage device, corresponding the to the maximum value for each frame interval bit number
To store bit number indicating data indicating
The number of bits for each frame section
Divide the instruction data into multiple parts, and divide each part
The waveform for a frame section before the frame section
Separated between sample data and stored in the storage device
A waveform data compression method comprising: a fifth step . 3. A first step of providing digital data for tone control having a predetermined number of bits consisting of a large number of samples, and dividing the digital data consisting of a large number of samples into a plurality of sections consisting of a plurality of samples. A second step of detecting a maximum value of the number of effective bits of the digital data for each section; and a second step for each section of all bits of each digital data provided in the first step. A third step of taking out lower bits of the number of bits corresponding to the maximum value detected in step (1), and storing in the storage device digital data aligned in the number of bits corresponding to the maximum value of the section in each section. , bi indicating the number of bits corresponding to the maximum value of each of said sections
Storing the number-of-units instruction data in the storage device.
And the bit number indication data for each section
Each is divided into a plurality of parts, and each part is
Of the digital data for the
A digital data compression method for musical tone control, comprising: a fourth step of storing in a storage device . 4. The storage device storing the waveform sample data and the bit number indication data according to the method according to claim 1, reading means for reading each data stored in the storage device, Each part of the bit number indication data is extracted from the data read by the reading means, and the collected bit number indication data is collected to reproduce the completed bit number indication data. The reproduced bit number indication data is used for the next section. Bit number instruction data reproducing means for outputting the waveform sample data from the data read by the reading means, wherein the bits output from the bit number instruction data reproducing means for the section Waveform sample data extracting means for extracting the waveform sample data with the number of bits indicated by the number instruction data. Waveform data reproducing device. 5. The storage device storing the waveform sample data and the bit number indication data according to the method according to claim 2, reading means for reading each data stored in the storage device, Each part of the bit number indication data is taken out from the data read by the reading means, and the collected bit number indication data is collected to reproduce the completed bit number indication data. A number-of-bits instruction data reproducing means for outputting the waveform sample data from the data read by the reading means, and outputting the waveform sample data from the bit number instruction data reproducing means for the frame section. Waveform sample data acquisition for extracting the waveform sample data with the number of bits indicated by the bit number indication data A waveform data reproducing apparatus, comprising: output means; and demodulation means for decompressing data of the extracted waveform sample data.